[deliverable/linux.git] / arch / powerpc / platforms / chrp / pegasos_eth.c

/*
 *  Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de>
 *  Thanks to :
 *	Dale Farnsworth <dale@farnsworth.org>
 *	Mark A. Greer <mgreer@mvista.com>
 *	Nicolas DET <nd@bplan-gmbh.de>
 *	Benjamin Herrenschmidt <benh@kernel.crashing.org>
 *  And anyone else who helped me on this.
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/mv643xx.h>
#include <linux/pci.h>

#define PEGASOS2_MARVELL_REGBASE 		(0xf1000000)
#define PEGASOS2_MARVELL_REGSIZE 		(0x00004000)
#define PEGASOS2_SRAM_BASE 			(0xf2000000)
#define PEGASOS2_SRAM_SIZE			(256*1024)

#define PEGASOS2_SRAM_BASE_ETH_PORT0			(PEGASOS2_SRAM_BASE)
#define PEGASOS2_SRAM_BASE_ETH_PORT1			(PEGASOS2_SRAM_BASE_ETH_PORT0 + (PEGASOS2_SRAM_SIZE / 2) )


#define PEGASOS2_SRAM_RXRING_SIZE		(PEGASOS2_SRAM_SIZE/4)
#define PEGASOS2_SRAM_TXRING_SIZE		(PEGASOS2_SRAM_SIZE/4)

#undef BE_VERBOSE

static struct resource mv643xx_eth_shared_resources[] = {
	[0] = {
		.name	= "ethernet shared base",
		.start	= 0xf1000000 + MV643XX_ETH_SHARED_REGS,
		.end	= 0xf1000000 + MV643XX_ETH_SHARED_REGS +
					MV643XX_ETH_SHARED_REGS_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device mv643xx_eth_shared_device = {
	.name		= MV643XX_ETH_SHARED_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(mv643xx_eth_shared_resources),
	.resource	= mv643xx_eth_shared_resources,
};

static struct resource mv643xx_eth_port1_resources[] = {
	[0] = {
		.name	= "eth port1 irq",
		.start	= 9,
		.end	= 9,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv643xx_eth_platform_data eth_port1_pd = {
	.shared		= &mv643xx_eth_shared_device,
	.port_number	= 1,
	.phy_addr	= MV643XX_ETH_PHY_ADDR(7),

	.tx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1,
	.tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
	.tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,

	.rx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1 + PEGASOS2_SRAM_TXRING_SIZE,
	.rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
	.rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
};

static struct platform_device eth_port1_device = {
	.name		= MV643XX_ETH_NAME,
	.id		= 1,
	.num_resources	= ARRAY_SIZE(mv643xx_eth_port1_resources),
	.resource	= mv643xx_eth_port1_resources,
	.dev = {
		.platform_data = &eth_port1_pd,
	},
};

static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
	&mv643xx_eth_shared_device,
	&eth_port1_device,
};

/***********/
/***********/
#define MV_READ(offset,val) 	{ val = readl(mv643xx_reg_base + offset); }
#define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)

static void __iomem *mv643xx_reg_base;

static int Enable_SRAM(void)
{
	u32 ALong;

	if (mv643xx_reg_base == NULL)
		mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE,
					PEGASOS2_MARVELL_REGSIZE);

	if (mv643xx_reg_base == NULL)
		return -ENOMEM;

#ifdef BE_VERBOSE
	printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n",
		(void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base);
#endif

	MV_WRITE(MV64340_SRAM_CONFIG, 0);

	MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16);

	MV_READ(MV64340_BASE_ADDR_ENABLE, ALong);
	ALong &= ~(1 << 19);
	MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong);

	ALong = 0x02;
	ALong |= PEGASOS2_SRAM_BASE & 0xffff0000;
	MV_WRITE(MV643XX_ETH_BAR_4, ALong);

	MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000);

	MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
	ALong &= ~(1 << 4);
	MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);

#ifdef BE_VERBOSE
	printk("Pegasos II/Marvell MV64361: register unmapped\n");
	printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE);
#endif

	iounmap(mv643xx_reg_base);
	mv643xx_reg_base = NULL;

	return 1;
}


/***********/
/***********/
static int __init mv643xx_eth_add_pds(void)
{
	int ret = 0;
	static struct pci_device_id pci_marvell_mv64360[] = {
		{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) },
		{ }
	};

#ifdef BE_VERBOSE
	printk("Pegasos II/Marvell MV64361: init\n");
#endif

	if (pci_dev_present(pci_marvell_mv64360)) {
		ret = platform_add_devices(mv643xx_eth_pd_devs,
				ARRAY_SIZE(mv643xx_eth_pd_devs));

		if ( Enable_SRAM() < 0)
		{
			eth_port1_pd.tx_sram_addr = 0;
			eth_port1_pd.tx_sram_size = 0;
			eth_port1_pd.rx_sram_addr = 0;
			eth_port1_pd.rx_sram_size = 0;

#ifdef BE_VERBOSE
			printk("Pegasos II/Marvell MV64361: Can't enable the "
				"SRAM\n");
#endif
		}
	}

#ifdef BE_VERBOSE
	printk("Pegasos II/Marvell MV64361: init is over\n");
#endif

	return ret;
}

device_initcall(mv643xx_eth_add_pds);
Commit	Line	Data
bbd0abda	1	/*
bbd0abda PM	2	* Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de>
	3	* Thanks to :
	4	* Dale Farnsworth <dale@farnsworth.org>
	5	* Mark A. Greer <mgreer@mvista.com>
	6	* Nicolas DET <nd@bplan-gmbh.de>
	7	* Benjamin Herrenschmidt <benh@kernel.crashing.org>
	8	* And anyone else who helped me on this.
	9	*/
	10
	11	#include <linux/types.h>
	12	#include <linux/init.h>
	13	#include <linux/ioport.h>
	14	#include <linux/device.h>
300230dc	15	#include <linux/platform_device.h>
bbd0abda PM	16	#include <linux/mv643xx.h>
	17	#include <linux/pci.h>
	18
dd03d25f ND	19	#define PEGASOS2_MARVELL_REGBASE (0xf1000000)
	20	#define PEGASOS2_MARVELL_REGSIZE (0x00004000)
	21	#define PEGASOS2_SRAM_BASE (0xf2000000)
	22	#define PEGASOS2_SRAM_SIZE (256*1024)
	23
10156cea GP	24	#define PEGASOS2_SRAM_BASE_ETH_PORT0 (PEGASOS2_SRAM_BASE)
10156cea GP	25	#define PEGASOS2_SRAM_BASE_ETH_PORT1 (PEGASOS2_SRAM_BASE_ETH_PORT0 + (PEGASOS2_SRAM_SIZE / 2) )
dd03d25f ND	26
	27
	28	#define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
	29	#define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
	30
	31	#undef BE_VERBOSE
	32
bbd0abda PM	33	static struct resource mv643xx_eth_shared_resources[] = {
	34	[0] = {
	35	.name = "ethernet shared base",
	36	.start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
	37	.end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
	38	MV643XX_ETH_SHARED_REGS_SIZE - 1,
	39	.flags = IORESOURCE_MEM,
	40	},
	41	};
	42
	43	static struct platform_device mv643xx_eth_shared_device = {
	44	.name = MV643XX_ETH_SHARED_NAME,
	45	.id = 0,
	46	.num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
	47	.resource = mv643xx_eth_shared_resources,
	48	};
	49
10156cea	50	static struct resource mv643xx_eth_port1_resources[] = {
bbd0abda	51	[0] = {
10156cea	52	.name = "eth port1 irq",
bbd0abda PM	53	.start = 9,
	54	.end = 9,
	55	.flags = IORESOURCE_IRQ,
	56	},
	57	};
	58
10156cea	59	static struct mv643xx_eth_platform_data eth_port1_pd = {
fa3959f4	60	.shared = &mv643xx_eth_shared_device,
84dd619e	61	.port_number = 1,
10156cea	62	.phy_addr = MV643XX_ETH_PHY_ADDR(7),
fa3959f4	63
10156cea	64	.tx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1,
dd03d25f ND	65	.tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
	66	.tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
	67
10156cea	68	.rx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1 + PEGASOS2_SRAM_TXRING_SIZE,
dd03d25f ND	69	.rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
	70	.rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
	71	};
bbd0abda	72
10156cea	73	static struct platform_device eth_port1_device = {
bbd0abda PM	74	.name = MV643XX_ETH_NAME,
bbd0abda PM	75	.id = 1,
10156cea GP	76	.num_resources = ARRAY_SIZE(mv643xx_eth_port1_resources),
10156cea GP	77	.resource = mv643xx_eth_port1_resources,
bbd0abda	78	.dev = {
10156cea	79	.platform_data = &eth_port1_pd,
bbd0abda PM	80	},
	81	};
	82
	83	static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
	84	&mv643xx_eth_shared_device,
10156cea	85	&eth_port1_device,
bbd0abda PM	86	};
bbd0abda PM	87
dd03d25f ND	88	/***********/
	89	/***********/
	90	#define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); }
	91	#define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
	92
	93	static void __iomem *mv643xx_reg_base;
	94
	95	static int Enable_SRAM(void)
	96	{
	97	u32 ALong;
	98
	99	if (mv643xx_reg_base == NULL)
	100	mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE,
	101	PEGASOS2_MARVELL_REGSIZE);
	102
	103	if (mv643xx_reg_base == NULL)
	104	return -ENOMEM;
	105
	106	#ifdef BE_VERBOSE
	107	printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n",
	108	(void )PEGASOS2_MARVELL_REGBASE, (void )mv643xx_reg_base);
	109	#endif
	110
	111	MV_WRITE(MV64340_SRAM_CONFIG, 0);
bbd0abda	112
dd03d25f ND	113	MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16);
	114
	115	MV_READ(MV64340_BASE_ADDR_ENABLE, ALong);
	116	ALong &= ~(1 << 19);
	117	MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong);
	118
	119	ALong = 0x02;
	120	ALong \|= PEGASOS2_SRAM_BASE & 0xffff0000;
	121	MV_WRITE(MV643XX_ETH_BAR_4, ALong);
	122
	123	MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000);
	124
	125	MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
	126	ALong &= ~(1 << 4);
	127	MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
	128
	129	#ifdef BE_VERBOSE
	130	printk("Pegasos II/Marvell MV64361: register unmapped\n");
	131	printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE);
	132	#endif
	133
	134	iounmap(mv643xx_reg_base);
	135	mv643xx_reg_base = NULL;
	136
	137	return 1;
	138	}
	139
	140
	141	/***********/
	142	/***********/
405861a0	143	static int __init mv643xx_eth_add_pds(void)
bbd0abda PM	144	{
	145	int ret = 0;
	146	static struct pci_device_id pci_marvell_mv64360[] = {
	147	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) },
	148	{ }
	149	};
	150
dd03d25f ND	151	#ifdef BE_VERBOSE
	152	printk("Pegasos II/Marvell MV64361: init\n");
	153	#endif
	154
bbd0abda	155	if (pci_dev_present(pci_marvell_mv64360)) {
dd03d25f ND	156	ret = platform_add_devices(mv643xx_eth_pd_devs,
	157	ARRAY_SIZE(mv643xx_eth_pd_devs));
	158
	159	if ( Enable_SRAM() < 0)
	160	{
10156cea GP	161	eth_port1_pd.tx_sram_addr = 0;
	162	eth_port1_pd.tx_sram_size = 0;
	163	eth_port1_pd.rx_sram_addr = 0;
	164	eth_port1_pd.rx_sram_size = 0;
dd03d25f ND	165
	166	#ifdef BE_VERBOSE
	167	printk("Pegasos II/Marvell MV64361: Can't enable the "
	168	"SRAM\n");
	169	#endif
	170	}
bbd0abda	171	}
dd03d25f ND	172
	173	#ifdef BE_VERBOSE
	174	printk("Pegasos II/Marvell MV64361: init is over\n");
	175	#endif
	176
bbd0abda PM	177	return ret;
bbd0abda PM	178	}
dd03d25f	179
bbd0abda	180	device_initcall(mv643xx_eth_add_pds);