Commit | Line | Data |
---|---|---|
bbd0abda | 1 | /* |
bbd0abda PM |
2 | * Copyright (C) 1995 Linus Torvalds |
3 | * Adapted from 'alpha' version by Gary Thomas | |
4 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
5 | */ | |
6 | ||
7 | /* | |
8 | * bootup setup stuff.. | |
9 | */ | |
10 | ||
bbd0abda PM |
11 | #include <linux/errno.h> |
12 | #include <linux/sched.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/stddef.h> | |
16 | #include <linux/unistd.h> | |
17 | #include <linux/ptrace.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/user.h> | |
20 | #include <linux/a.out.h> | |
21 | #include <linux/tty.h> | |
22 | #include <linux/major.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/reboot.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/pci.h> | |
63104eec | 27 | #include <linux/utsrelease.h> |
bbd0abda PM |
28 | #include <linux/adb.h> |
29 | #include <linux/module.h> | |
30 | #include <linux/delay.h> | |
bbd0abda PM |
31 | #include <linux/console.h> |
32 | #include <linux/seq_file.h> | |
33 | #include <linux/root_dev.h> | |
34 | #include <linux/initrd.h> | |
9618edab | 35 | #include <linux/timer.h> |
bbd0abda PM |
36 | |
37 | #include <asm/io.h> | |
38 | #include <asm/pgtable.h> | |
39 | #include <asm/prom.h> | |
40 | #include <asm/gg2.h> | |
41 | #include <asm/pci-bridge.h> | |
42 | #include <asm/dma.h> | |
43 | #include <asm/machdep.h> | |
44 | #include <asm/irq.h> | |
45 | #include <asm/hydra.h> | |
46 | #include <asm/sections.h> | |
47 | #include <asm/time.h> | |
bbd0abda PM |
48 | #include <asm/i8259.h> |
49 | #include <asm/mpic.h> | |
50 | #include <asm/rtas.h> | |
51 | #include <asm/xmon.h> | |
52 | ||
35e95e63 | 53 | #include "chrp.h" |
bbd0abda | 54 | |
bbd0abda | 55 | void rtas_indicator_progress(char *, unsigned short); |
bbd0abda PM |
56 | |
57 | int _chrp_type; | |
58 | EXPORT_SYMBOL(_chrp_type); | |
59 | ||
0ebfff14 | 60 | static struct mpic *chrp_mpic; |
bbd0abda | 61 | |
9618edab PM |
62 | /* Used for doing CHRP event-scans */ |
63 | DEFINE_PER_CPU(struct timer_list, heartbeat_timer); | |
64 | unsigned long event_scan_interval; | |
65 | ||
bbd0abda PM |
66 | /* |
67 | * XXX this should be in xmon.h, but putting it there means xmon.h | |
68 | * has to include <linux/interrupt.h> (to get irqreturn_t), which | |
69 | * causes all sorts of problems. -- paulus | |
70 | */ | |
35a84c2f | 71 | extern irqreturn_t xmon_irq(int, void *); |
bbd0abda PM |
72 | |
73 | extern unsigned long loops_per_jiffy; | |
74 | ||
26c5032e | 75 | /* To be replaced by RTAS when available */ |
9340b0d3 | 76 | static unsigned int __iomem *briq_SPOR; |
26c5032e | 77 | |
bbd0abda PM |
78 | #ifdef CONFIG_SMP |
79 | extern struct smp_ops_t chrp_smp_ops; | |
80 | #endif | |
81 | ||
82 | static const char *gg2_memtypes[4] = { | |
83 | "FPM", "SDRAM", "EDO", "BEDO" | |
84 | }; | |
85 | static const char *gg2_cachesizes[4] = { | |
86 | "256 KB", "512 KB", "1 MB", "Reserved" | |
87 | }; | |
88 | static const char *gg2_cachetypes[4] = { | |
89 | "Asynchronous", "Reserved", "Flow-Through Synchronous", | |
90 | "Pipelined Synchronous" | |
91 | }; | |
92 | static const char *gg2_cachemodes[4] = { | |
93 | "Disabled", "Write-Through", "Copy-Back", "Transparent Mode" | |
94 | }; | |
95 | ||
26c5032e BH |
96 | static const char *chrp_names[] = { |
97 | "Unknown", | |
98 | "","","", | |
99 | "Motorola", | |
100 | "IBM or Longtrail", | |
101 | "Genesi Pegasos", | |
102 | "Total Impact Briq" | |
103 | }; | |
104 | ||
bbd0abda PM |
105 | void chrp_show_cpuinfo(struct seq_file *m) |
106 | { | |
107 | int i, sdramen; | |
108 | unsigned int t; | |
109 | struct device_node *root; | |
110 | const char *model = ""; | |
111 | ||
8c8dc322 | 112 | root = of_find_node_by_path("/"); |
bbd0abda | 113 | if (root) |
e2eb6392 | 114 | model = of_get_property(root, "model", NULL); |
bbd0abda PM |
115 | seq_printf(m, "machine\t\t: CHRP %s\n", model); |
116 | ||
117 | /* longtrail (goldengate) stuff */ | |
118 | if (!strncmp(model, "IBM,LongTrail", 13)) { | |
119 | /* VLSI VAS96011/12 `Golden Gate 2' */ | |
120 | /* Memory banks */ | |
121 | sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL) | |
122 | >>31) & 1; | |
123 | for (i = 0; i < (sdramen ? 4 : 6); i++) { | |
124 | t = in_le32(gg2_pci_config_base+ | |
125 | GG2_PCI_DRAM_BANK0+ | |
126 | i*4); | |
127 | if (!(t & 1)) | |
128 | continue; | |
129 | switch ((t>>8) & 0x1f) { | |
130 | case 0x1f: | |
131 | model = "4 MB"; | |
132 | break; | |
133 | case 0x1e: | |
134 | model = "8 MB"; | |
135 | break; | |
136 | case 0x1c: | |
137 | model = "16 MB"; | |
138 | break; | |
139 | case 0x18: | |
140 | model = "32 MB"; | |
141 | break; | |
142 | case 0x10: | |
143 | model = "64 MB"; | |
144 | break; | |
145 | case 0x00: | |
146 | model = "128 MB"; | |
147 | break; | |
148 | default: | |
149 | model = "Reserved"; | |
150 | break; | |
151 | } | |
152 | seq_printf(m, "memory bank %d\t: %s %s\n", i, model, | |
153 | gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]); | |
154 | } | |
155 | /* L2 cache */ | |
156 | t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL); | |
157 | seq_printf(m, "board l2\t: %s %s (%s)\n", | |
158 | gg2_cachesizes[(t>>7) & 3], | |
159 | gg2_cachetypes[(t>>2) & 3], | |
160 | gg2_cachemodes[t & 3]); | |
161 | } | |
8c8dc322 | 162 | of_node_put(root); |
bbd0abda PM |
163 | } |
164 | ||
165 | /* | |
166 | * Fixes for the National Semiconductor PC78308VUL SuperI/O | |
167 | * | |
168 | * Some versions of Open Firmware incorrectly initialize the IRQ settings | |
169 | * for keyboard and mouse | |
170 | */ | |
171 | static inline void __init sio_write(u8 val, u8 index) | |
172 | { | |
173 | outb(index, 0x15c); | |
174 | outb(val, 0x15d); | |
175 | } | |
176 | ||
177 | static inline u8 __init sio_read(u8 index) | |
178 | { | |
179 | outb(index, 0x15c); | |
180 | return inb(0x15d); | |
181 | } | |
182 | ||
183 | static void __init sio_fixup_irq(const char *name, u8 device, u8 level, | |
184 | u8 type) | |
185 | { | |
186 | u8 level0, type0, active; | |
187 | ||
188 | /* select logical device */ | |
189 | sio_write(device, 0x07); | |
190 | active = sio_read(0x30); | |
191 | level0 = sio_read(0x70); | |
192 | type0 = sio_read(0x71); | |
193 | if (level0 != level || type0 != type || !active) { | |
194 | printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: " | |
195 | "remapping to level %d, type %d, active\n", | |
196 | name, level0, type0, !active ? "in" : "", level, type); | |
197 | sio_write(0x01, 0x30); | |
198 | sio_write(level, 0x70); | |
199 | sio_write(type, 0x71); | |
200 | } | |
201 | } | |
202 | ||
203 | static void __init sio_init(void) | |
204 | { | |
205 | struct device_node *root; | |
206 | ||
8c8dc322 | 207 | if ((root = of_find_node_by_path("/")) && |
e2eb6392 SR |
208 | !strncmp(of_get_property(root, "model", NULL), |
209 | "IBM,LongTrail", 13)) { | |
bbd0abda PM |
210 | /* logical device 0 (KBC/Keyboard) */ |
211 | sio_fixup_irq("keyboard", 0, 1, 2); | |
212 | /* select logical device 1 (KBC/Mouse) */ | |
213 | sio_fixup_irq("mouse", 1, 12, 2); | |
214 | } | |
8c8dc322 | 215 | of_node_put(root); |
bbd0abda PM |
216 | } |
217 | ||
218 | ||
219 | static void __init pegasos_set_l2cr(void) | |
220 | { | |
221 | struct device_node *np; | |
222 | ||
223 | /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */ | |
224 | if (_chrp_type != _CHRP_Pegasos) | |
225 | return; | |
226 | ||
227 | /* Enable L2 cache if needed */ | |
1658ab66 | 228 | np = of_find_node_by_type(NULL, "cpu"); |
bbd0abda | 229 | if (np != NULL) { |
e2eb6392 | 230 | const unsigned int *l2cr = of_get_property(np, "l2cr", NULL); |
bbd0abda PM |
231 | if (l2cr == NULL) { |
232 | printk ("Pegasos l2cr : no cpu l2cr property found\n"); | |
1658ab66 | 233 | goto out; |
bbd0abda PM |
234 | } |
235 | if (!((*l2cr) & 0x80000000)) { | |
236 | printk ("Pegasos l2cr : L2 cache was not active, " | |
237 | "activating\n"); | |
238 | _set_L2CR(0); | |
239 | _set_L2CR((*l2cr) | 0x80000000); | |
240 | } | |
241 | } | |
1658ab66 SR |
242 | out: |
243 | of_node_put(np); | |
bbd0abda PM |
244 | } |
245 | ||
26c5032e BH |
246 | static void briq_restart(char *cmd) |
247 | { | |
248 | local_irq_disable(); | |
249 | if (briq_SPOR) | |
250 | out_be32(briq_SPOR, 0); | |
251 | for(;;); | |
252 | } | |
253 | ||
bbd0abda PM |
254 | void __init chrp_setup_arch(void) |
255 | { | |
8c8dc322 | 256 | struct device_node *root = of_find_node_by_path("/"); |
ae6b4101 | 257 | const char *machine = NULL; |
bbd0abda PM |
258 | |
259 | /* init to some ~sane value until calibrate_delay() runs */ | |
260 | loops_per_jiffy = 50000000/HZ; | |
261 | ||
262 | if (root) | |
e2eb6392 | 263 | machine = of_get_property(root, "model", NULL); |
bbd0abda PM |
264 | if (machine && strncmp(machine, "Pegasos", 7) == 0) { |
265 | _chrp_type = _CHRP_Pegasos; | |
266 | } else if (machine && strncmp(machine, "IBM", 3) == 0) { | |
267 | _chrp_type = _CHRP_IBM; | |
268 | } else if (machine && strncmp(machine, "MOT", 3) == 0) { | |
269 | _chrp_type = _CHRP_Motorola; | |
26c5032e BH |
270 | } else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) { |
271 | _chrp_type = _CHRP_briq; | |
272 | /* Map the SPOR register on briq and change the restart hook */ | |
9340b0d3 | 273 | briq_SPOR = ioremap(0xff0000e8, 4); |
26c5032e | 274 | ppc_md.restart = briq_restart; |
bbd0abda PM |
275 | } else { |
276 | /* Let's assume it is an IBM chrp if all else fails */ | |
277 | _chrp_type = _CHRP_IBM; | |
278 | } | |
8c8dc322 | 279 | of_node_put(root); |
26c5032e | 280 | printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]); |
bbd0abda PM |
281 | |
282 | rtas_initialize(); | |
283 | if (rtas_token("display-character") >= 0) | |
284 | ppc_md.progress = rtas_progress; | |
285 | ||
49e16b7b PM |
286 | /* use RTAS time-of-day routines if available */ |
287 | if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) { | |
288 | ppc_md.get_boot_time = rtas_get_boot_time; | |
289 | ppc_md.get_rtc_time = rtas_get_rtc_time; | |
290 | ppc_md.set_rtc_time = rtas_set_rtc_time; | |
291 | } | |
292 | ||
bbd0abda PM |
293 | #ifdef CONFIG_BLK_DEV_INITRD |
294 | /* this is fine for chrp */ | |
295 | initrd_below_start_ok = 1; | |
296 | ||
297 | if (initrd_start) | |
298 | ROOT_DEV = Root_RAM0; | |
299 | else | |
300 | #endif | |
301 | ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */ | |
302 | ||
303 | /* On pegasos, enable the L2 cache if not already done by OF */ | |
304 | pegasos_set_l2cr(); | |
305 | ||
306 | /* Lookup PCI host bridges */ | |
307 | chrp_find_bridges(); | |
308 | ||
309 | /* | |
310 | * Temporary fixes for PCI devices. | |
311 | * -- Geert | |
312 | */ | |
313 | hydra_init(); /* Mac I/O */ | |
314 | ||
315 | /* | |
316 | * Fix the Super I/O configuration | |
317 | */ | |
318 | sio_init(); | |
319 | ||
bbd0abda PM |
320 | pci_create_OF_bus_map(); |
321 | ||
322 | /* | |
323 | * Print the banner, then scroll down so boot progress | |
324 | * can be printed. -- Cort | |
325 | */ | |
326 | if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0); | |
327 | } | |
328 | ||
329 | void | |
9618edab | 330 | chrp_event_scan(unsigned long unused) |
bbd0abda PM |
331 | { |
332 | unsigned char log[1024]; | |
333 | int ret = 0; | |
334 | ||
335 | /* XXX: we should loop until the hardware says no more error logs -- Cort */ | |
336 | rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0, | |
337 | __pa(log), 1024); | |
9618edab PM |
338 | mod_timer(&__get_cpu_var(heartbeat_timer), |
339 | jiffies + event_scan_interval); | |
bbd0abda PM |
340 | } |
341 | ||
35a84c2f | 342 | static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc) |
b9e5b4e6 | 343 | { |
35a84c2f | 344 | unsigned int cascade_irq = i8259_irq(); |
0ebfff14 | 345 | if (cascade_irq != NO_IRQ) |
49f19ce4 | 346 | generic_handle_irq(cascade_irq); |
0ebfff14 | 347 | desc->chip->eoi(irq); |
b9e5b4e6 BH |
348 | } |
349 | ||
bbd0abda PM |
350 | /* |
351 | * Finds the open-pic node and sets up the mpic driver. | |
352 | */ | |
353 | static void __init chrp_find_openpic(void) | |
354 | { | |
355 | struct device_node *np, *root; | |
0ebfff14 | 356 | int len, i, j; |
bbd0abda | 357 | int isu_size, idu_size; |
ae6b4101 | 358 | const unsigned int *iranges, *opprop = NULL; |
bbd0abda PM |
359 | int oplen = 0; |
360 | unsigned long opaddr; | |
361 | int na = 1; | |
bbd0abda | 362 | |
0ebfff14 | 363 | np = of_find_node_by_type(NULL, "open-pic"); |
bbd0abda PM |
364 | if (np == NULL) |
365 | return; | |
0ebfff14 | 366 | root = of_find_node_by_path("/"); |
bbd0abda | 367 | if (root) { |
e2eb6392 | 368 | opprop = of_get_property(root, "platform-open-pic", &oplen); |
a8bda5dd | 369 | na = of_n_addr_cells(root); |
bbd0abda PM |
370 | } |
371 | if (opprop && oplen >= na * sizeof(unsigned int)) { | |
372 | opaddr = opprop[na-1]; /* assume 32-bit */ | |
373 | oplen /= na * sizeof(unsigned int); | |
374 | } else { | |
575e3216 | 375 | struct resource r; |
0ebfff14 BH |
376 | if (of_address_to_resource(np, 0, &r)) { |
377 | goto bail; | |
378 | } | |
575e3216 | 379 | opaddr = r.start; |
bbd0abda PM |
380 | oplen = 0; |
381 | } | |
382 | ||
383 | printk(KERN_INFO "OpenPIC at %lx\n", opaddr); | |
384 | ||
e2eb6392 | 385 | iranges = of_get_property(np, "interrupt-ranges", &len); |
bbd0abda PM |
386 | if (iranges == NULL) |
387 | len = 0; /* non-distributed mpic */ | |
388 | else | |
389 | len /= 2 * sizeof(unsigned int); | |
390 | ||
391 | /* | |
392 | * The first pair of cells in interrupt-ranges refers to the | |
393 | * IDU; subsequent pairs refer to the ISUs. | |
394 | */ | |
395 | if (oplen < len) { | |
396 | printk(KERN_ERR "Insufficient addresses for distributed" | |
575e3216 | 397 | " OpenPIC (%d < %d)\n", oplen, len); |
bbd0abda PM |
398 | len = oplen; |
399 | } | |
400 | ||
401 | isu_size = 0; | |
402 | idu_size = 0; | |
403 | if (len > 0 && iranges[1] != 0) { | |
404 | printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n", | |
405 | iranges[0], iranges[0] + iranges[1] - 1); | |
406 | idu_size = iranges[1]; | |
407 | } | |
408 | if (len > 1) | |
409 | isu_size = iranges[3]; | |
410 | ||
0ebfff14 BH |
411 | chrp_mpic = mpic_alloc(np, opaddr, MPIC_PRIMARY, |
412 | isu_size, 0, " MPIC "); | |
bbd0abda PM |
413 | if (chrp_mpic == NULL) { |
414 | printk(KERN_ERR "Failed to allocate MPIC structure\n"); | |
0ebfff14 | 415 | goto bail; |
bbd0abda | 416 | } |
bbd0abda PM |
417 | j = na - 1; |
418 | for (i = 1; i < len; ++i) { | |
419 | iranges += 2; | |
420 | j += na; | |
421 | printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n", | |
422 | iranges[0], iranges[0] + iranges[1] - 1, | |
423 | opprop[j]); | |
424 | mpic_assign_isu(chrp_mpic, i - 1, opprop[j]); | |
425 | } | |
426 | ||
427 | mpic_init(chrp_mpic); | |
0ebfff14 BH |
428 | ppc_md.get_irq = mpic_get_irq; |
429 | bail: | |
430 | of_node_put(root); | |
431 | of_node_put(np); | |
bbd0abda PM |
432 | } |
433 | ||
e85f008d | 434 | #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) |
bbd0abda PM |
435 | static struct irqaction xmon_irqaction = { |
436 | .handler = xmon_irq, | |
437 | .mask = CPU_MASK_NONE, | |
438 | .name = "XMON break", | |
439 | }; | |
440 | #endif | |
441 | ||
0ebfff14 | 442 | static void __init chrp_find_8259(void) |
bbd0abda | 443 | { |
0ebfff14 | 444 | struct device_node *np, *pic = NULL; |
bbd0abda | 445 | unsigned long chrp_int_ack = 0; |
0ebfff14 | 446 | unsigned int cascade_irq; |
bbd0abda | 447 | |
0ebfff14 BH |
448 | /* Look for cascade */ |
449 | for_each_node_by_type(np, "interrupt-controller") | |
55b61fec | 450 | if (of_device_is_compatible(np, "chrp,iic")) { |
0ebfff14 BH |
451 | pic = np; |
452 | break; | |
453 | } | |
454 | /* Ok, 8259 wasn't found. We need to handle the case where | |
455 | * we have a pegasos that claims to be chrp but doesn't have | |
456 | * a proper interrupt tree | |
457 | */ | |
458 | if (pic == NULL && chrp_mpic != NULL) { | |
459 | printk(KERN_ERR "i8259: Not found in device-tree" | |
460 | " assuming no legacy interrupts\n"); | |
461 | return; | |
462 | } | |
463 | ||
464 | /* Look for intack. In a perfect world, we would look for it on | |
465 | * the ISA bus that holds the 8259 but heh... Works that way. If | |
466 | * we ever see a problem, we can try to re-use the pSeries code here. | |
467 | * Also, Pegasos-type platforms don't have a proper node to start | |
468 | * from anyway | |
469 | */ | |
30686ba6 | 470 | for_each_node_by_name(np, "pci") { |
e2eb6392 | 471 | const unsigned int *addrp = of_get_property(np, |
ae6b4101 | 472 | "8259-interrupt-acknowledge", NULL); |
bbd0abda PM |
473 | |
474 | if (addrp == NULL) | |
475 | continue; | |
a8bda5dd | 476 | chrp_int_ack = addrp[of_n_addr_cells(np)-1]; |
bbd0abda PM |
477 | break; |
478 | } | |
30686ba6 | 479 | of_node_put(np); |
bbd0abda | 480 | if (np == NULL) |
0ebfff14 BH |
481 | printk(KERN_WARNING "Cannot find PCI interrupt acknowledge" |
482 | " address, polling\n"); | |
483 | ||
484 | i8259_init(pic, chrp_int_ack); | |
f4d4c354 | 485 | if (ppc_md.get_irq == NULL) { |
0ebfff14 | 486 | ppc_md.get_irq = i8259_irq; |
f4d4c354 BH |
487 | irq_set_default_host(i8259_get_host()); |
488 | } | |
0ebfff14 BH |
489 | if (chrp_mpic != NULL) { |
490 | cascade_irq = irq_of_parse_and_map(pic, 0); | |
491 | if (cascade_irq == NO_IRQ) | |
492 | printk(KERN_ERR "i8259: failed to map cascade irq\n"); | |
493 | else | |
494 | set_irq_chained_handler(cascade_irq, | |
495 | chrp_8259_cascade); | |
496 | } | |
497 | } | |
bbd0abda | 498 | |
0ebfff14 BH |
499 | void __init chrp_init_IRQ(void) |
500 | { | |
e85f008d | 501 | #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) |
0ebfff14 BH |
502 | struct device_node *kbd; |
503 | #endif | |
bbd0abda | 504 | chrp_find_openpic(); |
0ebfff14 | 505 | chrp_find_8259(); |
bbd0abda | 506 | |
1e031d65 BH |
507 | #ifdef CONFIG_SMP |
508 | /* Pegasos has no MPIC, those ops would make it crash. It might be an | |
509 | * option to move setting them to after we probe the PIC though | |
510 | */ | |
511 | if (chrp_mpic != NULL) | |
512 | smp_ops = &chrp_smp_ops; | |
513 | #endif /* CONFIG_SMP */ | |
514 | ||
bbd0abda PM |
515 | if (_chrp_type == _CHRP_Pegasos) |
516 | ppc_md.get_irq = i8259_irq; | |
bbd0abda | 517 | |
e85f008d | 518 | #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) |
bbd0abda PM |
519 | /* see if there is a keyboard in the device tree |
520 | with a parent of type "adb" */ | |
30686ba6 | 521 | for_each_node_by_name(kbd, "keyboard") |
bbd0abda PM |
522 | if (kbd->parent && kbd->parent->type |
523 | && strcmp(kbd->parent->type, "adb") == 0) | |
524 | break; | |
30686ba6 | 525 | of_node_put(kbd); |
bbd0abda PM |
526 | if (kbd) |
527 | setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction); | |
528 | #endif | |
529 | } | |
530 | ||
531 | void __init | |
532 | chrp_init2(void) | |
533 | { | |
9618edab | 534 | struct device_node *device; |
ae6b4101 | 535 | const unsigned int *p = NULL; |
9618edab | 536 | |
35e95e63 OH |
537 | #ifdef CONFIG_NVRAM |
538 | chrp_nvram_init(); | |
539 | #endif | |
540 | ||
bbd0abda PM |
541 | request_region(0x20,0x20,"pic1"); |
542 | request_region(0xa0,0x20,"pic2"); | |
543 | request_region(0x00,0x20,"dma1"); | |
544 | request_region(0x40,0x20,"timer"); | |
545 | request_region(0x80,0x10,"dma page reg"); | |
546 | request_region(0xc0,0x20,"dma2"); | |
547 | ||
9618edab PM |
548 | /* Get the event scan rate for the rtas so we know how |
549 | * often it expects a heartbeat. -- Cort | |
550 | */ | |
30686ba6 | 551 | device = of_find_node_by_name(NULL, "rtas"); |
9618edab | 552 | if (device) |
e2eb6392 | 553 | p = of_get_property(device, "rtas-event-scan-rate", NULL); |
9618edab PM |
554 | if (p && *p) { |
555 | /* | |
556 | * Arrange to call chrp_event_scan at least *p times | |
557 | * per minute. We use 59 rather than 60 here so that | |
558 | * the rate will be slightly higher than the minimum. | |
559 | * This all assumes we don't do hotplug CPU on any | |
560 | * machine that needs the event scans done. | |
561 | */ | |
562 | unsigned long interval, offset; | |
563 | int cpu, ncpus; | |
564 | struct timer_list *timer; | |
565 | ||
566 | interval = HZ * 59 / *p; | |
567 | offset = HZ; | |
568 | ncpus = num_online_cpus(); | |
569 | event_scan_interval = ncpus * interval; | |
570 | for (cpu = 0; cpu < ncpus; ++cpu) { | |
571 | timer = &per_cpu(heartbeat_timer, cpu); | |
572 | setup_timer(timer, chrp_event_scan, 0); | |
573 | timer->expires = jiffies + offset; | |
574 | add_timer_on(timer, cpu); | |
575 | offset += interval; | |
576 | } | |
577 | printk("RTAS Event Scan Rate: %u (%lu jiffies)\n", | |
578 | *p, interval); | |
579 | } | |
30686ba6 | 580 | of_node_put(device); |
9618edab | 581 | |
bbd0abda PM |
582 | if (ppc_md.progress) |
583 | ppc_md.progress(" Have fun! ", 0x7777); | |
584 | } | |
585 | ||
e8222502 | 586 | static int __init chrp_probe(void) |
bbd0abda | 587 | { |
e8222502 BH |
588 | char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(), |
589 | "device_type", NULL); | |
590 | if (dtype == NULL) | |
591 | return 0; | |
592 | if (strcmp(dtype, "chrp")) | |
593 | return 0; | |
594 | ||
bbd0abda PM |
595 | ISA_DMA_THRESHOLD = ~0L; |
596 | DMA_MODE_READ = 0x44; | |
597 | DMA_MODE_WRITE = 0x48; | |
bbd0abda | 598 | |
b86756ae | 599 | return 1; |
bbd0abda | 600 | } |
b86756ae PM |
601 | |
602 | define_machine(chrp) { | |
603 | .name = "CHRP", | |
604 | .probe = chrp_probe, | |
605 | .setup_arch = chrp_setup_arch, | |
606 | .init = chrp_init2, | |
607 | .show_cpuinfo = chrp_show_cpuinfo, | |
608 | .init_IRQ = chrp_init_IRQ, | |
b86756ae PM |
609 | .restart = rtas_restart, |
610 | .power_off = rtas_power_off, | |
611 | .halt = rtas_halt, | |
612 | .time_init = chrp_time_init, | |
613 | .set_rtc_time = chrp_set_rtc_time, | |
614 | .get_rtc_time = chrp_get_rtc_time, | |
615 | .calibrate_decr = generic_calibrate_decr, | |
616 | .phys_mem_access_prot = pci_phys_mem_access_prot, | |
617 | }; |