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b66510cb KG |
1 | /* |
2 | * ULI M1575 setup code - specific to Freescale boards | |
3 | * | |
4 | * Copyright 2007 Freescale Semiconductor Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/stddef.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/mc146818rtc.h> | |
17 | ||
18 | #include <asm/system.h> | |
19 | #include <asm/pci-bridge.h> | |
20 | ||
21 | #define ULI_PIRQA 0x08 | |
22 | #define ULI_PIRQB 0x09 | |
23 | #define ULI_PIRQC 0x0a | |
24 | #define ULI_PIRQD 0x0b | |
25 | #define ULI_PIRQE 0x0c | |
26 | #define ULI_PIRQF 0x0d | |
27 | #define ULI_PIRQG 0x0e | |
28 | ||
29 | #define ULI_8259_NONE 0x00 | |
30 | #define ULI_8259_IRQ1 0x08 | |
31 | #define ULI_8259_IRQ3 0x02 | |
32 | #define ULI_8259_IRQ4 0x04 | |
33 | #define ULI_8259_IRQ5 0x05 | |
34 | #define ULI_8259_IRQ6 0x07 | |
35 | #define ULI_8259_IRQ7 0x06 | |
36 | #define ULI_8259_IRQ9 0x01 | |
37 | #define ULI_8259_IRQ10 0x03 | |
38 | #define ULI_8259_IRQ11 0x09 | |
39 | #define ULI_8259_IRQ12 0x0b | |
40 | #define ULI_8259_IRQ14 0x0d | |
41 | #define ULI_8259_IRQ15 0x0f | |
42 | ||
43 | u8 uli_pirq_to_irq[8] = { | |
44 | ULI_8259_IRQ9, /* PIRQA */ | |
45 | ULI_8259_IRQ10, /* PIRQB */ | |
46 | ULI_8259_IRQ11, /* PIRQC */ | |
47 | ULI_8259_IRQ12, /* PIRQD */ | |
48 | ULI_8259_IRQ5, /* PIRQE */ | |
49 | ULI_8259_IRQ6, /* PIRQF */ | |
50 | ULI_8259_IRQ7, /* PIRQG */ | |
51 | ULI_8259_NONE, /* PIRQH */ | |
52 | }; | |
53 | ||
b66510cb KG |
54 | /* Bridge */ |
55 | static void __devinit early_uli5249(struct pci_dev *dev) | |
56 | { | |
57 | unsigned char temp; | |
58 | ||
52ddd1cd AV |
59 | if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && |
60 | !machine_is(mpc8572_ds)) | |
b66510cb KG |
61 | return; |
62 | ||
63 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO | | |
64 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
65 | ||
66 | /* read/write lock */ | |
67 | pci_read_config_byte(dev, 0x7c, &temp); | |
68 | pci_write_config_byte(dev, 0x7c, 0x80); | |
69 | ||
70 | /* set as P2P bridge */ | |
71 | pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01); | |
72 | dev->class |= 0x1; | |
73 | ||
74 | /* restore lock */ | |
75 | pci_write_config_byte(dev, 0x7c, temp); | |
76 | } | |
77 | ||
78 | ||
79 | static void __devinit quirk_uli1575(struct pci_dev *dev) | |
80 | { | |
81 | int i; | |
82 | ||
52ddd1cd AV |
83 | if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && |
84 | !machine_is(mpc8572_ds)) | |
b66510cb KG |
85 | return; |
86 | ||
87 | /* | |
88 | * ULI1575 interrupts route setup | |
89 | */ | |
90 | ||
91 | /* ULI1575 IRQ mapping conf register maps PIRQx to IRQn */ | |
92 | for (i = 0; i < 4; i++) { | |
93 | u8 val = uli_pirq_to_irq[i*2] | (uli_pirq_to_irq[i*2+1] << 4); | |
94 | pci_write_config_byte(dev, 0x48 + i, val); | |
95 | } | |
96 | ||
97 | /* USB 1.1 OHCI controller 1: dev 28, func 0 - IRQ12 */ | |
98 | pci_write_config_byte(dev, 0x86, ULI_PIRQD); | |
99 | ||
100 | /* USB 1.1 OHCI controller 2: dev 28, func 1 - IRQ9 */ | |
101 | pci_write_config_byte(dev, 0x87, ULI_PIRQA); | |
102 | ||
103 | /* USB 1.1 OHCI controller 3: dev 28, func 2 - IRQ10 */ | |
104 | pci_write_config_byte(dev, 0x88, ULI_PIRQB); | |
105 | ||
106 | /* Lan controller: dev 27, func 0 - IRQ6 */ | |
107 | pci_write_config_byte(dev, 0x89, ULI_PIRQF); | |
108 | ||
109 | /* AC97 Audio controller: dev 29, func 0 - IRQ6 */ | |
110 | pci_write_config_byte(dev, 0x8a, ULI_PIRQF); | |
111 | ||
112 | /* Modem controller: dev 29, func 1 - IRQ6 */ | |
113 | pci_write_config_byte(dev, 0x8b, ULI_PIRQF); | |
114 | ||
115 | /* HD Audio controller: dev 29, func 2 - IRQ6 */ | |
116 | pci_write_config_byte(dev, 0x8c, ULI_PIRQF); | |
117 | ||
118 | /* SATA controller: dev 31, func 1 - IRQ5 */ | |
119 | pci_write_config_byte(dev, 0x8d, ULI_PIRQE); | |
120 | ||
121 | /* SMB interrupt: dev 30, func 1 - IRQ7 */ | |
122 | pci_write_config_byte(dev, 0x8e, ULI_PIRQG); | |
123 | ||
124 | /* PMU ACPI SCI interrupt: dev 30, func 2 - IRQ7 */ | |
125 | pci_write_config_byte(dev, 0x8f, ULI_PIRQG); | |
126 | ||
127 | /* USB 2.0 controller: dev 28, func 3 */ | |
128 | pci_write_config_byte(dev, 0x74, ULI_8259_IRQ11); | |
129 | ||
130 | /* Primary PATA IDE IRQ: 14 | |
131 | * Secondary PATA IDE IRQ: 15 | |
132 | */ | |
133 | pci_write_config_byte(dev, 0x44, 0x30 | ULI_8259_IRQ14); | |
134 | pci_write_config_byte(dev, 0x75, ULI_8259_IRQ15); | |
135 | } | |
136 | ||
137 | static void __devinit quirk_final_uli1575(struct pci_dev *dev) | |
138 | { | |
139 | /* Set i8259 interrupt trigger | |
140 | * IRQ 3: Level | |
141 | * IRQ 4: Level | |
142 | * IRQ 5: Level | |
143 | * IRQ 6: Level | |
144 | * IRQ 7: Level | |
145 | * IRQ 9: Level | |
146 | * IRQ 10: Level | |
147 | * IRQ 11: Level | |
148 | * IRQ 12: Level | |
149 | * IRQ 14: Edge | |
150 | * IRQ 15: Edge | |
151 | */ | |
52ddd1cd AV |
152 | if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && |
153 | !machine_is(mpc8572_ds)) | |
b66510cb KG |
154 | return; |
155 | ||
156 | outb(0xfa, 0x4d0); | |
157 | outb(0x1e, 0x4d1); | |
158 | ||
159 | /* setup RTC */ | |
160 | CMOS_WRITE(RTC_SET, RTC_CONTROL); | |
161 | CMOS_WRITE(RTC_24H, RTC_CONTROL); | |
162 | ||
163 | /* ensure month, date, and week alarm fields are ignored */ | |
164 | CMOS_WRITE(0, RTC_VALID); | |
165 | ||
166 | outb_p(0x7c, 0x72); | |
167 | outb_p(RTC_ALARM_DONT_CARE, 0x73); | |
168 | ||
169 | outb_p(0x7d, 0x72); | |
170 | outb_p(RTC_ALARM_DONT_CARE, 0x73); | |
171 | } | |
172 | ||
173 | /* SATA */ | |
174 | static void __devinit quirk_uli5288(struct pci_dev *dev) | |
175 | { | |
176 | unsigned char c; | |
177 | unsigned int d; | |
178 | ||
52ddd1cd AV |
179 | if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && |
180 | !machine_is(mpc8572_ds)) | |
b66510cb KG |
181 | return; |
182 | ||
183 | /* read/write lock */ | |
184 | pci_read_config_byte(dev, 0x83, &c); | |
185 | pci_write_config_byte(dev, 0x83, c|0x80); | |
186 | ||
187 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &d); | |
188 | d = (d & 0xff) | (PCI_CLASS_STORAGE_SATA_AHCI << 8); | |
189 | pci_write_config_dword(dev, PCI_CLASS_REVISION, d); | |
190 | ||
191 | /* restore lock */ | |
192 | pci_write_config_byte(dev, 0x83, c); | |
193 | ||
194 | /* disable emulated PATA mode enabled */ | |
195 | pci_read_config_byte(dev, 0x84, &c); | |
196 | pci_write_config_byte(dev, 0x84, c & ~0x01); | |
197 | } | |
198 | ||
199 | /* PATA */ | |
200 | static void __devinit quirk_uli5229(struct pci_dev *dev) | |
201 | { | |
202 | unsigned short temp; | |
203 | ||
52ddd1cd AV |
204 | if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && |
205 | !machine_is(mpc8572_ds)) | |
b66510cb KG |
206 | return; |
207 | ||
208 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE | | |
209 | PCI_COMMAND_MASTER | PCI_COMMAND_IO); | |
210 | ||
211 | /* Enable Native IRQ 14/15 */ | |
212 | pci_read_config_word(dev, 0x4a, &temp); | |
213 | pci_write_config_word(dev, 0x4a, temp | 0x1000); | |
214 | } | |
215 | ||
216 | /* We have to do a dummy read on the P2P for the RTC to work, WTF */ | |
217 | static void __devinit quirk_final_uli5249(struct pci_dev *dev) | |
218 | { | |
219 | int i; | |
220 | u8 *dummy; | |
221 | struct pci_bus *bus = dev->bus; | |
222 | ||
223 | for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
224 | if ((bus->resource[i]) && | |
225 | (bus->resource[i]->flags & IORESOURCE_MEM)) { | |
00c5372d | 226 | dummy = ioremap(bus->resource[i]->end - 3, 0x4); |
b66510cb KG |
227 | if (dummy) { |
228 | in_8(dummy); | |
229 | iounmap(dummy); | |
230 | } | |
231 | break; | |
232 | } | |
233 | } | |
234 | } | |
235 | ||
236 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249); | |
237 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575); | |
238 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288); | |
239 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229); | |
240 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249); | |
241 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575); | |
242 | ||
52ddd1cd AV |
243 | static void __devinit hpcd_quirk_uli1575(struct pci_dev *dev) |
244 | { | |
245 | u32 temp32; | |
246 | ||
247 | if (!machine_is(mpc86xx_hpcd)) | |
248 | return; | |
249 | ||
250 | /* Disable INTx */ | |
251 | pci_read_config_dword(dev, 0x48, &temp32); | |
252 | pci_write_config_dword(dev, 0x48, (temp32 | 1<<26)); | |
253 | ||
254 | /* Enable sideband interrupt */ | |
255 | pci_read_config_dword(dev, 0x90, &temp32); | |
256 | pci_write_config_dword(dev, 0x90, (temp32 | 1<<22)); | |
257 | } | |
258 | ||
259 | static void __devinit hpcd_quirk_uli5288(struct pci_dev *dev) | |
260 | { | |
261 | unsigned char c; | |
262 | unsigned short temp; | |
263 | ||
264 | if (!machine_is(mpc86xx_hpcd)) | |
265 | return; | |
266 | ||
267 | /* Interrupt Disable, Needed when SATA disabled */ | |
268 | pci_read_config_word(dev, PCI_COMMAND, &temp); | |
269 | temp |= 1<<10; | |
270 | pci_write_config_word(dev, PCI_COMMAND, temp); | |
271 | ||
272 | pci_read_config_byte(dev, 0x83, &c); | |
273 | c |= 0x80; | |
274 | pci_write_config_byte(dev, 0x83, c); | |
275 | ||
276 | pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01); | |
277 | pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06); | |
278 | ||
279 | pci_read_config_byte(dev, 0x83, &c); | |
280 | c &= 0x7f; | |
281 | pci_write_config_byte(dev, 0x83, c); | |
282 | } | |
283 | ||
284 | /* | |
285 | * Since 8259PIC was disabled on the board, the IDE device can not | |
286 | * use the legacy IRQ, we need to let the IDE device work under | |
287 | * native mode and use the interrupt line like other PCI devices. | |
288 | * IRQ14 is a sideband interrupt from IDE device to CPU and we use this | |
289 | * as the interrupt for IDE device. | |
290 | */ | |
291 | static void __devinit hpcd_quirk_uli5229(struct pci_dev *dev) | |
292 | { | |
293 | unsigned char c; | |
294 | ||
295 | if (!machine_is(mpc86xx_hpcd)) | |
296 | return; | |
297 | ||
298 | pci_read_config_byte(dev, 0x4b, &c); | |
299 | c |= 0x10; | |
300 | pci_write_config_byte(dev, 0x4b, c); | |
301 | } | |
302 | ||
303 | /* | |
304 | * SATA interrupt pin bug fix | |
305 | * There's a chip bug for 5288, The interrupt pin should be 2, | |
306 | * not the read only value 1, So it use INTB#, not INTA# which | |
307 | * actually used by the IDE device 5229. | |
308 | * As of this bug, during the PCI initialization, 5288 read the | |
309 | * irq of IDE device from the device tree, this function fix this | |
310 | * bug by re-assigning a correct irq to 5288. | |
311 | * | |
312 | */ | |
313 | static void __devinit hpcd_final_uli5288(struct pci_dev *dev) | |
314 | { | |
315 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
316 | struct device_node *hosenode = hose ? hose->dn : NULL; | |
317 | struct of_irq oirq; | |
318 | int virq, pin = 2; | |
319 | u32 laddr[3]; | |
320 | ||
321 | if (!machine_is(mpc86xx_hpcd)) | |
322 | return; | |
323 | ||
324 | if (!hosenode) | |
325 | return; | |
326 | ||
327 | laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8); | |
328 | laddr[1] = laddr[2] = 0; | |
329 | of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq); | |
330 | virq = irq_create_of_mapping(oirq.controller, oirq.specifier, | |
331 | oirq.size); | |
332 | dev->irq = virq; | |
333 | } | |
334 | ||
335 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, hpcd_quirk_uli1575); | |
336 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, hpcd_quirk_uli5288); | |
337 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, hpcd_quirk_uli5229); | |
338 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, hpcd_final_uli5288); | |
339 | ||
b66510cb KG |
340 | int uli_exclude_device(struct pci_controller *hose, |
341 | u_char bus, u_char devfn) | |
342 | { | |
343 | if (bus == (hose->first_busno + 2)) { | |
344 | /* exclude Modem controller */ | |
345 | if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 1)) | |
346 | return PCIBIOS_DEVICE_NOT_FOUND; | |
347 | ||
348 | /* exclude HD Audio controller */ | |
349 | if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 2)) | |
350 | return PCIBIOS_DEVICE_NOT_FOUND; | |
351 | } | |
352 | ||
353 | return PCIBIOS_SUCCESSFUL; | |
354 | } |