projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| 1da177e4 | 2 | * Copyright (C) 2001 Mike Corrigan IBM Corporation |
| fcee3895 | 3 | * |
| 1da177e4 LT |
4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by | |
| 6 | * the Free Software Foundation; either version 2 of the License, or | |
| 7 | * (at your option) any later version. | |
| fcee3895 | 8 | * |
| 1da177e4 LT |
9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | * GNU General Public License for more details. | |
| fcee3895 | 13 | * |
| 1da177e4 LT |
14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software | |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 17 | */ | |
| 06a36db1 ME |
18 | #ifndef _PLATFORMS_ISERIES_IT_LP_NACA_H |
| 19 | #define _PLATFORMS_ISERIES_IT_LP_NACA_H | |
| 1da177e4 | 20 | |
| 0bc0ffd5 SR |
21 | #include <linux/types.h> |
| 22 | ||
| fcee3895 SR |
23 | /* |
| 24 | * This control block contains the data that is shared between the | |
| 25 | * hypervisor (PLIC) and the OS. | |
| 26 | */ | |
| 1da177e4 | 27 | |
| fcee3895 | 28 | struct ItLpNaca { |
| 1da177e4 | 29 | // CACHE_LINE_1 0x0000 - 0x007F Contains read-only data |
| 1da177e4 LT |
30 | u32 xDesc; // Eye catcher x00-x03 |
| 31 | u16 xSize; // Size of this class x04-x05 | |
| 32 | u16 xIntHdlrOffset; // Offset to IntHdlr array x06-x07 | |
| 33 | u8 xMaxIntHdlrEntries; // Number of entries in array x08-x08 | |
| 34 | u8 xPrimaryLpIndex; // LP Index of Primary x09-x09 | |
| 35 | u8 xServiceLpIndex; // LP Ind of Service Focal Pointx0A-x0A | |
| 36 | u8 xLpIndex; // LP Index x0B-x0B | |
| 37 | u16 xMaxLpQueues; // Number of allocated queues x0C-x0D | |
| 38 | u16 xLpQueueOffset; // Offset to start of LP queues x0E-x0F | |
| f9cb83ac SR |
39 | u8 xPirEnvironMode; // Piranha or hardware x10-x10 |
| 40 | u8 xPirConsoleMode; // Piranha console indicator x11-x11 | |
| 41 | u8 xPirDasdMode; // Piranha dasd indicator x12-x12 | |
| 1da177e4 | 42 | u8 xRsvd1_0[5]; // Reserved for Piranha related x13-x17 |
| f9cb83ac SR |
43 | u8 flags; // flags, see below x18-x1F |
| 44 | u8 xSpVpdFormat; // VPD areas are in CSP format ... | |
| 45 | u8 xIntProcRatio; // Ratio of int procs to procs ... | |
| 1da177e4 LT |
46 | u8 xRsvd1_2[5]; // Reserved ... |
| 47 | u16 xRsvd1_3; // Reserved x20-x21 | |
| 48 | u16 xPlicVrmIndex; // VRM index of PLIC x22-x23 | |
| 49 | u16 xMinSupportedSlicVrmInd;// Min supported OS VRM index x24-x25 | |
| 50 | u16 xMinCompatableSlicVrmInd;// Min compatible OS VRM index x26-x27 | |
| 51 | u64 xLoadAreaAddr; // ER address of load area x28-x2F | |
| 52 | u32 xLoadAreaChunks; // Chunks for the load area x30-x33 | |
| 53 | u32 xPaseSysCallCRMask; // Mask used to test CR before x34-x37 | |
| fcee3895 SR |
54 | // doing an ASR switch on PASE |
| 55 | // system call. | |
| 56 | u64 xSlicSegmentTablePtr; // Pointer to Slic seg table. x38-x3f | |
| 57 | u8 xRsvd1_4[64]; // x40-x7F | |
| 58 | ||
| 1da177e4 | 59 | // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data |
| 1da177e4 LT |
60 | u8 xRsvd2_0[128]; // Reserved x00-x7F |
| 61 | ||
| 1da177e4 | 62 | // CACHE_LINE_3-6 0x0100 - 0x02FF Contains LP Queue indicators |
| 33567a02 | 63 | // NB: Padding required to keep xInterruptHdlr at x300 which is required |
| 1da177e4 | 64 | // for v4r4 PLIC. |
| 1da177e4 LT |
65 | u8 xOldLpQueue[128]; // LP Queue needed for v4r4 100-17F |
| 66 | u8 xRsvd3_0[384]; // Reserved 180-2FF | |
| fcee3895 | 67 | |
| 1da177e4 LT |
68 | // CACHE_LINE_7-8 0x0300 - 0x03FF Contains the address of the OS interrupt |
| 69 | // handlers | |
| 1da177e4 LT |
70 | u64 xInterruptHdlr[32]; // Interrupt handlers 300-x3FF |
| 71 | }; | |
| 72 | ||
| 0bc0ffd5 SR |
73 | extern struct ItLpNaca itLpNaca; |
| 74 | ||
| f9cb83ac SR |
75 | #define ITLPNACA_LPAR 0x80 /* Is LPAR installed on the system */ |
| 76 | #define ITLPNACA_PARTITIONED 0x40 /* Is the system partitioned */ | |
| 77 | #define ITLPNACA_HWSYNCEDTBS 0x20 /* Hardware synced TBs */ | |
| 78 | #define ITLPNACA_HMTINT 0x10 /* Utilize MHT for interrupts */ | |
| 79 | ||
| 06a36db1 | 80 | #endif /* _PLATFORMS_ISERIES_IT_LP_NACA_H */ |