Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001 Allan Trautman, IBM Corporation |
3 | * | |
4 | * iSeries specific routines for PCI. | |
d387899f | 5 | * |
1da177e4 LT |
6 | * Based on code from pci.c and iSeries_pci.c 32bit |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
d387899f | 12 | * |
1da177e4 LT |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
d387899f | 17 | * |
1da177e4 LT |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | #include <linux/kernel.h> | |
d387899f | 23 | #include <linux/list.h> |
1da177e4 LT |
24 | #include <linux/string.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/ide.h> | |
28 | #include <linux/pci.h> | |
29 | ||
30 | #include <asm/io.h> | |
31 | #include <asm/irq.h> | |
32 | #include <asm/prom.h> | |
33 | #include <asm/machdep.h> | |
34 | #include <asm/pci-bridge.h> | |
1da177e4 | 35 | #include <asm/iommu.h> |
426c1a11 | 36 | #include <asm/abs_addr.h> |
1da177e4 | 37 | |
8021b8a7 | 38 | #include <asm/iseries/hv_call_xm.h> |
bbc8b628 | 39 | #include <asm/iseries/mf.h> |
c7f0e8cb | 40 | #include <asm/iseries/iommu.h> |
1da177e4 | 41 | |
d387899f | 42 | #include <asm/ppc-pci.h> |
1da177e4 | 43 | |
b08567cb | 44 | #include "irq.h" |
426c1a11 | 45 | #include "pci.h" |
c6d2ea92 | 46 | #include "call_pci.h" |
b08567cb | 47 | |
1da177e4 | 48 | /* |
d387899f | 49 | * Forward declares of prototypes. |
1da177e4 | 50 | */ |
252e75a5 | 51 | static struct device_node *find_Device_Node(int bus, int devfn); |
1da177e4 LT |
52 | static void scan_PHB_slots(struct pci_controller *Phb); |
53 | static void scan_EADS_bridge(HvBusNumber Bus, HvSubBusNumber SubBus, int IdSel); | |
54 | static int scan_bridge_slot(HvBusNumber Bus, struct HvCallPci_BridgeInfo *Info); | |
55 | ||
56 | LIST_HEAD(iSeries_Global_Device_List); | |
57 | ||
58 | static int DeviceCount; | |
59 | ||
60 | /* Counters and control flags. */ | |
61 | static long Pci_Io_Read_Count; | |
62 | static long Pci_Io_Write_Count; | |
63 | #if 0 | |
64 | static long Pci_Cfg_Read_Count; | |
65 | static long Pci_Cfg_Write_Count; | |
66 | #endif | |
67 | static long Pci_Error_Count; | |
68 | ||
d387899f | 69 | static int Pci_Retry_Max = 3; /* Only retry 3 times */ |
1da177e4 LT |
70 | static int Pci_Error_Flag = 1; /* Set Retry Error on. */ |
71 | ||
72 | static struct pci_ops iSeries_pci_ops; | |
73 | ||
74 | /* | |
75 | * Table defines | |
76 | * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space. | |
77 | */ | |
78 | #define IOMM_TABLE_MAX_ENTRIES 1024 | |
79 | #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL | |
80 | #define BASE_IO_MEMORY 0xE000000000000000UL | |
81 | ||
82 | static unsigned long max_io_memory = 0xE000000000000000UL; | |
83 | static long current_iomm_table_entry; | |
84 | ||
85 | /* | |
86 | * Lookup Tables. | |
87 | */ | |
252e75a5 | 88 | static struct device_node **iomm_table; |
1da177e4 LT |
89 | static u8 *iobar_table; |
90 | ||
91 | /* | |
92 | * Static and Global variables | |
93 | */ | |
94 | static char *pci_io_text = "iSeries PCI I/O"; | |
95 | static DEFINE_SPINLOCK(iomm_table_lock); | |
96 | ||
97 | /* | |
98 | * iomm_table_initialize | |
99 | * | |
100 | * Allocates and initalizes the Address Translation Table and Bar | |
101 | * Tables to get them ready for use. Must be called before any | |
102 | * I/O space is handed out to the device BARs. | |
103 | */ | |
104 | static void iomm_table_initialize(void) | |
105 | { | |
106 | spin_lock(&iomm_table_lock); | |
107 | iomm_table = kmalloc(sizeof(*iomm_table) * IOMM_TABLE_MAX_ENTRIES, | |
108 | GFP_KERNEL); | |
109 | iobar_table = kmalloc(sizeof(*iobar_table) * IOMM_TABLE_MAX_ENTRIES, | |
110 | GFP_KERNEL); | |
111 | spin_unlock(&iomm_table_lock); | |
112 | if ((iomm_table == NULL) || (iobar_table == NULL)) | |
113 | panic("PCI: I/O tables allocation failed.\n"); | |
114 | } | |
115 | ||
116 | /* | |
117 | * iomm_table_allocate_entry | |
118 | * | |
119 | * Adds pci_dev entry in address translation table | |
120 | * | |
121 | * - Allocates the number of entries required in table base on BAR | |
122 | * size. | |
123 | * - Allocates starting at BASE_IO_MEMORY and increases. | |
124 | * - The size is round up to be a multiple of entry size. | |
125 | * - CurrentIndex is incremented to keep track of the last entry. | |
126 | * - Builds the resource entry for allocated BARs. | |
127 | */ | |
128 | static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num) | |
129 | { | |
130 | struct resource *bar_res = &dev->resource[bar_num]; | |
131 | long bar_size = pci_resource_len(dev, bar_num); | |
132 | ||
133 | /* | |
134 | * No space to allocate, quick exit, skip Allocation. | |
135 | */ | |
136 | if (bar_size == 0) | |
137 | return; | |
138 | /* | |
139 | * Set Resource values. | |
140 | */ | |
141 | spin_lock(&iomm_table_lock); | |
142 | bar_res->name = pci_io_text; | |
143 | bar_res->start = | |
144 | IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; | |
145 | bar_res->start += BASE_IO_MEMORY; | |
146 | bar_res->end = bar_res->start + bar_size - 1; | |
147 | /* | |
148 | * Allocate the number of table entries needed for BAR. | |
149 | */ | |
150 | while (bar_size > 0 ) { | |
151 | iomm_table[current_iomm_table_entry] = dev->sysdata; | |
152 | iobar_table[current_iomm_table_entry] = bar_num; | |
153 | bar_size -= IOMM_TABLE_ENTRY_SIZE; | |
154 | ++current_iomm_table_entry; | |
155 | } | |
156 | max_io_memory = BASE_IO_MEMORY + | |
157 | (IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry); | |
158 | spin_unlock(&iomm_table_lock); | |
159 | } | |
160 | ||
161 | /* | |
162 | * allocate_device_bars | |
163 | * | |
164 | * - Allocates ALL pci_dev BAR's and updates the resources with the | |
165 | * BAR value. BARS with zero length will have the resources | |
166 | * The HvCallPci_getBarParms is used to get the size of the BAR | |
167 | * space. It calls iomm_table_allocate_entry to allocate | |
168 | * each entry. | |
169 | * - Loops through The Bar resources(0 - 5) including the ROM | |
170 | * is resource(6). | |
171 | */ | |
172 | static void allocate_device_bars(struct pci_dev *dev) | |
173 | { | |
174 | struct resource *bar_res; | |
175 | int bar_num; | |
176 | ||
177 | for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) { | |
178 | bar_res = &dev->resource[bar_num]; | |
179 | iomm_table_allocate_entry(dev, bar_num); | |
d387899f | 180 | } |
1da177e4 LT |
181 | } |
182 | ||
183 | /* | |
184 | * Log error information to system console. | |
185 | * Filter out the device not there errors. | |
186 | * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx | |
187 | * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx | |
188 | * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx | |
189 | */ | |
190 | static void pci_Log_Error(char *Error_Text, int Bus, int SubBus, | |
191 | int AgentId, int HvRc) | |
192 | { | |
193 | if (HvRc == 0x0302) | |
194 | return; | |
195 | printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X", | |
196 | Error_Text, Bus, SubBus, AgentId, HvRc); | |
197 | } | |
198 | ||
199 | /* | |
200 | * build_device_node(u16 Bus, int SubBus, u8 DevFn) | |
201 | */ | |
252e75a5 | 202 | static struct device_node *build_device_node(HvBusNumber Bus, |
1da177e4 LT |
203 | HvSubBusNumber SubBus, int AgentId, int Function) |
204 | { | |
252e75a5 SR |
205 | struct device_node *node; |
206 | struct pci_dn *pdn; | |
1da177e4 | 207 | |
252e75a5 | 208 | node = kmalloc(sizeof(struct device_node), GFP_KERNEL); |
1da177e4 LT |
209 | if (node == NULL) |
210 | return NULL; | |
252e75a5 SR |
211 | memset(node, 0, sizeof(struct device_node)); |
212 | pdn = kzalloc(sizeof(*pdn), GFP_KERNEL); | |
213 | if (pdn == NULL) { | |
214 | kfree(node); | |
215 | return NULL; | |
216 | } | |
217 | node->data = pdn; | |
f255f0dd | 218 | pdn->node = node; |
76f9f87f | 219 | list_add_tail(&pdn->Device_List, &iSeries_Global_Device_List); |
20f48ccf SR |
220 | pdn->busno = Bus; |
221 | pdn->bussubno = SubBus; | |
252e75a5 | 222 | pdn->devfn = PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId), Function); |
1da177e4 LT |
223 | return node; |
224 | } | |
225 | ||
226 | /* | |
227 | * unsigned long __init find_and_init_phbs(void) | |
228 | * | |
229 | * Description: | |
230 | * This function checks for all possible system PCI host bridges that connect | |
231 | * PCI buses. The system hypervisor is queried as to the guest partition | |
232 | * ownership status. A pci_controller is built for any bus which is partially | |
233 | * owned or fully owned by this guest partition. | |
234 | */ | |
235 | unsigned long __init find_and_init_phbs(void) | |
236 | { | |
237 | struct pci_controller *phb; | |
238 | HvBusNumber bus; | |
239 | ||
1da177e4 LT |
240 | /* Check all possible buses. */ |
241 | for (bus = 0; bus < 256; bus++) { | |
242 | int ret = HvCallXm_testBus(bus); | |
243 | if (ret == 0) { | |
244 | printk("bus %d appears to exist\n", bus); | |
245 | ||
b5166cc2 | 246 | phb = pcibios_alloc_controller(NULL); |
1da177e4 LT |
247 | if (phb == NULL) |
248 | return -ENOMEM; | |
1da177e4 LT |
249 | |
250 | phb->pci_mem_offset = phb->local_number = bus; | |
251 | phb->first_busno = bus; | |
252 | phb->last_busno = bus; | |
253 | phb->ops = &iSeries_pci_ops; | |
254 | ||
1da177e4 LT |
255 | /* Find and connect the devices. */ |
256 | scan_PHB_slots(phb); | |
257 | } | |
258 | /* | |
259 | * Check for Unexpected Return code, a clue that something | |
260 | * has gone wrong. | |
261 | */ | |
262 | else if (ret != 0x0301) | |
263 | printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X", | |
264 | bus, ret); | |
265 | } | |
266 | return 0; | |
267 | } | |
268 | ||
269 | /* | |
270 | * iSeries_pcibios_init | |
d387899f | 271 | * |
1da177e4 LT |
272 | * Chance to initialize and structures or variable before PCI Bus walk. |
273 | */ | |
274 | void iSeries_pcibios_init(void) | |
275 | { | |
1da177e4 LT |
276 | iomm_table_initialize(); |
277 | find_and_init_phbs(); | |
1da177e4 LT |
278 | } |
279 | ||
280 | /* | |
d387899f | 281 | * iSeries_pci_final_fixup(void) |
1da177e4 LT |
282 | */ |
283 | void __init iSeries_pci_final_fixup(void) | |
284 | { | |
285 | struct pci_dev *pdev = NULL; | |
252e75a5 | 286 | struct device_node *node; |
d387899f | 287 | int DeviceCount = 0; |
1da177e4 | 288 | |
1da177e4 LT |
289 | /* Fix up at the device node and pci_dev relationship */ |
290 | mf_display_src(0xC9000100); | |
291 | ||
292 | printk("pcibios_final_fixup\n"); | |
293 | for_each_pci_dev(pdev) { | |
294 | node = find_Device_Node(pdev->bus->number, pdev->devfn); | |
295 | printk("pci dev %p (%x.%x), node %p\n", pdev, | |
296 | pdev->bus->number, pdev->devfn, node); | |
297 | ||
298 | if (node != NULL) { | |
299 | ++DeviceCount; | |
300 | pdev->sysdata = (void *)node; | |
252e75a5 | 301 | PCI_DN(node)->pcidev = pdev; |
1da177e4 | 302 | allocate_device_bars(pdev); |
061c063e | 303 | iSeries_Device_Information(pdev, DeviceCount); |
1da177e4 LT |
304 | iommu_devnode_init_iSeries(node); |
305 | } else | |
306 | printk("PCI: Device Tree not found for 0x%016lX\n", | |
307 | (unsigned long)pdev); | |
252e75a5 | 308 | pdev->irq = PCI_DN(node)->Irq; |
1da177e4 LT |
309 | } |
310 | iSeries_activate_IRQs(); | |
311 | mf_display_src(0xC9000200); | |
312 | } | |
313 | ||
314 | void pcibios_fixup_bus(struct pci_bus *PciBus) | |
315 | { | |
1da177e4 LT |
316 | } |
317 | ||
318 | void pcibios_fixup_resources(struct pci_dev *pdev) | |
319 | { | |
d387899f | 320 | } |
1da177e4 LT |
321 | |
322 | /* | |
d387899f | 323 | * Loop through each node function to find usable EADs bridges. |
1da177e4 LT |
324 | */ |
325 | static void scan_PHB_slots(struct pci_controller *Phb) | |
326 | { | |
327 | struct HvCallPci_DeviceInfo *DevInfo; | |
d387899f | 328 | HvBusNumber bus = Phb->local_number; /* System Bus */ |
1da177e4 LT |
329 | const HvSubBusNumber SubBus = 0; /* EADs is always 0. */ |
330 | int HvRc = 0; | |
d387899f | 331 | int IdSel; |
1da177e4 LT |
332 | const int MaxAgents = 8; |
333 | ||
334 | DevInfo = (struct HvCallPci_DeviceInfo*) | |
335 | kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL); | |
336 | if (DevInfo == NULL) | |
337 | return; | |
338 | ||
339 | /* | |
d387899f | 340 | * Probe for EADs Bridges |
1da177e4 LT |
341 | */ |
342 | for (IdSel = 1; IdSel < MaxAgents; ++IdSel) { | |
d387899f | 343 | HvRc = HvCallPci_getDeviceInfo(bus, SubBus, IdSel, |
426c1a11 | 344 | iseries_hv_addr(DevInfo), |
1da177e4 LT |
345 | sizeof(struct HvCallPci_DeviceInfo)); |
346 | if (HvRc == 0) { | |
347 | if (DevInfo->deviceType == HvCallPci_NodeDevice) | |
348 | scan_EADS_bridge(bus, SubBus, IdSel); | |
349 | else | |
350 | printk("PCI: Invalid System Configuration(0x%02X)" | |
351 | " for bus 0x%02x id 0x%02x.\n", | |
352 | DevInfo->deviceType, bus, IdSel); | |
353 | } | |
354 | else | |
355 | pci_Log_Error("getDeviceInfo", bus, SubBus, IdSel, HvRc); | |
356 | } | |
357 | kfree(DevInfo); | |
358 | } | |
359 | ||
360 | static void scan_EADS_bridge(HvBusNumber bus, HvSubBusNumber SubBus, | |
361 | int IdSel) | |
362 | { | |
363 | struct HvCallPci_BridgeInfo *BridgeInfo; | |
364 | HvAgentId AgentId; | |
365 | int Function; | |
366 | int HvRc; | |
367 | ||
368 | BridgeInfo = (struct HvCallPci_BridgeInfo *) | |
369 | kmalloc(sizeof(struct HvCallPci_BridgeInfo), GFP_KERNEL); | |
370 | if (BridgeInfo == NULL) | |
371 | return; | |
372 | ||
373 | /* Note: hvSubBus and irq is always be 0 at this level! */ | |
374 | for (Function = 0; Function < 8; ++Function) { | |
d387899f | 375 | AgentId = ISERIES_PCI_AGENTID(IdSel, Function); |
1da177e4 | 376 | HvRc = HvCallXm_connectBusUnit(bus, SubBus, AgentId, 0); |
d387899f | 377 | if (HvRc == 0) { |
1da177e4 LT |
378 | printk("found device at bus %d idsel %d func %d (AgentId %x)\n", |
379 | bus, IdSel, Function, AgentId); | |
d387899f | 380 | /* Connect EADs: 0x18.00.12 = 0x00 */ |
d387899f | 381 | HvRc = HvCallPci_getBusUnitInfo(bus, SubBus, AgentId, |
426c1a11 | 382 | iseries_hv_addr(BridgeInfo), |
1da177e4 | 383 | sizeof(struct HvCallPci_BridgeInfo)); |
d387899f | 384 | if (HvRc == 0) { |
1da177e4 LT |
385 | printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n", |
386 | BridgeInfo->busUnitInfo.deviceType, | |
387 | BridgeInfo->subBusNumber, | |
388 | BridgeInfo->maxAgents, | |
389 | BridgeInfo->maxSubBusNumber, | |
390 | BridgeInfo->logicalSlotNumber); | |
1da177e4 LT |
391 | if (BridgeInfo->busUnitInfo.deviceType == |
392 | HvCallPci_BridgeDevice) { | |
393 | /* Scan_Bridge_Slot...: 0x18.00.12 */ | |
394 | scan_bridge_slot(bus, BridgeInfo); | |
395 | } else | |
396 | printk("PCI: Invalid Bridge Configuration(0x%02X)", | |
397 | BridgeInfo->busUnitInfo.deviceType); | |
398 | } | |
d387899f | 399 | } else if (HvRc != 0x000B) |
1da177e4 LT |
400 | pci_Log_Error("EADs Connect", |
401 | bus, SubBus, AgentId, HvRc); | |
402 | } | |
403 | kfree(BridgeInfo); | |
404 | } | |
405 | ||
406 | /* | |
407 | * This assumes that the node slot is always on the primary bus! | |
408 | */ | |
409 | static int scan_bridge_slot(HvBusNumber Bus, | |
410 | struct HvCallPci_BridgeInfo *BridgeInfo) | |
411 | { | |
252e75a5 | 412 | struct device_node *node; |
1da177e4 LT |
413 | HvSubBusNumber SubBus = BridgeInfo->subBusNumber; |
414 | u16 VendorId = 0; | |
415 | int HvRc = 0; | |
416 | u8 Irq = 0; | |
417 | int IdSel = ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus); | |
418 | int Function = ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus); | |
419 | HvAgentId EADsIdSel = ISERIES_PCI_AGENTID(IdSel, Function); | |
420 | ||
421 | /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */ | |
d387899f | 422 | Irq = iSeries_allocate_IRQ(Bus, 0, EADsIdSel); |
1da177e4 LT |
423 | |
424 | /* | |
d387899f | 425 | * Connect all functions of any device found. |
1da177e4 | 426 | */ |
d387899f SR |
427 | for (IdSel = 1; IdSel <= BridgeInfo->maxAgents; ++IdSel) { |
428 | for (Function = 0; Function < 8; ++Function) { | |
1da177e4 LT |
429 | HvAgentId AgentId = ISERIES_PCI_AGENTID(IdSel, Function); |
430 | HvRc = HvCallXm_connectBusUnit(Bus, SubBus, | |
431 | AgentId, Irq); | |
432 | if (HvRc != 0) { | |
433 | pci_Log_Error("Connect Bus Unit", | |
434 | Bus, SubBus, AgentId, HvRc); | |
435 | continue; | |
436 | } | |
437 | ||
438 | HvRc = HvCallPci_configLoad16(Bus, SubBus, AgentId, | |
439 | PCI_VENDOR_ID, &VendorId); | |
440 | if (HvRc != 0) { | |
441 | pci_Log_Error("Read Vendor", | |
442 | Bus, SubBus, AgentId, HvRc); | |
443 | continue; | |
444 | } | |
445 | printk("read vendor ID: %x\n", VendorId); | |
446 | ||
447 | /* FoundDevice: 0x18.28.10 = 0x12AE */ | |
1da177e4 | 448 | HvRc = HvCallPci_configStore8(Bus, SubBus, AgentId, |
d387899f | 449 | PCI_INTERRUPT_LINE, Irq); |
1da177e4 LT |
450 | if (HvRc != 0) |
451 | pci_Log_Error("PciCfgStore Irq Failed!", | |
452 | Bus, SubBus, AgentId, HvRc); | |
453 | ||
454 | ++DeviceCount; | |
455 | node = build_device_node(Bus, SubBus, EADsIdSel, Function); | |
252e75a5 SR |
456 | PCI_DN(node)->Irq = Irq; |
457 | PCI_DN(node)->LogicalSlot = BridgeInfo->logicalSlotNumber; | |
1da177e4 LT |
458 | |
459 | } /* for (Function = 0; Function < 8; ++Function) */ | |
460 | } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */ | |
461 | return HvRc; | |
462 | } | |
463 | ||
464 | /* | |
465 | * I/0 Memory copy MUST use mmio commands on iSeries | |
466 | * To do; For performance, include the hv call directly | |
467 | */ | |
468 | void iSeries_memset_io(volatile void __iomem *dest, char c, size_t Count) | |
469 | { | |
470 | u8 ByteValue = c; | |
471 | long NumberOfBytes = Count; | |
472 | ||
473 | while (NumberOfBytes > 0) { | |
474 | iSeries_Write_Byte(ByteValue, dest++); | |
475 | -- NumberOfBytes; | |
476 | } | |
477 | } | |
478 | EXPORT_SYMBOL(iSeries_memset_io); | |
479 | ||
480 | void iSeries_memcpy_toio(volatile void __iomem *dest, void *source, size_t count) | |
481 | { | |
482 | char *src = source; | |
483 | long NumberOfBytes = count; | |
484 | ||
485 | while (NumberOfBytes > 0) { | |
486 | iSeries_Write_Byte(*src++, dest++); | |
487 | -- NumberOfBytes; | |
488 | } | |
489 | } | |
490 | EXPORT_SYMBOL(iSeries_memcpy_toio); | |
491 | ||
492 | void iSeries_memcpy_fromio(void *dest, const volatile void __iomem *src, size_t count) | |
493 | { | |
494 | char *dst = dest; | |
495 | long NumberOfBytes = count; | |
496 | ||
497 | while (NumberOfBytes > 0) { | |
498 | *dst++ = iSeries_Read_Byte(src++); | |
499 | -- NumberOfBytes; | |
500 | } | |
501 | } | |
502 | EXPORT_SYMBOL(iSeries_memcpy_fromio); | |
503 | ||
504 | /* | |
505 | * Look down the chain to find the matching Device Device | |
506 | */ | |
252e75a5 | 507 | static struct device_node *find_Device_Node(int bus, int devfn) |
1da177e4 | 508 | { |
76f9f87f | 509 | struct pci_dn *pdn; |
1da177e4 | 510 | |
76f9f87f | 511 | list_for_each_entry(pdn, &iSeries_Global_Device_List, Device_List) { |
20f48ccf | 512 | if ((bus == pdn->busno) && (devfn == pdn->devfn)) |
76f9f87f | 513 | return pdn->node; |
1da177e4 LT |
514 | } |
515 | return NULL; | |
516 | } | |
517 | ||
518 | #if 0 | |
519 | /* | |
520 | * Returns the device node for the passed pci_dev | |
521 | * Sanity Check Node PciDev to passed pci_dev | |
522 | * If none is found, returns a NULL which the client must handle. | |
523 | */ | |
252e75a5 | 524 | static struct device_node *get_Device_Node(struct pci_dev *pdev) |
1da177e4 | 525 | { |
252e75a5 | 526 | struct device_node *node; |
1da177e4 LT |
527 | |
528 | node = pdev->sysdata; | |
252e75a5 | 529 | if (node == NULL || PCI_DN(node)->pcidev != pdev) |
1da177e4 LT |
530 | node = find_Device_Node(pdev->bus->number, pdev->devfn); |
531 | return node; | |
532 | } | |
533 | #endif | |
534 | ||
535 | /* | |
536 | * Config space read and write functions. | |
537 | * For now at least, we look for the device node for the bus and devfn | |
538 | * that we are asked to access. It may be possible to translate the devfn | |
539 | * to a subbus and deviceid more directly. | |
540 | */ | |
541 | static u64 hv_cfg_read_func[4] = { | |
542 | HvCallPciConfigLoad8, HvCallPciConfigLoad16, | |
543 | HvCallPciConfigLoad32, HvCallPciConfigLoad32 | |
544 | }; | |
545 | ||
546 | static u64 hv_cfg_write_func[4] = { | |
547 | HvCallPciConfigStore8, HvCallPciConfigStore16, | |
548 | HvCallPciConfigStore32, HvCallPciConfigStore32 | |
549 | }; | |
550 | ||
551 | /* | |
552 | * Read PCI config space | |
553 | */ | |
554 | static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn, | |
555 | int offset, int size, u32 *val) | |
556 | { | |
252e75a5 | 557 | struct device_node *node = find_Device_Node(bus->number, devfn); |
1da177e4 LT |
558 | u64 fn; |
559 | struct HvCallPci_LoadReturn ret; | |
560 | ||
561 | if (node == NULL) | |
562 | return PCIBIOS_DEVICE_NOT_FOUND; | |
563 | if (offset > 255) { | |
564 | *val = ~0; | |
565 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
566 | } | |
567 | ||
568 | fn = hv_cfg_read_func[(size - 1) & 3]; | |
20f48ccf | 569 | HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0); |
1da177e4 LT |
570 | |
571 | if (ret.rc != 0) { | |
572 | *val = ~0; | |
573 | return PCIBIOS_DEVICE_NOT_FOUND; /* or something */ | |
574 | } | |
575 | ||
576 | *val = ret.value; | |
577 | return 0; | |
578 | } | |
579 | ||
580 | /* | |
581 | * Write PCI config space | |
582 | */ | |
583 | ||
584 | static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn, | |
585 | int offset, int size, u32 val) | |
586 | { | |
252e75a5 | 587 | struct device_node *node = find_Device_Node(bus->number, devfn); |
1da177e4 LT |
588 | u64 fn; |
589 | u64 ret; | |
590 | ||
591 | if (node == NULL) | |
592 | return PCIBIOS_DEVICE_NOT_FOUND; | |
593 | if (offset > 255) | |
594 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
595 | ||
596 | fn = hv_cfg_write_func[(size - 1) & 3]; | |
20f48ccf | 597 | ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0); |
1da177e4 LT |
598 | |
599 | if (ret != 0) | |
600 | return PCIBIOS_DEVICE_NOT_FOUND; | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | static struct pci_ops iSeries_pci_ops = { | |
606 | .read = iSeries_pci_read_config, | |
607 | .write = iSeries_pci_write_config | |
608 | }; | |
609 | ||
610 | /* | |
611 | * Check Return Code | |
612 | * -> On Failure, print and log information. | |
613 | * Increment Retry Count, if exceeds max, panic partition. | |
1da177e4 LT |
614 | * |
615 | * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234 | |
616 | * PCI: Device 23.90 ReadL Retry( 1) | |
617 | * PCI: Device 23.90 ReadL Retry Successful(1) | |
618 | */ | |
252e75a5 | 619 | static int CheckReturnCode(char *TextHdr, struct device_node *DevNode, |
a2ebaf25 | 620 | int *retry, u64 ret) |
1da177e4 LT |
621 | { |
622 | if (ret != 0) { | |
252e75a5 SR |
623 | struct pci_dn *pdn = PCI_DN(DevNode); |
624 | ||
1da177e4 | 625 | ++Pci_Error_Count; |
a2ebaf25 | 626 | (*retry)++; |
1da177e4 | 627 | printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n", |
20f48ccf | 628 | TextHdr, pdn->busno, pdn->devfn, |
a2ebaf25 | 629 | *retry, (int)ret); |
1da177e4 LT |
630 | /* |
631 | * Bump the retry and check for retry count exceeded. | |
632 | * If, Exceeded, panic the system. | |
633 | */ | |
a2ebaf25 | 634 | if (((*retry) > Pci_Retry_Max) && |
1da177e4 LT |
635 | (Pci_Error_Flag > 0)) { |
636 | mf_display_src(0xB6000103); | |
a2ebaf25 | 637 | panic_timeout = 0; |
1da177e4 LT |
638 | panic("PCI: Hardware I/O Error, SRC B6000103, " |
639 | "Automatic Reboot Disabled.\n"); | |
640 | } | |
641 | return -1; /* Retry Try */ | |
642 | } | |
a2ebaf25 | 643 | return 0; |
1da177e4 LT |
644 | } |
645 | ||
646 | /* | |
647 | * Translate the I/O Address into a device node, bar, and bar offset. | |
648 | * Note: Make sure the passed variable end up on the stack to avoid | |
649 | * the exposure of being device global. | |
650 | */ | |
252e75a5 | 651 | static inline struct device_node *xlate_iomm_address( |
1da177e4 LT |
652 | const volatile void __iomem *IoAddress, |
653 | u64 *dsaptr, u64 *BarOffsetPtr) | |
654 | { | |
655 | unsigned long OrigIoAddr; | |
656 | unsigned long BaseIoAddr; | |
657 | unsigned long TableIndex; | |
252e75a5 | 658 | struct device_node *DevNode; |
1da177e4 LT |
659 | |
660 | OrigIoAddr = (unsigned long __force)IoAddress; | |
661 | if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory)) | |
662 | return NULL; | |
663 | BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY; | |
664 | TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE; | |
665 | DevNode = iomm_table[TableIndex]; | |
666 | ||
667 | if (DevNode != NULL) { | |
668 | int barnum = iobar_table[TableIndex]; | |
20f48ccf | 669 | *dsaptr = iseries_ds_addr(DevNode) | (barnum << 24); |
1da177e4 LT |
670 | *BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE; |
671 | } else | |
672 | panic("PCI: Invalid PCI IoAddress detected!\n"); | |
673 | return DevNode; | |
674 | } | |
675 | ||
676 | /* | |
677 | * Read MM I/O Instructions for the iSeries | |
678 | * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal | |
679 | * else, data is returned in big Endian format. | |
680 | * | |
681 | * iSeries_Read_Byte = Read Byte ( 8 bit) | |
682 | * iSeries_Read_Word = Read Word (16 bit) | |
683 | * iSeries_Read_Long = Read Long (32 bit) | |
684 | */ | |
685 | u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress) | |
686 | { | |
687 | u64 BarOffset; | |
688 | u64 dsa; | |
a2ebaf25 | 689 | int retry = 0; |
1da177e4 | 690 | struct HvCallPci_LoadReturn ret; |
252e75a5 | 691 | struct device_node *DevNode = |
1da177e4 LT |
692 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
693 | ||
694 | if (DevNode == NULL) { | |
695 | static unsigned long last_jiffies; | |
696 | static int num_printed; | |
697 | ||
698 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
699 | last_jiffies = jiffies; | |
700 | num_printed = 0; | |
701 | } | |
702 | if (num_printed++ < 10) | |
703 | printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress); | |
704 | return 0xff; | |
705 | } | |
706 | do { | |
707 | ++Pci_Io_Read_Count; | |
708 | HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0); | |
a2ebaf25 | 709 | } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0); |
1da177e4 LT |
710 | |
711 | return (u8)ret.value; | |
712 | } | |
713 | EXPORT_SYMBOL(iSeries_Read_Byte); | |
714 | ||
715 | u16 iSeries_Read_Word(const volatile void __iomem *IoAddress) | |
716 | { | |
717 | u64 BarOffset; | |
718 | u64 dsa; | |
a2ebaf25 | 719 | int retry = 0; |
1da177e4 | 720 | struct HvCallPci_LoadReturn ret; |
252e75a5 | 721 | struct device_node *DevNode = |
1da177e4 LT |
722 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
723 | ||
724 | if (DevNode == NULL) { | |
725 | static unsigned long last_jiffies; | |
726 | static int num_printed; | |
727 | ||
728 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
729 | last_jiffies = jiffies; | |
730 | num_printed = 0; | |
731 | } | |
732 | if (num_printed++ < 10) | |
733 | printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", IoAddress); | |
734 | return 0xffff; | |
735 | } | |
736 | do { | |
737 | ++Pci_Io_Read_Count; | |
738 | HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa, | |
739 | BarOffset, 0); | |
a2ebaf25 | 740 | } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0); |
1da177e4 LT |
741 | |
742 | return swab16((u16)ret.value); | |
743 | } | |
744 | EXPORT_SYMBOL(iSeries_Read_Word); | |
745 | ||
746 | u32 iSeries_Read_Long(const volatile void __iomem *IoAddress) | |
747 | { | |
748 | u64 BarOffset; | |
749 | u64 dsa; | |
a2ebaf25 | 750 | int retry = 0; |
1da177e4 | 751 | struct HvCallPci_LoadReturn ret; |
252e75a5 | 752 | struct device_node *DevNode = |
1da177e4 LT |
753 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
754 | ||
755 | if (DevNode == NULL) { | |
756 | static unsigned long last_jiffies; | |
757 | static int num_printed; | |
758 | ||
759 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
760 | last_jiffies = jiffies; | |
761 | num_printed = 0; | |
762 | } | |
763 | if (num_printed++ < 10) | |
764 | printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", IoAddress); | |
765 | return 0xffffffff; | |
766 | } | |
767 | do { | |
768 | ++Pci_Io_Read_Count; | |
769 | HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa, | |
770 | BarOffset, 0); | |
a2ebaf25 | 771 | } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0); |
1da177e4 LT |
772 | |
773 | return swab32((u32)ret.value); | |
774 | } | |
775 | EXPORT_SYMBOL(iSeries_Read_Long); | |
776 | ||
777 | /* | |
778 | * Write MM I/O Instructions for the iSeries | |
779 | * | |
780 | * iSeries_Write_Byte = Write Byte (8 bit) | |
781 | * iSeries_Write_Word = Write Word(16 bit) | |
782 | * iSeries_Write_Long = Write Long(32 bit) | |
783 | */ | |
784 | void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress) | |
785 | { | |
786 | u64 BarOffset; | |
787 | u64 dsa; | |
a2ebaf25 | 788 | int retry = 0; |
1da177e4 | 789 | u64 rc; |
252e75a5 | 790 | struct device_node *DevNode = |
1da177e4 LT |
791 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
792 | ||
793 | if (DevNode == NULL) { | |
794 | static unsigned long last_jiffies; | |
795 | static int num_printed; | |
796 | ||
797 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
798 | last_jiffies = jiffies; | |
799 | num_printed = 0; | |
800 | } | |
801 | if (num_printed++ < 10) | |
802 | printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress); | |
803 | return; | |
804 | } | |
805 | do { | |
806 | ++Pci_Io_Write_Count; | |
807 | rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0); | |
a2ebaf25 | 808 | } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0); |
1da177e4 LT |
809 | } |
810 | EXPORT_SYMBOL(iSeries_Write_Byte); | |
811 | ||
812 | void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress) | |
813 | { | |
814 | u64 BarOffset; | |
815 | u64 dsa; | |
a2ebaf25 | 816 | int retry = 0; |
1da177e4 | 817 | u64 rc; |
252e75a5 | 818 | struct device_node *DevNode = |
1da177e4 LT |
819 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
820 | ||
821 | if (DevNode == NULL) { | |
822 | static unsigned long last_jiffies; | |
823 | static int num_printed; | |
824 | ||
825 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
826 | last_jiffies = jiffies; | |
827 | num_printed = 0; | |
828 | } | |
829 | if (num_printed++ < 10) | |
830 | printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", IoAddress); | |
831 | return; | |
832 | } | |
833 | do { | |
834 | ++Pci_Io_Write_Count; | |
835 | rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0); | |
a2ebaf25 | 836 | } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0); |
1da177e4 LT |
837 | } |
838 | EXPORT_SYMBOL(iSeries_Write_Word); | |
839 | ||
840 | void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress) | |
841 | { | |
842 | u64 BarOffset; | |
843 | u64 dsa; | |
a2ebaf25 | 844 | int retry = 0; |
1da177e4 | 845 | u64 rc; |
252e75a5 | 846 | struct device_node *DevNode = |
1da177e4 LT |
847 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
848 | ||
849 | if (DevNode == NULL) { | |
850 | static unsigned long last_jiffies; | |
851 | static int num_printed; | |
852 | ||
853 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
854 | last_jiffies = jiffies; | |
855 | num_printed = 0; | |
856 | } | |
857 | if (num_printed++ < 10) | |
858 | printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", IoAddress); | |
859 | return; | |
860 | } | |
861 | do { | |
862 | ++Pci_Io_Write_Count; | |
863 | rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0); | |
a2ebaf25 | 864 | } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0); |
1da177e4 LT |
865 | } |
866 | EXPORT_SYMBOL(iSeries_Write_Long); |