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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
3 | * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu> | |
4 | * | |
1da177e4 LT |
5 | * Description: |
6 | * Architecture- / platform-specific boot-time initialization code for | |
7 | * the IBM iSeries LPAR. Adapted from original code by Grant Erickson and | |
8 | * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek | |
9 | * <dan@net4x.com>. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | */ | |
16 | ||
17 | #undef DEBUG | |
18 | ||
19 | #include <linux/config.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/threads.h> | |
22 | #include <linux/smp.h> | |
23 | #include <linux/param.h> | |
24 | #include <linux/string.h> | |
1da177e4 LT |
25 | #include <linux/initrd.h> |
26 | #include <linux/seq_file.h> | |
27 | #include <linux/kdev_t.h> | |
28 | #include <linux/major.h> | |
29 | #include <linux/root_dev.h> | |
bec7c458 | 30 | #include <linux/kernel.h> |
1da177e4 LT |
31 | |
32 | #include <asm/processor.h> | |
33 | #include <asm/machdep.h> | |
34 | #include <asm/page.h> | |
35 | #include <asm/mmu.h> | |
36 | #include <asm/pgtable.h> | |
37 | #include <asm/mmu_context.h> | |
38 | #include <asm/cputable.h> | |
39 | #include <asm/sections.h> | |
40 | #include <asm/iommu.h> | |
aed31351 | 41 | #include <asm/firmware.h> |
49b09853 | 42 | #include <asm/system.h> |
1da177e4 | 43 | #include <asm/time.h> |
1da177e4 LT |
44 | #include <asm/paca.h> |
45 | #include <asm/cache.h> | |
46 | #include <asm/sections.h> | |
0bc0ffd5 | 47 | #include <asm/abs_addr.h> |
15b17189 | 48 | #include <asm/iseries/hv_lp_config.h> |
c0a8d05c | 49 | #include <asm/iseries/hv_call_event.h> |
8021b8a7 | 50 | #include <asm/iseries/hv_call_xm.h> |
8875ccfb | 51 | #include <asm/iseries/it_lp_queue.h> |
bbc8b628 | 52 | #include <asm/iseries/mf.h> |
e45423ea | 53 | #include <asm/iseries/hv_lp_event.h> |
c43a55ff | 54 | #include <asm/iseries/lpar_map.h> |
bf6a7112 | 55 | #include <asm/udbg.h> |
1da177e4 | 56 | |
f11b7bd8 | 57 | #include "naca.h" |
c8b84976 | 58 | #include "setup.h" |
b08567cb SR |
59 | #include "irq.h" |
60 | #include "vpd_areas.h" | |
61 | #include "processor_vpd.h" | |
62 | #include "main_store.h" | |
63 | #include "call_sm.h" | |
0e29bb1a | 64 | #include "call_hpt.h" |
c8b84976 | 65 | |
1da177e4 | 66 | #ifdef DEBUG |
bf6a7112 | 67 | #define DBG(fmt...) udbg_printf(fmt) |
1da177e4 LT |
68 | #else |
69 | #define DBG(fmt...) | |
70 | #endif | |
71 | ||
72 | /* Function Prototypes */ | |
799d6046 | 73 | static unsigned long build_iSeries_Memory_Map(void); |
143a1dec PM |
74 | static void iseries_shared_idle(void); |
75 | static void iseries_dedicated_idle(void); | |
145d01e4 | 76 | #ifdef CONFIG_PCI |
1da177e4 | 77 | extern void iSeries_pci_final_fixup(void); |
145d01e4 SR |
78 | #else |
79 | static void iSeries_pci_final_fixup(void) { } | |
80 | #endif | |
1da177e4 LT |
81 | |
82 | /* Global Variables */ | |
1da177e4 LT |
83 | int piranha_simulator; |
84 | ||
85 | extern int rd_size; /* Defined in drivers/block/rd.c */ | |
1da177e4 LT |
86 | extern unsigned long embedded_sysmap_start; |
87 | extern unsigned long embedded_sysmap_end; | |
88 | ||
89 | extern unsigned long iSeries_recal_tb; | |
90 | extern unsigned long iSeries_recal_titan; | |
91 | ||
92 | static int mf_initialized; | |
93 | ||
bec7c458 SR |
94 | static unsigned long cmd_mem_limit; |
95 | ||
1da177e4 LT |
96 | struct MemoryBlock { |
97 | unsigned long absStart; | |
98 | unsigned long absEnd; | |
99 | unsigned long logicalStart; | |
100 | unsigned long logicalEnd; | |
101 | }; | |
102 | ||
103 | /* | |
104 | * Process the main store vpd to determine where the holes in memory are | |
105 | * and return the number of physical blocks and fill in the array of | |
106 | * block data. | |
107 | */ | |
108 | static unsigned long iSeries_process_Condor_mainstore_vpd( | |
109 | struct MemoryBlock *mb_array, unsigned long max_entries) | |
110 | { | |
111 | unsigned long holeFirstChunk, holeSizeChunks; | |
112 | unsigned long numMemoryBlocks = 1; | |
113 | struct IoHriMainStoreSegment4 *msVpd = | |
114 | (struct IoHriMainStoreSegment4 *)xMsVpd; | |
115 | unsigned long holeStart = msVpd->nonInterleavedBlocksStartAdr; | |
116 | unsigned long holeEnd = msVpd->nonInterleavedBlocksEndAdr; | |
117 | unsigned long holeSize = holeEnd - holeStart; | |
118 | ||
119 | printk("Mainstore_VPD: Condor\n"); | |
120 | /* | |
121 | * Determine if absolute memory has any | |
122 | * holes so that we can interpret the | |
123 | * access map we get back from the hypervisor | |
124 | * correctly. | |
125 | */ | |
126 | mb_array[0].logicalStart = 0; | |
127 | mb_array[0].logicalEnd = 0x100000000; | |
128 | mb_array[0].absStart = 0; | |
129 | mb_array[0].absEnd = 0x100000000; | |
130 | ||
131 | if (holeSize) { | |
132 | numMemoryBlocks = 2; | |
133 | holeStart = holeStart & 0x000fffffffffffff; | |
134 | holeStart = addr_to_chunk(holeStart); | |
135 | holeFirstChunk = holeStart; | |
136 | holeSize = addr_to_chunk(holeSize); | |
137 | holeSizeChunks = holeSize; | |
138 | printk( "Main store hole: start chunk = %0lx, size = %0lx chunks\n", | |
139 | holeFirstChunk, holeSizeChunks ); | |
140 | mb_array[0].logicalEnd = holeFirstChunk; | |
141 | mb_array[0].absEnd = holeFirstChunk; | |
142 | mb_array[1].logicalStart = holeFirstChunk; | |
143 | mb_array[1].logicalEnd = 0x100000000 - holeSizeChunks; | |
144 | mb_array[1].absStart = holeFirstChunk + holeSizeChunks; | |
145 | mb_array[1].absEnd = 0x100000000; | |
146 | } | |
147 | return numMemoryBlocks; | |
148 | } | |
149 | ||
150 | #define MaxSegmentAreas 32 | |
151 | #define MaxSegmentAdrRangeBlocks 128 | |
152 | #define MaxAreaRangeBlocks 4 | |
153 | ||
154 | static unsigned long iSeries_process_Regatta_mainstore_vpd( | |
155 | struct MemoryBlock *mb_array, unsigned long max_entries) | |
156 | { | |
157 | struct IoHriMainStoreSegment5 *msVpdP = | |
158 | (struct IoHriMainStoreSegment5 *)xMsVpd; | |
159 | unsigned long numSegmentBlocks = 0; | |
160 | u32 existsBits = msVpdP->msAreaExists; | |
161 | unsigned long area_num; | |
162 | ||
163 | printk("Mainstore_VPD: Regatta\n"); | |
164 | ||
165 | for (area_num = 0; area_num < MaxSegmentAreas; ++area_num ) { | |
166 | unsigned long numAreaBlocks; | |
167 | struct IoHriMainStoreArea4 *currentArea; | |
168 | ||
169 | if (existsBits & 0x80000000) { | |
170 | unsigned long block_num; | |
171 | ||
172 | currentArea = &msVpdP->msAreaArray[area_num]; | |
173 | numAreaBlocks = currentArea->numAdrRangeBlocks; | |
174 | printk("ms_vpd: processing area %2ld blocks=%ld", | |
175 | area_num, numAreaBlocks); | |
176 | for (block_num = 0; block_num < numAreaBlocks; | |
177 | ++block_num ) { | |
178 | /* Process an address range block */ | |
179 | struct MemoryBlock tempBlock; | |
180 | unsigned long i; | |
181 | ||
182 | tempBlock.absStart = | |
183 | (unsigned long)currentArea->xAdrRangeBlock[block_num].blockStart; | |
184 | tempBlock.absEnd = | |
185 | (unsigned long)currentArea->xAdrRangeBlock[block_num].blockEnd; | |
186 | tempBlock.logicalStart = 0; | |
187 | tempBlock.logicalEnd = 0; | |
188 | printk("\n block %ld absStart=%016lx absEnd=%016lx", | |
189 | block_num, tempBlock.absStart, | |
190 | tempBlock.absEnd); | |
191 | ||
192 | for (i = 0; i < numSegmentBlocks; ++i) { | |
193 | if (mb_array[i].absStart == | |
194 | tempBlock.absStart) | |
195 | break; | |
196 | } | |
197 | if (i == numSegmentBlocks) { | |
198 | if (numSegmentBlocks == max_entries) | |
199 | panic("iSeries_process_mainstore_vpd: too many memory blocks"); | |
200 | mb_array[numSegmentBlocks] = tempBlock; | |
201 | ++numSegmentBlocks; | |
202 | } else | |
203 | printk(" (duplicate)"); | |
204 | } | |
205 | printk("\n"); | |
206 | } | |
207 | existsBits <<= 1; | |
208 | } | |
209 | /* Now sort the blocks found into ascending sequence */ | |
210 | if (numSegmentBlocks > 1) { | |
211 | unsigned long m, n; | |
212 | ||
213 | for (m = 0; m < numSegmentBlocks - 1; ++m) { | |
214 | for (n = numSegmentBlocks - 1; m < n; --n) { | |
215 | if (mb_array[n].absStart < | |
216 | mb_array[n-1].absStart) { | |
217 | struct MemoryBlock tempBlock; | |
218 | ||
219 | tempBlock = mb_array[n]; | |
220 | mb_array[n] = mb_array[n-1]; | |
221 | mb_array[n-1] = tempBlock; | |
222 | } | |
223 | } | |
224 | } | |
225 | } | |
226 | /* | |
227 | * Assign "logical" addresses to each block. These | |
228 | * addresses correspond to the hypervisor "bitmap" space. | |
229 | * Convert all addresses into units of 256K chunks. | |
230 | */ | |
231 | { | |
232 | unsigned long i, nextBitmapAddress; | |
233 | ||
234 | printk("ms_vpd: %ld sorted memory blocks\n", numSegmentBlocks); | |
235 | nextBitmapAddress = 0; | |
236 | for (i = 0; i < numSegmentBlocks; ++i) { | |
237 | unsigned long length = mb_array[i].absEnd - | |
238 | mb_array[i].absStart; | |
239 | ||
240 | mb_array[i].logicalStart = nextBitmapAddress; | |
241 | mb_array[i].logicalEnd = nextBitmapAddress + length; | |
242 | nextBitmapAddress += length; | |
243 | printk(" Bitmap range: %016lx - %016lx\n" | |
244 | " Absolute range: %016lx - %016lx\n", | |
245 | mb_array[i].logicalStart, | |
246 | mb_array[i].logicalEnd, | |
247 | mb_array[i].absStart, mb_array[i].absEnd); | |
248 | mb_array[i].absStart = addr_to_chunk(mb_array[i].absStart & | |
249 | 0x000fffffffffffff); | |
250 | mb_array[i].absEnd = addr_to_chunk(mb_array[i].absEnd & | |
251 | 0x000fffffffffffff); | |
252 | mb_array[i].logicalStart = | |
253 | addr_to_chunk(mb_array[i].logicalStart); | |
254 | mb_array[i].logicalEnd = addr_to_chunk(mb_array[i].logicalEnd); | |
255 | } | |
256 | } | |
257 | ||
258 | return numSegmentBlocks; | |
259 | } | |
260 | ||
261 | static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array, | |
262 | unsigned long max_entries) | |
263 | { | |
264 | unsigned long i; | |
265 | unsigned long mem_blocks = 0; | |
266 | ||
267 | if (cpu_has_feature(CPU_FTR_SLB)) | |
268 | mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array, | |
269 | max_entries); | |
270 | else | |
271 | mem_blocks = iSeries_process_Condor_mainstore_vpd(mb_array, | |
272 | max_entries); | |
273 | ||
274 | printk("Mainstore_VPD: numMemoryBlocks = %ld \n", mem_blocks); | |
275 | for (i = 0; i < mem_blocks; ++i) { | |
276 | printk("Mainstore_VPD: block %3ld logical chunks %016lx - %016lx\n" | |
277 | " abs chunks %016lx - %016lx\n", | |
278 | i, mb_array[i].logicalStart, mb_array[i].logicalEnd, | |
279 | mb_array[i].absStart, mb_array[i].absEnd); | |
280 | } | |
281 | return mem_blocks; | |
282 | } | |
283 | ||
284 | static void __init iSeries_get_cmdline(void) | |
285 | { | |
286 | char *p, *q; | |
287 | ||
288 | /* copy the command line parameter from the primary VSP */ | |
289 | HvCallEvent_dmaToSp(cmd_line, 2 * 64* 1024, 256, | |
290 | HvLpDma_Direction_RemoteToLocal); | |
291 | ||
292 | p = cmd_line; | |
293 | q = cmd_line + 255; | |
294 | while(p < q) { | |
295 | if (!*p || *p == '\n') | |
296 | break; | |
297 | ++p; | |
298 | } | |
299 | *p = 0; | |
300 | } | |
301 | ||
302 | static void __init iSeries_init_early(void) | |
303 | { | |
1da177e4 LT |
304 | DBG(" -> iSeries_init_early()\n"); |
305 | ||
aed31351 SR |
306 | ppc64_firmware_features = FW_FEATURE_ISERIES; |
307 | ||
ba293fff ME |
308 | ppc64_interrupt_controller = IC_ISERIES; |
309 | ||
1da177e4 LT |
310 | #if defined(CONFIG_BLK_DEV_INITRD) |
311 | /* | |
312 | * If the init RAM disk has been configured and there is | |
313 | * a non-zero starting address for it, set it up | |
314 | */ | |
315 | if (naca.xRamDisk) { | |
316 | initrd_start = (unsigned long)__va(naca.xRamDisk); | |
3c726f8d | 317 | initrd_end = initrd_start + naca.xRamDiskSize * HW_PAGE_SIZE; |
1da177e4 LT |
318 | initrd_below_start_ok = 1; // ramdisk in kernel space |
319 | ROOT_DEV = Root_RAM0; | |
3c726f8d BH |
320 | if (((rd_size * 1024) / HW_PAGE_SIZE) < naca.xRamDiskSize) |
321 | rd_size = (naca.xRamDiskSize * HW_PAGE_SIZE) / 1024; | |
1da177e4 LT |
322 | } else |
323 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
324 | { | |
325 | /* ROOT_DEV = MKDEV(VIODASD_MAJOR, 1); */ | |
326 | } | |
327 | ||
328 | iSeries_recal_tb = get_tb(); | |
329 | iSeries_recal_titan = HvCallXm_loadTod(); | |
330 | ||
1da177e4 LT |
331 | /* |
332 | * Initialize the hash table management pointers | |
333 | */ | |
334 | hpte_init_iSeries(); | |
335 | ||
336 | /* | |
337 | * Initialize the DMA/TCE management | |
338 | */ | |
339 | iommu_init_early_iSeries(); | |
340 | ||
1da177e4 LT |
341 | /* Initialize machine-dependency vectors */ |
342 | #ifdef CONFIG_SMP | |
343 | smp_init_iSeries(); | |
344 | #endif | |
345 | if (itLpNaca.xPirEnvironMode == 0) | |
346 | piranha_simulator = 1; | |
347 | ||
348 | /* Associate Lp Event Queue 0 with processor 0 */ | |
349 | HvCallEvent_setLpEventQueueInterruptProc(0, 0); | |
350 | ||
351 | mf_init(); | |
352 | mf_initialized = 1; | |
353 | mb(); | |
354 | ||
355 | /* If we were passed an initrd, set the ROOT_DEV properly if the values | |
356 | * look sensible. If not, clear initrd reference. | |
357 | */ | |
358 | #ifdef CONFIG_BLK_DEV_INITRD | |
359 | if (initrd_start >= KERNELBASE && initrd_end >= KERNELBASE && | |
360 | initrd_end > initrd_start) | |
361 | ROOT_DEV = Root_RAM0; | |
362 | else | |
363 | initrd_start = initrd_end = 0; | |
364 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
365 | ||
366 | DBG(" <- iSeries_init_early()\n"); | |
367 | } | |
368 | ||
56e97b71 | 369 | struct mschunks_map mschunks_map = { |
34c8f696 ME |
370 | /* XXX We don't use these, but Piranha might need them. */ |
371 | .chunk_size = MSCHUNKS_CHUNK_SIZE, | |
372 | .chunk_shift = MSCHUNKS_CHUNK_SHIFT, | |
373 | .chunk_mask = MSCHUNKS_OFFSET_MASK, | |
374 | }; | |
56e97b71 | 375 | EXPORT_SYMBOL(mschunks_map); |
34c8f696 | 376 | |
56e97b71 | 377 | void mschunks_alloc(unsigned long num_chunks) |
34c8f696 ME |
378 | { |
379 | klimit = _ALIGN(klimit, sizeof(u32)); | |
56e97b71 | 380 | mschunks_map.mapping = (u32 *)klimit; |
34c8f696 | 381 | klimit += num_chunks * sizeof(u32); |
56e97b71 | 382 | mschunks_map.num_chunks = num_chunks; |
34c8f696 ME |
383 | } |
384 | ||
1da177e4 LT |
385 | /* |
386 | * The iSeries may have very large memories ( > 128 GB ) and a partition | |
387 | * may get memory in "chunks" that may be anywhere in the 2**52 real | |
388 | * address space. The chunks are 256K in size. To map this to the | |
389 | * memory model Linux expects, the AS/400 specific code builds a | |
390 | * translation table to translate what Linux thinks are "physical" | |
391 | * addresses to the actual real addresses. This allows us to make | |
392 | * it appear to Linux that we have contiguous memory starting at | |
393 | * physical address zero while in fact this could be far from the truth. | |
394 | * To avoid confusion, I'll let the words physical and/or real address | |
395 | * apply to the Linux addresses while I'll use "absolute address" to | |
396 | * refer to the actual hardware real address. | |
397 | * | |
398 | * build_iSeries_Memory_Map gets information from the Hypervisor and | |
399 | * looks at the Main Store VPD to determine the absolute addresses | |
400 | * of the memory that has been assigned to our partition and builds | |
401 | * a table used to translate Linux's physical addresses to these | |
402 | * absolute addresses. Absolute addresses are needed when | |
403 | * communicating with the hypervisor (e.g. to build HPT entries) | |
799d6046 PM |
404 | * |
405 | * Returns the physical memory size | |
1da177e4 LT |
406 | */ |
407 | ||
799d6046 | 408 | static unsigned long __init build_iSeries_Memory_Map(void) |
1da177e4 LT |
409 | { |
410 | u32 loadAreaFirstChunk, loadAreaLastChunk, loadAreaSize; | |
411 | u32 nextPhysChunk; | |
412 | u32 hptFirstChunk, hptLastChunk, hptSizeChunks, hptSizePages; | |
1da177e4 LT |
413 | u32 totalChunks,moreChunks; |
414 | u32 currChunk, thisChunk, absChunk; | |
415 | u32 currDword; | |
416 | u32 chunkBit; | |
417 | u64 map; | |
418 | struct MemoryBlock mb[32]; | |
419 | unsigned long numMemoryBlocks, curBlock; | |
420 | ||
421 | /* Chunk size on iSeries is 256K bytes */ | |
422 | totalChunks = (u32)HvLpConfig_getMsChunks(); | |
56e97b71 | 423 | mschunks_alloc(totalChunks); |
1da177e4 LT |
424 | |
425 | /* | |
426 | * Get absolute address of our load area | |
427 | * and map it to physical address 0 | |
428 | * This guarantees that the loadarea ends up at physical 0 | |
429 | * otherwise, it might not be returned by PLIC as the first | |
430 | * chunks | |
431 | */ | |
432 | ||
433 | loadAreaFirstChunk = (u32)addr_to_chunk(itLpNaca.xLoadAreaAddr); | |
434 | loadAreaSize = itLpNaca.xLoadAreaChunks; | |
435 | ||
436 | /* | |
437 | * Only add the pages already mapped here. | |
438 | * Otherwise we might add the hpt pages | |
439 | * The rest of the pages of the load area | |
440 | * aren't in the HPT yet and can still | |
441 | * be assigned an arbitrary physical address | |
442 | */ | |
443 | if ((loadAreaSize * 64) > HvPagesToMap) | |
444 | loadAreaSize = HvPagesToMap / 64; | |
445 | ||
446 | loadAreaLastChunk = loadAreaFirstChunk + loadAreaSize - 1; | |
447 | ||
448 | /* | |
449 | * TODO Do we need to do something if the HPT is in the 64MB load area? | |
450 | * This would be required if the itLpNaca.xLoadAreaChunks includes | |
451 | * the HPT size | |
452 | */ | |
453 | ||
454 | printk("Mapping load area - physical addr = 0000000000000000\n" | |
455 | " absolute addr = %016lx\n", | |
456 | chunk_to_addr(loadAreaFirstChunk)); | |
457 | printk("Load area size %dK\n", loadAreaSize * 256); | |
458 | ||
459 | for (nextPhysChunk = 0; nextPhysChunk < loadAreaSize; ++nextPhysChunk) | |
56e97b71 | 460 | mschunks_map.mapping[nextPhysChunk] = |
1da177e4 LT |
461 | loadAreaFirstChunk + nextPhysChunk; |
462 | ||
463 | /* | |
464 | * Get absolute address of our HPT and remember it so | |
465 | * we won't map it to any physical address | |
466 | */ | |
467 | hptFirstChunk = (u32)addr_to_chunk(HvCallHpt_getHptAddress()); | |
468 | hptSizePages = (u32)HvCallHpt_getHptPages(); | |
3c726f8d BH |
469 | hptSizeChunks = hptSizePages >> |
470 | (MSCHUNKS_CHUNK_SHIFT - HW_PAGE_SHIFT); | |
1da177e4 LT |
471 | hptLastChunk = hptFirstChunk + hptSizeChunks - 1; |
472 | ||
473 | printk("HPT absolute addr = %016lx, size = %dK\n", | |
474 | chunk_to_addr(hptFirstChunk), hptSizeChunks * 256); | |
475 | ||
1da177e4 LT |
476 | /* |
477 | * Determine if absolute memory has any | |
478 | * holes so that we can interpret the | |
479 | * access map we get back from the hypervisor | |
480 | * correctly. | |
481 | */ | |
482 | numMemoryBlocks = iSeries_process_mainstore_vpd(mb, 32); | |
483 | ||
484 | /* | |
485 | * Process the main store access map from the hypervisor | |
486 | * to build up our physical -> absolute translation table | |
487 | */ | |
488 | curBlock = 0; | |
489 | currChunk = 0; | |
490 | currDword = 0; | |
491 | moreChunks = totalChunks; | |
492 | ||
493 | while (moreChunks) { | |
494 | map = HvCallSm_get64BitsOfAccessMap(itLpNaca.xLpIndex, | |
495 | currDword); | |
496 | thisChunk = currChunk; | |
497 | while (map) { | |
498 | chunkBit = map >> 63; | |
499 | map <<= 1; | |
500 | if (chunkBit) { | |
501 | --moreChunks; | |
502 | while (thisChunk >= mb[curBlock].logicalEnd) { | |
503 | ++curBlock; | |
504 | if (curBlock >= numMemoryBlocks) | |
505 | panic("out of memory blocks"); | |
506 | } | |
507 | if (thisChunk < mb[curBlock].logicalStart) | |
508 | panic("memory block error"); | |
509 | ||
510 | absChunk = mb[curBlock].absStart + | |
511 | (thisChunk - mb[curBlock].logicalStart); | |
512 | if (((absChunk < hptFirstChunk) || | |
513 | (absChunk > hptLastChunk)) && | |
514 | ((absChunk < loadAreaFirstChunk) || | |
515 | (absChunk > loadAreaLastChunk))) { | |
56e97b71 ME |
516 | mschunks_map.mapping[nextPhysChunk] = |
517 | absChunk; | |
1da177e4 LT |
518 | ++nextPhysChunk; |
519 | } | |
520 | } | |
521 | ++thisChunk; | |
522 | } | |
523 | ++currDword; | |
524 | currChunk += 64; | |
525 | } | |
526 | ||
527 | /* | |
528 | * main store size (in chunks) is | |
529 | * totalChunks - hptSizeChunks | |
530 | * which should be equal to | |
531 | * nextPhysChunk | |
532 | */ | |
799d6046 | 533 | return chunk_to_addr(nextPhysChunk); |
1da177e4 LT |
534 | } |
535 | ||
1da177e4 LT |
536 | /* |
537 | * Document me. | |
538 | */ | |
539 | static void __init iSeries_setup_arch(void) | |
540 | { | |
9f497581 ME |
541 | if (get_paca()->lppaca.shared_proc) { |
542 | ppc_md.idle_loop = iseries_shared_idle; | |
543 | printk(KERN_INFO "Using shared processor idle loop\n"); | |
544 | } else { | |
545 | ppc_md.idle_loop = iseries_dedicated_idle; | |
546 | printk(KERN_INFO "Using dedicated idle loop\n"); | |
547 | } | |
548 | ||
1da177e4 | 549 | /* Setup the Lp Event Queue */ |
512d31d6 | 550 | setup_hvlpevent_queue(); |
1da177e4 | 551 | |
1da177e4 LT |
552 | printk("Max logical processors = %d\n", |
553 | itVpdAreas.xSlicMaxLogicalProcs); | |
554 | printk("Max physical processors = %d\n", | |
555 | itVpdAreas.xSlicMaxPhysicalProcs); | |
1da177e4 LT |
556 | } |
557 | ||
d8699e65 | 558 | static void iSeries_show_cpuinfo(struct seq_file *m) |
1da177e4 LT |
559 | { |
560 | seq_printf(m, "machine\t\t: 64-bit iSeries Logical Partition\n"); | |
561 | } | |
562 | ||
1da177e4 LT |
563 | /* |
564 | * Document me. | |
565 | */ | |
566 | static void iSeries_restart(char *cmd) | |
567 | { | |
568 | mf_reboot(); | |
569 | } | |
570 | ||
571 | /* | |
572 | * Document me. | |
573 | */ | |
574 | static void iSeries_power_off(void) | |
575 | { | |
576 | mf_power_off(); | |
577 | } | |
578 | ||
579 | /* | |
580 | * Document me. | |
581 | */ | |
582 | static void iSeries_halt(void) | |
583 | { | |
584 | mf_power_off(); | |
585 | } | |
586 | ||
1da177e4 LT |
587 | static void __init iSeries_progress(char * st, unsigned short code) |
588 | { | |
589 | printk("Progress: [%04x] - %s\n", (unsigned)code, st); | |
590 | if (!piranha_simulator && mf_initialized) { | |
591 | if (code != 0xffff) | |
592 | mf_display_progress(code); | |
593 | else | |
594 | mf_clear_src(); | |
595 | } | |
596 | } | |
597 | ||
598 | static void __init iSeries_fixup_klimit(void) | |
599 | { | |
600 | /* | |
601 | * Change klimit to take into account any ram disk | |
602 | * that may be included | |
603 | */ | |
604 | if (naca.xRamDisk) | |
605 | klimit = KERNELBASE + (u64)naca.xRamDisk + | |
3c726f8d | 606 | (naca.xRamDiskSize * HW_PAGE_SIZE); |
1da177e4 LT |
607 | else { |
608 | /* | |
609 | * No ram disk was included - check and see if there | |
610 | * was an embedded system map. Change klimit to take | |
611 | * into account any embedded system map | |
612 | */ | |
613 | if (embedded_sysmap_end) | |
614 | klimit = KERNELBASE + ((embedded_sysmap_end + 4095) & | |
615 | 0xfffffffffffff000); | |
616 | } | |
617 | } | |
618 | ||
619 | static int __init iSeries_src_init(void) | |
620 | { | |
621 | /* clear the progress line */ | |
622 | ppc_md.progress(" ", 0xffff); | |
623 | return 0; | |
624 | } | |
625 | ||
626 | late_initcall(iSeries_src_init); | |
627 | ||
d200903e ME |
628 | static inline void process_iSeries_events(void) |
629 | { | |
630 | asm volatile ("li 0,0x5555; sc" : : : "r0", "r3"); | |
631 | } | |
632 | ||
633 | static void yield_shared_processor(void) | |
634 | { | |
635 | unsigned long tb; | |
d200903e ME |
636 | |
637 | HvCall_setEnabledInterrupts(HvCall_MaskIPI | | |
638 | HvCall_MaskLpEvent | | |
639 | HvCall_MaskLpProd | | |
640 | HvCall_MaskTimeout); | |
641 | ||
642 | tb = get_tb(); | |
643 | /* Compute future tb value when yield should expire */ | |
644 | HvCall_yieldProcessor(HvCall_YieldTimed, tb+tb_ticks_per_jiffy); | |
645 | ||
d200903e ME |
646 | /* |
647 | * The decrementer stops during the yield. Force a fake decrementer | |
648 | * here and let the timer_interrupt code sort out the actual time. | |
649 | */ | |
650 | get_paca()->lppaca.int_dword.fields.decr_int = 1; | |
651 | process_iSeries_events(); | |
652 | } | |
653 | ||
143a1dec | 654 | static void iseries_shared_idle(void) |
d200903e | 655 | { |
3c57bb9f AB |
656 | while (1) { |
657 | while (!need_resched() && !hvlpevent_is_pending()) { | |
658 | local_irq_disable(); | |
659 | ppc64_runlatch_off(); | |
660 | ||
661 | /* Recheck with irqs off */ | |
662 | if (!need_resched() && !hvlpevent_is_pending()) | |
663 | yield_shared_processor(); | |
d200903e | 664 | |
3c57bb9f AB |
665 | HMT_medium(); |
666 | local_irq_enable(); | |
667 | } | |
668 | ||
669 | ppc64_runlatch_on(); | |
d200903e | 670 | |
3c57bb9f AB |
671 | if (hvlpevent_is_pending()) |
672 | process_iSeries_events(); | |
673 | ||
5bfb5d69 | 674 | preempt_enable_no_resched(); |
3c57bb9f | 675 | schedule(); |
5bfb5d69 | 676 | preempt_disable(); |
3c57bb9f | 677 | } |
3c57bb9f AB |
678 | } |
679 | ||
143a1dec | 680 | static void iseries_dedicated_idle(void) |
3c57bb9f | 681 | { |
64c7c8f8 | 682 | set_thread_flag(TIF_POLLING_NRFLAG); |
d200903e ME |
683 | |
684 | while (1) { | |
64c7c8f8 | 685 | if (!need_resched()) { |
3c57bb9f AB |
686 | while (!need_resched()) { |
687 | ppc64_runlatch_off(); | |
688 | HMT_low(); | |
689 | ||
690 | if (hvlpevent_is_pending()) { | |
d200903e | 691 | HMT_medium(); |
3c57bb9f AB |
692 | ppc64_runlatch_on(); |
693 | process_iSeries_events(); | |
d200903e | 694 | } |
d200903e | 695 | } |
3c57bb9f AB |
696 | |
697 | HMT_medium(); | |
d200903e ME |
698 | } |
699 | ||
700 | ppc64_runlatch_on(); | |
5bfb5d69 | 701 | preempt_enable_no_resched(); |
d200903e | 702 | schedule(); |
5bfb5d69 | 703 | preempt_disable(); |
d200903e | 704 | } |
d200903e ME |
705 | } |
706 | ||
145d01e4 SR |
707 | #ifndef CONFIG_PCI |
708 | void __init iSeries_init_IRQ(void) { } | |
709 | #endif | |
710 | ||
4762713a ME |
711 | static int __init iseries_probe(int platform) |
712 | { | |
713 | return PLATFORM_ISERIES_LPAR == platform; | |
714 | } | |
715 | ||
9f497581 ME |
716 | struct machdep_calls __initdata iseries_md = { |
717 | .setup_arch = iSeries_setup_arch, | |
d8699e65 | 718 | .show_cpuinfo = iSeries_show_cpuinfo, |
9f497581 ME |
719 | .init_IRQ = iSeries_init_IRQ, |
720 | .get_irq = iSeries_get_irq, | |
721 | .init_early = iSeries_init_early, | |
722 | .pcibios_fixup = iSeries_pci_final_fixup, | |
723 | .restart = iSeries_restart, | |
724 | .power_off = iSeries_power_off, | |
725 | .halt = iSeries_halt, | |
726 | .get_boot_time = iSeries_get_boot_time, | |
727 | .set_rtc_time = iSeries_set_rtc_time, | |
728 | .get_rtc_time = iSeries_get_rtc_time, | |
95b29380 | 729 | .calibrate_decr = generic_calibrate_decr, |
9f497581 | 730 | .progress = iSeries_progress, |
4762713a | 731 | .probe = iseries_probe, |
9f497581 ME |
732 | /* XXX Implement enable_pmcs for iSeries */ |
733 | }; | |
734 | ||
c0a59491 ME |
735 | struct blob { |
736 | unsigned char data[PAGE_SIZE]; | |
737 | unsigned long next; | |
738 | }; | |
739 | ||
740 | struct iseries_flat_dt { | |
741 | struct boot_param_header header; | |
742 | u64 reserve_map[2]; | |
743 | struct blob dt; | |
744 | struct blob strings; | |
745 | }; | |
746 | ||
747 | struct iseries_flat_dt iseries_dt; | |
748 | ||
749 | void dt_init(struct iseries_flat_dt *dt) | |
750 | { | |
751 | dt->header.off_mem_rsvmap = | |
752 | offsetof(struct iseries_flat_dt, reserve_map); | |
753 | dt->header.off_dt_struct = offsetof(struct iseries_flat_dt, dt); | |
754 | dt->header.off_dt_strings = offsetof(struct iseries_flat_dt, strings); | |
755 | dt->header.totalsize = sizeof(struct iseries_flat_dt); | |
756 | dt->header.dt_strings_size = sizeof(struct blob); | |
757 | ||
758 | /* There is no notion of hardware cpu id on iSeries */ | |
759 | dt->header.boot_cpuid_phys = smp_processor_id(); | |
760 | ||
761 | dt->dt.next = (unsigned long)&dt->dt.data; | |
762 | dt->strings.next = (unsigned long)&dt->strings.data; | |
763 | ||
764 | dt->header.magic = OF_DT_HEADER; | |
765 | dt->header.version = 0x10; | |
766 | dt->header.last_comp_version = 0x10; | |
767 | ||
768 | dt->reserve_map[0] = 0; | |
769 | dt->reserve_map[1] = 0; | |
770 | } | |
771 | ||
772 | void dt_check_blob(struct blob *b) | |
773 | { | |
774 | if (b->next >= (unsigned long)&b->next) { | |
775 | DBG("Ran out of space in flat device tree blob!\n"); | |
776 | BUG(); | |
777 | } | |
778 | } | |
779 | ||
780 | void dt_push_u32(struct iseries_flat_dt *dt, u32 value) | |
781 | { | |
782 | *((u32*)dt->dt.next) = value; | |
783 | dt->dt.next += sizeof(u32); | |
784 | ||
785 | dt_check_blob(&dt->dt); | |
786 | } | |
787 | ||
788 | void dt_push_u64(struct iseries_flat_dt *dt, u64 value) | |
789 | { | |
790 | *((u64*)dt->dt.next) = value; | |
791 | dt->dt.next += sizeof(u64); | |
792 | ||
793 | dt_check_blob(&dt->dt); | |
794 | } | |
795 | ||
796 | unsigned long dt_push_bytes(struct blob *blob, char *data, int len) | |
797 | { | |
798 | unsigned long start = blob->next - (unsigned long)blob->data; | |
799 | ||
800 | memcpy((char *)blob->next, data, len); | |
801 | blob->next = _ALIGN(blob->next + len, 4); | |
802 | ||
803 | dt_check_blob(blob); | |
804 | ||
805 | return start; | |
806 | } | |
807 | ||
808 | void dt_start_node(struct iseries_flat_dt *dt, char *name) | |
809 | { | |
810 | dt_push_u32(dt, OF_DT_BEGIN_NODE); | |
811 | dt_push_bytes(&dt->dt, name, strlen(name) + 1); | |
812 | } | |
813 | ||
814 | #define dt_end_node(dt) dt_push_u32(dt, OF_DT_END_NODE) | |
815 | ||
816 | void dt_prop(struct iseries_flat_dt *dt, char *name, char *data, int len) | |
817 | { | |
818 | unsigned long offset; | |
819 | ||
820 | dt_push_u32(dt, OF_DT_PROP); | |
821 | ||
822 | /* Length of the data */ | |
823 | dt_push_u32(dt, len); | |
824 | ||
825 | /* Put the property name in the string blob. */ | |
826 | offset = dt_push_bytes(&dt->strings, name, strlen(name) + 1); | |
827 | ||
828 | /* The offset of the properties name in the string blob. */ | |
829 | dt_push_u32(dt, (u32)offset); | |
830 | ||
831 | /* The actual data. */ | |
832 | dt_push_bytes(&dt->dt, data, len); | |
833 | } | |
834 | ||
835 | void dt_prop_str(struct iseries_flat_dt *dt, char *name, char *data) | |
836 | { | |
837 | dt_prop(dt, name, data, strlen(data) + 1); /* + 1 for NULL */ | |
838 | } | |
839 | ||
840 | void dt_prop_u32(struct iseries_flat_dt *dt, char *name, u32 data) | |
841 | { | |
842 | dt_prop(dt, name, (char *)&data, sizeof(u32)); | |
843 | } | |
844 | ||
845 | void dt_prop_u64(struct iseries_flat_dt *dt, char *name, u64 data) | |
846 | { | |
847 | dt_prop(dt, name, (char *)&data, sizeof(u64)); | |
848 | } | |
849 | ||
850 | void dt_prop_u64_list(struct iseries_flat_dt *dt, char *name, u64 *data, int n) | |
851 | { | |
852 | dt_prop(dt, name, (char *)data, sizeof(u64) * n); | |
853 | } | |
854 | ||
7eb5476f ME |
855 | void dt_prop_u32_list(struct iseries_flat_dt *dt, char *name, u32 *data, int n) |
856 | { | |
857 | dt_prop(dt, name, (char *)data, sizeof(u32) * n); | |
858 | } | |
859 | ||
c0a59491 ME |
860 | void dt_prop_empty(struct iseries_flat_dt *dt, char *name) |
861 | { | |
862 | dt_prop(dt, name, NULL, 0); | |
863 | } | |
864 | ||
95b29380 ME |
865 | void dt_cpus(struct iseries_flat_dt *dt) |
866 | { | |
867 | unsigned char buf[32]; | |
868 | unsigned char *p; | |
869 | unsigned int i, index; | |
870 | struct IoHriProcessorVpd *d; | |
7eb5476f | 871 | u32 pft_size[2]; |
95b29380 ME |
872 | |
873 | /* yuck */ | |
874 | snprintf(buf, 32, "PowerPC,%s", cur_cpu_spec->cpu_name); | |
875 | p = strchr(buf, ' '); | |
876 | if (!p) p = buf + strlen(buf); | |
877 | ||
878 | dt_start_node(dt, "cpus"); | |
879 | dt_prop_u32(dt, "#address-cells", 1); | |
880 | dt_prop_u32(dt, "#size-cells", 0); | |
881 | ||
7eb5476f ME |
882 | pft_size[0] = 0; /* NUMA CEC cookie, 0 for non NUMA */ |
883 | pft_size[1] = __ilog2(HvCallHpt_getHptPages() * HW_PAGE_SIZE); | |
884 | ||
95b29380 ME |
885 | for (i = 0; i < NR_CPUS; i++) { |
886 | if (paca[i].lppaca.dyn_proc_status >= 2) | |
887 | continue; | |
888 | ||
889 | snprintf(p, 32 - (p - buf), "@%d", i); | |
890 | dt_start_node(dt, buf); | |
891 | ||
892 | dt_prop_str(dt, "device_type", "cpu"); | |
893 | ||
894 | index = paca[i].lppaca.dyn_hv_phys_proc_index; | |
895 | d = &xIoHriProcessorVpd[index]; | |
896 | ||
897 | dt_prop_u32(dt, "i-cache-size", d->xInstCacheSize * 1024); | |
898 | dt_prop_u32(dt, "i-cache-line-size", d->xInstCacheOperandSize); | |
899 | ||
900 | dt_prop_u32(dt, "d-cache-size", d->xDataL1CacheSizeKB * 1024); | |
901 | dt_prop_u32(dt, "d-cache-line-size", d->xDataCacheOperandSize); | |
902 | ||
903 | /* magic conversions to Hz copied from old code */ | |
904 | dt_prop_u32(dt, "clock-frequency", | |
905 | ((1UL << 34) * 1000000) / d->xProcFreq); | |
906 | dt_prop_u32(dt, "timebase-frequency", | |
907 | ((1UL << 32) * 1000000) / d->xTimeBaseFreq); | |
908 | ||
909 | dt_prop_u32(dt, "reg", i); | |
910 | ||
7eb5476f ME |
911 | dt_prop_u32_list(dt, "ibm,pft-size", pft_size, 2); |
912 | ||
95b29380 ME |
913 | dt_end_node(dt); |
914 | } | |
915 | ||
916 | dt_end_node(dt); | |
917 | } | |
918 | ||
799d6046 | 919 | void build_flat_dt(struct iseries_flat_dt *dt, unsigned long phys_mem_size) |
c0a59491 | 920 | { |
3ab42407 ME |
921 | u64 tmp[2]; |
922 | ||
c0a59491 ME |
923 | dt_init(dt); |
924 | ||
925 | dt_start_node(dt, ""); | |
3ab42407 ME |
926 | |
927 | dt_prop_u32(dt, "#address-cells", 2); | |
928 | dt_prop_u32(dt, "#size-cells", 2); | |
929 | ||
930 | /* /memory */ | |
931 | dt_start_node(dt, "memory@0"); | |
932 | dt_prop_str(dt, "name", "memory"); | |
933 | dt_prop_str(dt, "device_type", "memory"); | |
934 | tmp[0] = 0; | |
799d6046 | 935 | tmp[1] = phys_mem_size; |
3ab42407 ME |
936 | dt_prop_u64_list(dt, "reg", tmp, 2); |
937 | dt_end_node(dt); | |
938 | ||
47db3603 ME |
939 | /* /chosen */ |
940 | dt_start_node(dt, "chosen"); | |
941 | dt_prop_u32(dt, "linux,platform", PLATFORM_ISERIES_LPAR); | |
bec7c458 SR |
942 | if (cmd_mem_limit) |
943 | dt_prop_u64(dt, "linux,memory-limit", cmd_mem_limit); | |
47db3603 ME |
944 | dt_end_node(dt); |
945 | ||
95b29380 ME |
946 | dt_cpus(dt); |
947 | ||
c0a59491 ME |
948 | dt_end_node(dt); |
949 | ||
950 | dt_push_u32(dt, OF_DT_END); | |
951 | } | |
952 | ||
4762713a | 953 | void * __init iSeries_early_setup(void) |
1da177e4 | 954 | { |
799d6046 PM |
955 | unsigned long phys_mem_size; |
956 | ||
1da177e4 | 957 | iSeries_fixup_klimit(); |
c0a59491 | 958 | |
4762713a ME |
959 | /* |
960 | * Initialize the table which translate Linux physical addresses to | |
961 | * AS/400 absolute addresses | |
962 | */ | |
799d6046 | 963 | phys_mem_size = build_iSeries_Memory_Map(); |
4762713a | 964 | |
bec7c458 SR |
965 | iSeries_get_cmdline(); |
966 | ||
967 | /* Save unparsed command line copy for /proc/cmdline */ | |
968 | strlcpy(saved_command_line, cmd_line, COMMAND_LINE_SIZE); | |
969 | ||
970 | /* Parse early parameters, in particular mem=x */ | |
971 | parse_early_param(); | |
972 | ||
799d6046 | 973 | build_flat_dt(&iseries_dt, phys_mem_size); |
4762713a ME |
974 | |
975 | return (void *) __pa(&iseries_dt); | |
1da177e4 | 976 | } |
bec7c458 SR |
977 | |
978 | /* | |
979 | * On iSeries we just parse the mem=X option from the command line. | |
980 | * On pSeries it's a bit more complicated, see prom_init_mem() | |
981 | */ | |
982 | static int __init early_parsemem(char *p) | |
983 | { | |
984 | if (p) | |
985 | cmd_mem_limit = ALIGN(memparse(p, &p), PAGE_SIZE); | |
986 | return 0; | |
987 | } | |
988 | early_param("mem", early_parsemem); | |
bf6a7112 ME |
989 | |
990 | static void hvputc(char c) | |
991 | { | |
992 | if (c == '\n') | |
993 | hvputc('\r'); | |
994 | ||
995 | HvCall_writeLogBuffer(&c, 1); | |
996 | } | |
997 | ||
998 | void __init udbg_init_iseries(void) | |
999 | { | |
1000 | udbg_putc = hvputc; | |
1001 | } |