[deliverable/linux.git] / arch / powerpc / platforms / maple / pci.c

/*
 * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
 *		      IBM Corp.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#undef DEBUG

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/irq.h>

#include <asm/sections.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/machdep.h>
#include <asm/iommu.h>
#include <asm/ppc-pci.h>

#include "maple.h"

#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif

static struct pci_controller *u3_agp, *u3_ht, *u4_pcie;

static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
{
	for (; node != 0;node = node->sibling) {
		const int *bus_range;
		const unsigned int *class_code;
		int len;

		/* For PCI<->PCI bridges or CardBus bridges, we go down */
		class_code = of_get_property(node, "class-code", NULL);
		if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
			(*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
			continue;
		bus_range = of_get_property(node, "bus-range", &len);
		if (bus_range != NULL && len > 2 * sizeof(int)) {
			if (bus_range[1] > higher)
				higher = bus_range[1];
		}
		higher = fixup_one_level_bus_range(node->child, higher);
	}
	return higher;
}

/* This routine fixes the "bus-range" property of all bridges in the
 * system since they tend to have their "last" member wrong on macs
 *
 * Note that the bus numbers manipulated here are OF bus numbers, they
 * are not Linux bus numbers.
 */
static void __init fixup_bus_range(struct device_node *bridge)
{
	int *bus_range;
	struct property *prop;
	int len;

	/* Lookup the "bus-range" property for the hose */
	prop = of_find_property(bridge, "bus-range", &len);
	if (prop == NULL  || prop->value == NULL || len < 2 * sizeof(int)) {
		printk(KERN_WARNING "Can't get bus-range for %s\n",
			       bridge->full_name);
		return;
	}
	bus_range = prop->value;
	bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
}


static unsigned long u3_agp_cfa0(u8 devfn, u8 off)
{
	return (1 << (unsigned long)PCI_SLOT(devfn)) |
		((unsigned long)PCI_FUNC(devfn) << 8) |
		((unsigned long)off & 0xFCUL);
}

static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off)
{
	return ((unsigned long)bus << 16) |
		((unsigned long)devfn << 8) |
		((unsigned long)off & 0xFCUL) |
		1UL;
}

static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose,
				       u8 bus, u8 dev_fn, u8 offset)
{
	unsigned int caddr;

	if (bus == hose->first_busno) {
		if (dev_fn < (11 << 3))
			return NULL;
		caddr = u3_agp_cfa0(dev_fn, offset);
	} else
		caddr = u3_agp_cfa1(bus, dev_fn, offset);

	/* Uninorth will return garbage if we don't read back the value ! */
	do {
		out_le32(hose->cfg_addr, caddr);
	} while (in_le32(hose->cfg_addr) != caddr);

	offset &= 0x07;
	return hose->cfg_data + offset;
}

static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
			      int offset, int len, u32 *val)
{
	struct pci_controller *hose;
	volatile void __iomem *addr;

	hose = pci_bus_to_host(bus);
	if (hose == NULL)
		return PCIBIOS_DEVICE_NOT_FOUND;

	addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
	if (!addr)
		return PCIBIOS_DEVICE_NOT_FOUND;
	/*
	 * Note: the caller has already checked that offset is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	switch (len) {
	case 1:
		*val = in_8(addr);
		break;
	case 2:
		*val = in_le16(addr);
		break;
	default:
		*val = in_le32(addr);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
			       int offset, int len, u32 val)
{
	struct pci_controller *hose;
	volatile void __iomem *addr;

	hose = pci_bus_to_host(bus);
	if (hose == NULL)
		return PCIBIOS_DEVICE_NOT_FOUND;

	addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
	if (!addr)
		return PCIBIOS_DEVICE_NOT_FOUND;
	/*
	 * Note: the caller has already checked that offset is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	switch (len) {
	case 1:
		out_8(addr, val);
		break;
	case 2:
		out_le16(addr, val);
		break;
	default:
		out_le32(addr, val);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops u3_agp_pci_ops =
{
	.read = u3_agp_read_config,
	.write = u3_agp_write_config,
};

static unsigned long u3_ht_cfa0(u8 devfn, u8 off)
{
	return (devfn << 8) | off;
}

static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off)
{
	return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL;
}

static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
				      u8 bus, u8 devfn, u8 offset)
{
	if (bus == hose->first_busno) {
		if (PCI_SLOT(devfn) == 0)
			return NULL;
		return hose->cfg_data + u3_ht_cfa0(devfn, offset);
	} else
		return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);
}

static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
			     int offset, int len, u32 *val)
{
	struct pci_controller *hose;
	volatile void __iomem *addr;

	hose = pci_bus_to_host(bus);
	if (hose == NULL)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (offset > 0xff)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
	if (!addr)
		return PCIBIOS_DEVICE_NOT_FOUND;

	/*
	 * Note: the caller has already checked that offset is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	switch (len) {
	case 1:
		*val = in_8(addr);
		break;
	case 2:
		*val = in_le16(addr);
		break;
	default:
		*val = in_le32(addr);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
			      int offset, int len, u32 val)
{
	struct pci_controller *hose;
	volatile void __iomem *addr;

	hose = pci_bus_to_host(bus);
	if (hose == NULL)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (offset > 0xff)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
	if (!addr)
		return PCIBIOS_DEVICE_NOT_FOUND;
	/*
	 * Note: the caller has already checked that offset is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	switch (len) {
	case 1:
		out_8(addr, val);
		break;
	case 2:
		out_le16(addr, val);
		break;
	default:
		out_le32(addr, val);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops u3_ht_pci_ops =
{
	.read = u3_ht_read_config,
	.write = u3_ht_write_config,
};

static unsigned int u4_pcie_cfa0(unsigned int devfn, unsigned int off)
{
	return (1 << PCI_SLOT(devfn))	|
	       (PCI_FUNC(devfn) << 8)	|
	       ((off >> 8) << 28) 	|
	       (off & 0xfcu);
}

static unsigned int u4_pcie_cfa1(unsigned int bus, unsigned int devfn,
				 unsigned int off)
{
        return (bus << 16)		|
	       (devfn << 8)		|
	       ((off >> 8) << 28)	|
	       (off & 0xfcu)		| 1u;
}

static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
                                        u8 bus, u8 dev_fn, int offset)
{
        unsigned int caddr;

        if (bus == hose->first_busno)
                caddr = u4_pcie_cfa0(dev_fn, offset);
        else
                caddr = u4_pcie_cfa1(bus, dev_fn, offset);

        /* Uninorth will return garbage if we don't read back the value ! */
        do {
                out_le32(hose->cfg_addr, caddr);
        } while (in_le32(hose->cfg_addr) != caddr);

        offset &= 0x03;
        return hose->cfg_data + offset;
}

static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
                               int offset, int len, u32 *val)
{
        struct pci_controller *hose;
        volatile void __iomem *addr;

        hose = pci_bus_to_host(bus);
        if (hose == NULL)
                return PCIBIOS_DEVICE_NOT_FOUND;
        if (offset >= 0x1000)
                return  PCIBIOS_BAD_REGISTER_NUMBER;
        addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
        if (!addr)
                return PCIBIOS_DEVICE_NOT_FOUND;
        /*
         * Note: the caller has already checked that offset is
         * suitably aligned and that len is 1, 2 or 4.
         */
        switch (len) {
        case 1:
                *val = in_8(addr);
                break;
        case 2:
                *val = in_le16(addr);
                break;
        default:
                *val = in_le32(addr);
                break;
        }
        return PCIBIOS_SUCCESSFUL;
}
static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
                                int offset, int len, u32 val)
{
        struct pci_controller *hose;
        volatile void __iomem *addr;

        hose = pci_bus_to_host(bus);
        if (hose == NULL)
                return PCIBIOS_DEVICE_NOT_FOUND;
        if (offset >= 0x1000)
                return  PCIBIOS_BAD_REGISTER_NUMBER;
        addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
        if (!addr)
                return PCIBIOS_DEVICE_NOT_FOUND;
        /*
         * Note: the caller has already checked that offset is
         * suitably aligned and that len is 1, 2 or 4.
         */
        switch (len) {
        case 1:
                out_8(addr, val);
                break;
        case 2:
                out_le16(addr, val);
                break;
        default:
                out_le32(addr, val);
                break;
        }
        return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops u4_pcie_pci_ops =
{
	.read = u4_pcie_read_config,
	.write = u4_pcie_write_config,
};

static void __init setup_u3_agp(struct pci_controller* hose)
{
	/* On G5, we move AGP up to high bus number so we don't need
	 * to reassign bus numbers for HT. If we ever have P2P bridges
	 * on AGP, we'll have to move pci_assign_all_buses to the
	 * pci_controller structure so we enable it for AGP and not for
	 * HT childs.
	 * We hard code the address because of the different size of
	 * the reg address cell, we shall fix that by killing struct
	 * reg_property and using some accessor functions instead
	 */
	hose->first_busno = 0xf0;
	hose->last_busno = 0xff;
	hose->ops = &u3_agp_pci_ops;
	hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
	hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);

	u3_agp = hose;
}

static void __init setup_u4_pcie(struct pci_controller* hose)
{
        /* We currently only implement the "non-atomic" config space, to
         * be optimised later.
         */
        hose->ops = &u4_pcie_pci_ops;
        hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
        hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);

        u4_pcie = hose;
}

static void __init setup_u3_ht(struct pci_controller* hose)
{
	hose->ops = &u3_ht_pci_ops;

	/* We hard code the address because of the different size of
	 * the reg address cell, we shall fix that by killing struct
	 * reg_property and using some accessor functions instead
	 */
	hose->cfg_data = ioremap(0xf2000000, 0x02000000);

	hose->first_busno = 0;
	hose->last_busno = 0xef;

	u3_ht = hose;
}

static int __init maple_add_bridge(struct device_node *dev)
{
	int len;
	struct pci_controller *hose;
	char* disp_name;
	const int *bus_range;
	int primary = 1;

	DBG("Adding PCI host bridge %s\n", dev->full_name);

	bus_range = of_get_property(dev, "bus-range", &len);
	if (bus_range == NULL || len < 2 * sizeof(int)) {
		printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
		dev->full_name);
	}

	hose = pcibios_alloc_controller(dev);
	if (hose == NULL)
		return -ENOMEM;
	hose->first_busno = bus_range ? bus_range[0] : 0;
	hose->last_busno = bus_range ? bus_range[1] : 0xff;

	disp_name = NULL;
	if (of_device_is_compatible(dev, "u3-agp")) {
		setup_u3_agp(hose);
		disp_name = "U3-AGP";
		primary = 0;
	} else if (of_device_is_compatible(dev, "u3-ht")) {
		setup_u3_ht(hose);
		disp_name = "U3-HT";
		primary = 1;
        } else if (of_device_is_compatible(dev, "u4-pcie")) {
                setup_u4_pcie(hose);
                disp_name = "U4-PCIE";
                primary = 0;
	}
	printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
		disp_name, hose->first_busno, hose->last_busno);

	/* Interpret the "ranges" property */
	/* This also maps the I/O region and sets isa_io/mem_base */
	pci_process_bridge_OF_ranges(hose, dev, primary);

	/* Fixup "bus-range" OF property */
	fixup_bus_range(dev);

	/* Check for legacy IOs */
	isa_bridge_find_early(hose);

	return 0;
}


void __devinit maple_pci_irq_fixup(struct pci_dev *dev)
{
	DBG(" -> maple_pci_irq_fixup\n");

	/* Fixup IRQ for PCIe host */
	if (u4_pcie != NULL && dev->bus->number == 0 &&
	    pci_bus_to_host(dev->bus) == u4_pcie) {
		printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n");
		dev->irq = irq_create_mapping(NULL, 1);
		if (dev->irq != NO_IRQ)
			set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
	}

	/* Hide AMD8111 IDE interrupt when in legacy mode so
	 * the driver calls pci_get_legacy_ide_irq()
	 */
	if (dev->vendor == PCI_VENDOR_ID_AMD &&
	    dev->device == PCI_DEVICE_ID_AMD_8111_IDE &&
	    (dev->class & 5) != 5) {
		dev->irq = NO_IRQ;
	}

	DBG(" <- maple_pci_irq_fixup\n");
}

void __init maple_pci_init(void)
{
	struct device_node *np, *root;
	struct device_node *ht = NULL;

	/* Probe root PCI hosts, that is on U3 the AGP host and the
	 * HyperTransport host. That one is actually "kept" around
	 * and actually added last as it's resource management relies
	 * on the AGP resources to have been setup first
	 */
	root = of_find_node_by_path("/");
	if (root == NULL) {
		printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n");
		return;
	}
	for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
		if (!np->type)
			continue;
		if (strcmp(np->type, "pci") && strcmp(np->type, "ht"))
			continue;
		if ((of_device_is_compatible(np, "u4-pcie") ||
		     of_device_is_compatible(np, "u3-agp")) &&
		    maple_add_bridge(np) == 0)
			of_node_get(np);

		if (of_device_is_compatible(np, "u3-ht")) {
			of_node_get(np);
			ht = np;
		}
	}
	of_node_put(root);

	/* Now setup the HyperTransport host if we found any
	 */
	if (ht && maple_add_bridge(ht) != 0)
		of_node_put(ht);

	/* Setup the linkage between OF nodes and PHBs */ 
	pci_devs_phb_init();

	/* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
	 * assume there is no P2P bridge on the AGP bus, which should be a
	 * safe assumptions hopefully.
	 */
	if (u3_agp) {
		struct device_node *np = u3_agp->dn;
		PCI_DN(np)->busno = 0xf0;
		for (np = np->child; np; np = np->sibling)
			PCI_DN(np)->busno = 0xf0;
	}

	/* Tell pci.c to not change any resource allocations.  */
	pci_probe_only = 1;
}

int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
{
	struct device_node *np;
	unsigned int defirq = channel ? 15 : 14;
	unsigned int irq;

	if (pdev->vendor != PCI_VENDOR_ID_AMD ||
	    pdev->device != PCI_DEVICE_ID_AMD_8111_IDE)
		return defirq;

	np = pci_device_to_OF_node(pdev);
	if (np == NULL) {
		printk("Failed to locate OF node for IDE %s\n",
		       pci_name(pdev));
		return defirq;
	}
	irq = irq_of_parse_and_map(np, channel & 0x1);
	if (irq == NO_IRQ) {
		printk("Failed to map onboard IDE interrupt for channel %d\n",
		       channel);
		return defirq;
	}
	return irq;
}

static void __devinit quirk_ipr_msi(struct pci_dev *dev)
{
	/* Something prevents MSIs from the IPR from working on Bimini,
	 * and the driver has no smarts to recover. So disable MSI
	 * on it for now. */

	if (machine_is(maple)) {
		dev->no_msi = 1;
		dev_info(&dev->dev, "Quirk disabled MSI\n");
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
			quirk_ipr_msi);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
	3	* IBM Corp.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*/
	10
c10af8c3	11	#undef DEBUG
1da177e4 LT	12
	13	#include <linux/kernel.h>
	14	#include <linux/pci.h>
	15	#include <linux/delay.h>
	16	#include <linux/string.h>
	17	#include <linux/init.h>
	18	#include <linux/bootmem.h>
c10af8c3	19	#include <linux/irq.h>
1da177e4 LT	20
	21	#include <asm/sections.h>
	22	#include <asm/io.h>
	23	#include <asm/prom.h>
	24	#include <asm/pci-bridge.h>
	25	#include <asm/machdep.h>
	26	#include <asm/iommu.h>
d387899f	27	#include <asm/ppc-pci.h>
1da177e4	28
0cb7b2af PM	29	#include "maple.h"
0cb7b2af PM	30
1da177e4 LT	31	#ifdef DEBUG
	32	#define DBG(x...) printk(x)
	33	#else
	34	#define DBG(x...)
	35	#endif
	36
c10af8c3	37	static struct pci_controller u3_agp, u3_ht, *u4_pcie;
1da177e4 LT	38
	39	static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
	40	{
	41	for (; node != 0;node = node->sibling) {
eeb2b723 JK	42	const int *bus_range;
eeb2b723 JK	43	const unsigned int *class_code;
1da177e4 LT	44	int len;
	45
	46	/* For PCI<->PCI bridges or CardBus bridges, we go down */
e2eb6392	47	class_code = of_get_property(node, "class-code", NULL);
1da177e4 LT	48	if (!class_code \|\| ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
	49	(*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
	50	continue;
e2eb6392	51	bus_range = of_get_property(node, "bus-range", &len);
1da177e4 LT	52	if (bus_range != NULL && len > 2 * sizeof(int)) {
	53	if (bus_range[1] > higher)
	54	higher = bus_range[1];
	55	}
	56	higher = fixup_one_level_bus_range(node->child, higher);
	57	}
	58	return higher;
	59	}
	60
	61	/* This routine fixes the "bus-range" property of all bridges in the
	62	* system since they tend to have their "last" member wrong on macs
	63	*
	64	* Note that the bus numbers manipulated here are OF bus numbers, they
	65	* are not Linux bus numbers.
	66	*/
	67	static void __init fixup_bus_range(struct device_node *bridge)
	68	{
eeb2b723 JK	69	int *bus_range;
eeb2b723 JK	70	struct property *prop;
1da177e4 LT	71	int len;
	72
	73	/* Lookup the "bus-range" property for the hose */
eeb2b723 JK	74	prop = of_find_property(bridge, "bus-range", &len);
eeb2b723 JK	75	if (prop == NULL \|\| prop->value == NULL \|\| len < 2 * sizeof(int)) {
1da177e4 LT	76	printk(KERN_WARNING "Can't get bus-range for %s\n",
	77	bridge->full_name);
	78	return;
	79	}
1a38147e	80	bus_range = prop->value;
1da177e4 LT	81	bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
	82	}
	83
	84
cc9881ce NL	85	static unsigned long u3_agp_cfa0(u8 devfn, u8 off)
	86	{
	87	return (1 << (unsigned long)PCI_SLOT(devfn)) \|
	88	((unsigned long)PCI_FUNC(devfn) << 8) \|
	89	((unsigned long)off & 0xFCUL);
	90	}
1da177e4	91
cc9881ce NL	92	static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off)
	93	{
	94	return ((unsigned long)bus << 16) \|
	95	((unsigned long)devfn << 8) \|
	96	((unsigned long)off & 0xFCUL) \|
	97	1UL;
	98	}
1da177e4	99
8c42ec2c	100	static volatile void __iomem u3_agp_cfg_access(struct pci_controller hose,
1da177e4 LT	101	u8 bus, u8 dev_fn, u8 offset)
	102	{
	103	unsigned int caddr;
	104
	105	if (bus == hose->first_busno) {
	106	if (dev_fn < (11 << 3))
8c42ec2c	107	return NULL;
cc9881ce	108	caddr = u3_agp_cfa0(dev_fn, offset);
1da177e4	109	} else
cc9881ce	110	caddr = u3_agp_cfa1(bus, dev_fn, offset);
1da177e4 LT	111
	112	/* Uninorth will return garbage if we don't read back the value ! */
	113	do {
	114	out_le32(hose->cfg_addr, caddr);
	115	} while (in_le32(hose->cfg_addr) != caddr);
	116
	117	offset &= 0x07;
8c42ec2c	118	return hose->cfg_data + offset;
1da177e4 LT	119	}
	120
	121	static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
	122	int offset, int len, u32 *val)
	123	{
	124	struct pci_controller *hose;
8c42ec2c	125	volatile void __iomem *addr;
1da177e4 LT	126
	127	hose = pci_bus_to_host(bus);
	128	if (hose == NULL)
	129	return PCIBIOS_DEVICE_NOT_FOUND;
	130
	131	addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
	132	if (!addr)
	133	return PCIBIOS_DEVICE_NOT_FOUND;
	134	/*
	135	* Note: the caller has already checked that offset is
	136	* suitably aligned and that len is 1, 2 or 4.
	137	*/
	138	switch (len) {
	139	case 1:
8c42ec2c	140	*val = in_8(addr);
1da177e4 LT	141	break;
1da177e4 LT	142	case 2:
8c42ec2c	143	*val = in_le16(addr);
1da177e4 LT	144	break;
1da177e4 LT	145	default:
8c42ec2c	146	*val = in_le32(addr);
1da177e4 LT	147	break;
	148	}
	149	return PCIBIOS_SUCCESSFUL;
	150	}
	151
	152	static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
	153	int offset, int len, u32 val)
	154	{
	155	struct pci_controller *hose;
8c42ec2c	156	volatile void __iomem *addr;
1da177e4 LT	157
	158	hose = pci_bus_to_host(bus);
	159	if (hose == NULL)
	160	return PCIBIOS_DEVICE_NOT_FOUND;
	161
	162	addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
	163	if (!addr)
	164	return PCIBIOS_DEVICE_NOT_FOUND;
	165	/*
	166	* Note: the caller has already checked that offset is
	167	* suitably aligned and that len is 1, 2 or 4.
	168	*/
	169	switch (len) {
	170	case 1:
8c42ec2c	171	out_8(addr, val);
1da177e4 LT	172	break;
1da177e4 LT	173	case 2:
8c42ec2c	174	out_le16(addr, val);
1da177e4 LT	175	break;
1da177e4 LT	176	default:
8c42ec2c	177	out_le32(addr, val);
1da177e4 LT	178	break;
	179	}
	180	return PCIBIOS_SUCCESSFUL;
	181	}
	182
	183	static struct pci_ops u3_agp_pci_ops =
	184	{
2e67d407 NL	185	.read = u3_agp_read_config,
2e67d407 NL	186	.write = u3_agp_write_config,
1da177e4 LT	187	};
1da177e4 LT	188
cc9881ce NL	189	static unsigned long u3_ht_cfa0(u8 devfn, u8 off)
	190	{
	191	return (devfn << 8) \| off;
	192	}
1da177e4	193
cc9881ce NL	194	static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off)
	195	{
	196	return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL;
	197	}
1da177e4	198
8c42ec2c	199	static volatile void __iomem u3_ht_cfg_access(struct pci_controller hose,
1da177e4 LT	200	u8 bus, u8 devfn, u8 offset)
	201	{
	202	if (bus == hose->first_busno) {
	203	if (PCI_SLOT(devfn) == 0)
8c42ec2c AV	204	return NULL;
8c42ec2c AV	205	return hose->cfg_data + u3_ht_cfa0(devfn, offset);
1da177e4	206	} else
8c42ec2c	207	return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);
1da177e4 LT	208	}
	209
	210	static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
	211	int offset, int len, u32 *val)
	212	{
	213	struct pci_controller *hose;
8c42ec2c	214	volatile void __iomem *addr;
1da177e4 LT	215
	216	hose = pci_bus_to_host(bus);
	217	if (hose == NULL)
	218	return PCIBIOS_DEVICE_NOT_FOUND;
	219
d608df5c NL	220	if (offset > 0xff)
	221	return PCIBIOS_BAD_REGISTER_NUMBER;
	222
1da177e4 LT	223	addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
	224	if (!addr)
	225	return PCIBIOS_DEVICE_NOT_FOUND;
	226
	227	/*
	228	* Note: the caller has already checked that offset is
	229	* suitably aligned and that len is 1, 2 or 4.
	230	*/
	231	switch (len) {
	232	case 1:
8c42ec2c	233	*val = in_8(addr);
1da177e4 LT	234	break;
1da177e4 LT	235	case 2:
8c42ec2c	236	*val = in_le16(addr);
1da177e4 LT	237	break;
1da177e4 LT	238	default:
8c42ec2c	239	*val = in_le32(addr);
1da177e4 LT	240	break;
	241	}
	242	return PCIBIOS_SUCCESSFUL;
	243	}
	244
	245	static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
	246	int offset, int len, u32 val)
	247	{
	248	struct pci_controller *hose;
8c42ec2c	249	volatile void __iomem *addr;
1da177e4 LT	250
	251	hose = pci_bus_to_host(bus);
	252	if (hose == NULL)
	253	return PCIBIOS_DEVICE_NOT_FOUND;
	254
d608df5c NL	255	if (offset > 0xff)
	256	return PCIBIOS_BAD_REGISTER_NUMBER;
	257
1da177e4 LT	258	addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
	259	if (!addr)
	260	return PCIBIOS_DEVICE_NOT_FOUND;
	261	/*
	262	* Note: the caller has already checked that offset is
	263	* suitably aligned and that len is 1, 2 or 4.
	264	*/
	265	switch (len) {
	266	case 1:
8c42ec2c	267	out_8(addr, val);
1da177e4 LT	268	break;
1da177e4 LT	269	case 2:
8c42ec2c	270	out_le16(addr, val);
1da177e4 LT	271	break;
1da177e4 LT	272	default:
8c42ec2c	273	out_le32(addr, val);
1da177e4 LT	274	break;
	275	}
	276	return PCIBIOS_SUCCESSFUL;
	277	}
	278
	279	static struct pci_ops u3_ht_pci_ops =
	280	{
2e67d407 NL	281	.read = u3_ht_read_config,
2e67d407 NL	282	.write = u3_ht_write_config,
1da177e4 LT	283	};
1da177e4 LT	284
c10af8c3 BH	285	static unsigned int u4_pcie_cfa0(unsigned int devfn, unsigned int off)
	286	{
	287	return (1 << PCI_SLOT(devfn)) \|
	288	(PCI_FUNC(devfn) << 8) \|
	289	((off >> 8) << 28) \|
	290	(off & 0xfcu);
	291	}
	292
	293	static unsigned int u4_pcie_cfa1(unsigned int bus, unsigned int devfn,
	294	unsigned int off)
	295	{
	296	return (bus << 16) \|
	297	(devfn << 8) \|
	298	((off >> 8) << 28) \|
	299	(off & 0xfcu) \| 1u;
	300	}
	301
	302	static volatile void __iomem u4_pcie_cfg_access(struct pci_controller hose,
	303	u8 bus, u8 dev_fn, int offset)
	304	{
	305	unsigned int caddr;
	306
	307	if (bus == hose->first_busno)
	308	caddr = u4_pcie_cfa0(dev_fn, offset);
	309	else
	310	caddr = u4_pcie_cfa1(bus, dev_fn, offset);
	311
	312	/* Uninorth will return garbage if we don't read back the value ! */
	313	do {
	314	out_le32(hose->cfg_addr, caddr);
	315	} while (in_le32(hose->cfg_addr) != caddr);
	316
	317	offset &= 0x03;
	318	return hose->cfg_data + offset;
	319	}
	320
	321	static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
	322	int offset, int len, u32 *val)
	323	{
	324	struct pci_controller *hose;
	325	volatile void __iomem *addr;
	326
	327	hose = pci_bus_to_host(bus);
	328	if (hose == NULL)
	329	return PCIBIOS_DEVICE_NOT_FOUND;
	330	if (offset >= 0x1000)
	331	return PCIBIOS_BAD_REGISTER_NUMBER;
	332	addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
	333	if (!addr)
	334	return PCIBIOS_DEVICE_NOT_FOUND;
	335	/*
	336	* Note: the caller has already checked that offset is
	337	* suitably aligned and that len is 1, 2 or 4.
	338	*/
	339	switch (len) {
	340	case 1:
	341	*val = in_8(addr);
	342	break;
	343	case 2:
	344	*val = in_le16(addr);
	345	break;
	346	default:
	347	*val = in_le32(addr);
	348	break;
349	}
350	return PCIBIOS_SUCCESSFUL;
351	}
352	static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
353	int offset, int len, u32 val)
354	{
355	struct pci_controller *hose;
356	volatile void __iomem *addr;
357
358	hose = pci_bus_to_host(bus);
359	if (hose == NULL)
360	return PCIBIOS_DEVICE_NOT_FOUND;
361	if (offset >= 0x1000)
362	return PCIBIOS_BAD_REGISTER_NUMBER;
363	addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
364	if (!addr)
365	return PCIBIOS_DEVICE_NOT_FOUND;
366	/*
367	* Note: the caller has already checked that offset is
368	* suitably aligned and that len is 1, 2 or 4.
369	*/
370	switch (len) {
371	case 1:
372	out_8(addr, val);
c10af8c3 BH	373	break;
	374	case 2:
	375	out_le16(addr, val);
c10af8c3 BH	376	break;
	377	default:
	378	out_le32(addr, val);
c10af8c3 BH	379	break;
	380	}
	381	return PCIBIOS_SUCCESSFUL;
	382	}
	383
	384	static struct pci_ops u4_pcie_pci_ops =
	385	{
2e67d407 NL	386	.read = u4_pcie_read_config,
2e67d407 NL	387	.write = u4_pcie_write_config,
c10af8c3 BH	388	};
c10af8c3 BH	389
1da177e4 LT	390	static void __init setup_u3_agp(struct pci_controller* hose)
	391	{
	392	/* On G5, we move AGP up to high bus number so we don't need
	393	* to reassign bus numbers for HT. If we ever have P2P bridges
399fe2bd	394	* on AGP, we'll have to move pci_assign_all_buses to the
1da177e4 LT	395	* pci_controller structure so we enable it for AGP and not for
	396	* HT childs.
	397	* We hard code the address because of the different size of
	398	* the reg address cell, we shall fix that by killing struct
	399	* reg_property and using some accessor functions instead
	400	*/
3238e9c9	401	hose->first_busno = 0xf0;
1da177e4 LT	402	hose->last_busno = 0xff;
	403	hose->ops = &u3_agp_pci_ops;
	404	hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
	405	hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
	406
	407	u3_agp = hose;
	408	}
	409
c10af8c3 BH	410	static void __init setup_u4_pcie(struct pci_controller* hose)
	411	{
	412	/* We currently only implement the "non-atomic" config space, to
	413	* be optimised later.
	414	*/
	415	hose->ops = &u4_pcie_pci_ops;
	416	hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
	417	hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
	418
c10af8c3 BH	419	u4_pcie = hose;
	420	}
	421
1da177e4 LT	422	static void __init setup_u3_ht(struct pci_controller* hose)
	423	{
	424	hose->ops = &u3_ht_pci_ops;
	425
	426	/* We hard code the address because of the different size of
	427	* the reg address cell, we shall fix that by killing struct
	428	* reg_property and using some accessor functions instead
	429	*/
8c42ec2c	430	hose->cfg_data = ioremap(0xf2000000, 0x02000000);
1da177e4 LT	431
	432	hose->first_busno = 0;
	433	hose->last_busno = 0xef;
	434
	435	u3_ht = hose;
	436	}
	437
09b55f76	438	static int __init maple_add_bridge(struct device_node *dev)
1da177e4 LT	439	{
	440	int len;
	441	struct pci_controller *hose;
	442	char* disp_name;
eeb2b723	443	const int *bus_range;
1da177e4	444	int primary = 1;
1da177e4 LT	445
	446	DBG("Adding PCI host bridge %s\n", dev->full_name);
	447
e2eb6392	448	bus_range = of_get_property(dev, "bus-range", &len);
3238e9c9 AB	449	if (bus_range == NULL \|\| len < 2 * sizeof(int)) {
	450	printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
	451	dev->full_name);
	452	}
1da177e4	453
b5166cc2	454	hose = pcibios_alloc_controller(dev);
1da177e4 LT	455	if (hose == NULL)
1da177e4 LT	456	return -ENOMEM;
3238e9c9 AB	457	hose->first_busno = bus_range ? bus_range[0] : 0;
3238e9c9 AB	458	hose->last_busno = bus_range ? bus_range[1] : 0xff;
1da177e4	459
1da177e4	460	disp_name = NULL;
55b61fec	461	if (of_device_is_compatible(dev, "u3-agp")) {
3238e9c9 AB	462	setup_u3_agp(hose);
	463	disp_name = "U3-AGP";
	464	primary = 0;
55b61fec	465	} else if (of_device_is_compatible(dev, "u3-ht")) {
3238e9c9 AB	466	setup_u3_ht(hose);
	467	disp_name = "U3-HT";
	468	primary = 1;
55b61fec	469	} else if (of_device_is_compatible(dev, "u4-pcie")) {
c10af8c3 BH	470	setup_u4_pcie(hose);
	471	disp_name = "U4-PCIE";
	472	primary = 0;
3238e9c9 AB	473	}
	474	printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
	475	disp_name, hose->first_busno, hose->last_busno);
	476
	477	/* Interpret the "ranges" property */
	478	/* This also maps the I/O region and sets isa_io/mem_base */
f7abbc19	479	pci_process_bridge_OF_ranges(hose, dev, primary);
1da177e4	480
3238e9c9 AB	481	/* Fixup "bus-range" OF property */
3238e9c9 AB	482	fixup_bus_range(dev);
1da177e4	483
17cd87c2 BH	484	/* Check for legacy IOs */
	485	isa_bridge_find_early(hose);
	486
1da177e4 LT	487	return 0;
	488	}
	489
	490
f90bb153	491	void __devinit maple_pci_irq_fixup(struct pci_dev *dev)
1da177e4	492	{
f90bb153 BH	493	DBG(" -> maple_pci_irq_fixup\n");
	494
	495	/* Fixup IRQ for PCIe host */
	496	if (u4_pcie != NULL && dev->bus->number == 0 &&
	497	pci_bus_to_host(dev->bus) == u4_pcie) {
	498	printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n");
	499	dev->irq = irq_create_mapping(NULL, 1);
	500	if (dev->irq != NO_IRQ)
	501	set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
	502	}
1e1b20a1	503
f90bb153 BH	504	/* Hide AMD8111 IDE interrupt when in legacy mode so
	505	* the driver calls pci_get_legacy_ide_irq()
	506	*/
	507	if (dev->vendor == PCI_VENDOR_ID_AMD &&
	508	dev->device == PCI_DEVICE_ID_AMD_8111_IDE &&
	509	(dev->class & 5) != 5) {
	510	dev->irq = NO_IRQ;
c10af8c3	511	}
1da177e4	512
f90bb153	513	DBG(" <- maple_pci_irq_fixup\n");
1da177e4 LT	514	}
1da177e4 LT	515
1da177e4 LT	516	void __init maple_pci_init(void)
	517	{
	518	struct device_node np, root;
	519	struct device_node *ht = NULL;
	520
	521	/* Probe root PCI hosts, that is on U3 the AGP host and the
	522	* HyperTransport host. That one is actually "kept" around
	523	* and actually added last as it's resource management relies
	524	* on the AGP resources to have been setup first
	525	*/
	526	root = of_find_node_by_path("/");
	527	if (root == NULL) {
	528	printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n");
	529	return;
	530	}
	531	for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
f1f00333	532	if (!np->type)
1da177e4	533	continue;
f1f00333 NL	534	if (strcmp(np->type, "pci") && strcmp(np->type, "ht"))
f1f00333 NL	535	continue;
55b61fec SR	536	if ((of_device_is_compatible(np, "u4-pcie") \|\|
55b61fec SR	537	of_device_is_compatible(np, "u3-agp")) &&
09b55f76	538	maple_add_bridge(np) == 0)
f1f00333 NL	539	of_node_get(np);
f1f00333 NL	540
55b61fec	541	if (of_device_is_compatible(np, "u3-ht")) {
1da177e4 LT	542	of_node_get(np);
	543	ht = np;
	544	}
	545	}
	546	of_node_put(root);
	547
	548	/* Now setup the HyperTransport host if we found any
	549	*/
09b55f76	550	if (ht && maple_add_bridge(ht) != 0)
1da177e4 LT	551	of_node_put(ht);
1da177e4 LT	552
1da177e4 LT	553	/* Setup the linkage between OF nodes and PHBs */
	554	pci_devs_phb_init();
	555
	556	/* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
	557	* assume there is no P2P bridge on the AGP bus, which should be a
	558	* safe assumptions hopefully.
	559	*/
	560	if (u3_agp) {
44ef3390	561	struct device_node *np = u3_agp->dn;
1635317f	562	PCI_DN(np)->busno = 0xf0;
1da177e4	563	for (np = np->child; np; np = np->sibling)
1635317f	564	PCI_DN(np)->busno = 0xf0;
1da177e4 LT	565	}
1da177e4 LT	566
4558f417 SB	567	/* Tell pci.c to not change any resource allocations. */
4558f417 SB	568	pci_probe_only = 1;
1da177e4 LT	569	}
	570
	571	int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
	572	{
	573	struct device_node *np;
0ebfff14 BH	574	unsigned int defirq = channel ? 15 : 14;
0ebfff14 BH	575	unsigned int irq;
1da177e4 LT	576
	577	if (pdev->vendor != PCI_VENDOR_ID_AMD \|\|
	578	pdev->device != PCI_DEVICE_ID_AMD_8111_IDE)
0ebfff14	579	return defirq;
1da177e4 LT	580
1da177e4 LT	581	np = pci_device_to_OF_node(pdev);
c10af8c3 BH	582	if (np == NULL) {
	583	printk("Failed to locate OF node for IDE %s\n",
	584	pci_name(pdev));
0ebfff14	585	return defirq;
c10af8c3	586	}
0ebfff14 BH	587	irq = irq_of_parse_and_map(np, channel & 0x1);
	588	if (irq == NO_IRQ) {
	589	printk("Failed to map onboard IDE interrupt for channel %d\n",
	590	channel);
	591	return defirq;
	592	}
	593	return irq;
1da177e4	594	}
6eb0ac03 ME	595
	596	static void __devinit quirk_ipr_msi(struct pci_dev *dev)
	597	{
	598	/* Something prevents MSIs from the IPR from working on Bimini,
	599	* and the driver has no smarts to recover. So disable MSI
	600	* on it for now. */
	601
	602	if (machine_is(maple)) {
	603	dev->no_msi = 1;
	604	dev_info(&dev->dev, "Quirk disabled MSI\n");
	605	}
	606	}
	607	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
	608	quirk_ipr_msi);