[deliverable/linux.git] / arch / powerpc / platforms / pasemi / pci.c

/*
 * Copyright (C) 2006 PA Semi, Inc
 *
 * Authors: Kip Walker, PA Semi
 *	    Olof Johansson, PA Semi
 *
 * Maintained by: Olof Johansson <olof@lixom.net>
 *
 * Based on arch/powerpc/platforms/maple/pci.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */


#include <linux/kernel.h>
#include <linux/pci.h>

#include <asm/pci-bridge.h>
#include <asm/machdep.h>

#include <asm/ppc-pci.h>

#define PA_PXP_CFA(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))

static inline int pa_pxp_offset_valid(u8 bus, u8 devfn, int offset)
{
	/* Device 0 Function 0 is special: It's config space spans function 1 as
	 * well, so allow larger offset. It's really a two-function device but the
	 * second function does not probe.
	 */
	if (bus == 0 && devfn == 0)
		return offset < 8192;
	else
		return offset < 4096;
}

static void volatile __iomem *pa_pxp_cfg_addr(struct pci_controller *hose,
				       u8 bus, u8 devfn, int offset)
{
	return hose->cfg_data + PA_PXP_CFA(bus, devfn, offset);
}

static int pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn,
			      int offset, int len, u32 *val)
{
	struct pci_controller *hose;
	void volatile __iomem *addr;

	hose = pci_bus_to_host(bus);
	if (!hose)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (!pa_pxp_offset_valid(bus->number, devfn, offset))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);

	/*
	 * Note: the caller has already checked that offset is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	switch (len) {
	case 1:
		*val = in_8(addr);
		break;
	case 2:
		*val = in_le16(addr);
		break;
	default:
		*val = in_le32(addr);
		break;
	}

	return PCIBIOS_SUCCESSFUL;
}

static int pa_pxp_write_config(struct pci_bus *bus, unsigned int devfn,
			       int offset, int len, u32 val)
{
	struct pci_controller *hose;
	void volatile __iomem *addr;

	hose = pci_bus_to_host(bus);
	if (!hose)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (!pa_pxp_offset_valid(bus->number, devfn, offset))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);

	/*
	 * Note: the caller has already checked that offset is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	switch (len) {
	case 1:
		out_8(addr, val);
		(void) in_8(addr);
		break;
	case 2:
		out_le16(addr, val);
		(void) in_le16(addr);
		break;
	default:
		out_le32(addr, val);
		(void) in_le32(addr);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops pa_pxp_ops = {
	pa_pxp_read_config,
	pa_pxp_write_config,
};

static void __init setup_pa_pxp(struct pci_controller *hose)
{
	hose->ops = &pa_pxp_ops;
	hose->cfg_data = ioremap(0xe0000000, 0x10000000);
}

static int __init add_bridge(struct device_node *dev)
{
	struct pci_controller *hose;

	pr_debug("Adding PCI host bridge %s\n", dev->full_name);

	hose = pcibios_alloc_controller(dev);
	if (!hose)
		return -ENOMEM;

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	setup_pa_pxp(hose);

	printk(KERN_INFO "Found PA-PXP PCI host bridge.\n");

	/* Interpret the "ranges" property */
	pci_process_bridge_OF_ranges(hose, dev, 1);

	return 0;
}

void __init pas_pci_init(void)
{
	struct device_node *np, *root;

	root = of_find_node_by_path("/");
	if (!root) {
		printk(KERN_CRIT "pas_pci_init: can't find root "
			"of device tree\n");
		return;
	}

	for (np = NULL; (np = of_get_next_child(root, np)) != NULL;)
		if (np->name && !strcmp(np->name, "pxp") && !add_bridge(np))
			of_node_get(np);

	of_node_put(root);

	/* Setup the linkage between OF nodes and PHBs */
	pci_devs_phb_init();

	/* Use the common resource allocation mechanism */
	pci_probe_only = 1;
}
Commit	Line	Data
1e76875e OJ	1	/*
	2	* Copyright (C) 2006 PA Semi, Inc
	3	*
	4	* Authors: Kip Walker, PA Semi
	5	* Olof Johansson, PA Semi
	6	*
	7	* Maintained by: Olof Johansson <olof@lixom.net>
	8	*
	9	* Based on arch/powerpc/platforms/maple/pci.c
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*/
	24
	25
	26	#include <linux/kernel.h>
	27	#include <linux/pci.h>
	28
	29	#include <asm/pci-bridge.h>
	30	#include <asm/machdep.h>
	31
	32	#include <asm/ppc-pci.h>
	33
	34	#define PA_PXP_CFA(bus, devfn, off) (((bus) << 20) \| ((devfn) << 12) \| (off))
	35
df7e70a2 OJ	36	static inline int pa_pxp_offset_valid(u8 bus, u8 devfn, int offset)
	37	{
	38	/* Device 0 Function 0 is special: It's config space spans function 1 as
	39	* well, so allow larger offset. It's really a two-function device but the
	40	* second function does not probe.
	41	*/
	42	if (bus == 0 && devfn == 0)
	43	return offset < 8192;
	44	else
	45	return offset < 4096;
	46	}
1e76875e	47
7c84ace9	48	static void volatile __iomem pa_pxp_cfg_addr(struct pci_controller hose,
1e76875e OJ	49	u8 bus, u8 devfn, int offset)
1e76875e OJ	50	{
7c84ace9	51	return hose->cfg_data + PA_PXP_CFA(bus, devfn, offset);
1e76875e OJ	52	}
	53
	54	static int pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn,
	55	int offset, int len, u32 *val)
	56	{
	57	struct pci_controller *hose;
7c84ace9	58	void volatile __iomem *addr;
1e76875e OJ	59
	60	hose = pci_bus_to_host(bus);
	61	if (!hose)
	62	return PCIBIOS_DEVICE_NOT_FOUND;
	63
df7e70a2	64	if (!pa_pxp_offset_valid(bus->number, devfn, offset))
1e76875e OJ	65	return PCIBIOS_BAD_REGISTER_NUMBER;
	66
	67	addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
	68
	69	/*
	70	* Note: the caller has already checked that offset is
	71	* suitably aligned and that len is 1, 2 or 4.
	72	*/
	73	switch (len) {
	74	case 1:
7c84ace9	75	*val = in_8(addr);
1e76875e OJ	76	break;
1e76875e OJ	77	case 2:
7c84ace9	78	*val = in_le16(addr);
1e76875e OJ	79	break;
1e76875e OJ	80	default:
7c84ace9	81	*val = in_le32(addr);
1e76875e OJ	82	break;
	83	}
	84
	85	return PCIBIOS_SUCCESSFUL;
	86	}
	87
	88	static int pa_pxp_write_config(struct pci_bus *bus, unsigned int devfn,
	89	int offset, int len, u32 val)
	90	{
	91	struct pci_controller *hose;
7c84ace9	92	void volatile __iomem *addr;
1e76875e OJ	93
	94	hose = pci_bus_to_host(bus);
	95	if (!hose)
	96	return PCIBIOS_DEVICE_NOT_FOUND;
	97
df7e70a2	98	if (!pa_pxp_offset_valid(bus->number, devfn, offset))
1e76875e OJ	99	return PCIBIOS_BAD_REGISTER_NUMBER;
	100
	101	addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
	102
	103	/*
	104	* Note: the caller has already checked that offset is
	105	* suitably aligned and that len is 1, 2 or 4.
	106	*/
	107	switch (len) {
	108	case 1:
7c84ace9 AV	109	out_8(addr, val);
7c84ace9 AV	110	(void) in_8(addr);
1e76875e OJ	111	break;
1e76875e OJ	112	case 2:
7c84ace9 AV	113	out_le16(addr, val);
7c84ace9 AV	114	(void) in_le16(addr);
1e76875e OJ	115	break;
1e76875e OJ	116	default:
7c84ace9 AV	117	out_le32(addr, val);
7c84ace9 AV	118	(void) in_le32(addr);
1e76875e OJ	119	break;
	120	}
	121	return PCIBIOS_SUCCESSFUL;
	122	}
	123
	124	static struct pci_ops pa_pxp_ops = {
	125	pa_pxp_read_config,
	126	pa_pxp_write_config,
	127	};
	128
	129	static void __init setup_pa_pxp(struct pci_controller *hose)
	130	{
	131	hose->ops = &pa_pxp_ops;
	132	hose->cfg_data = ioremap(0xe0000000, 0x10000000);
	133	}
	134
	135	static int __init add_bridge(struct device_node *dev)
	136	{
	137	struct pci_controller *hose;
	138
	139	pr_debug("Adding PCI host bridge %s\n", dev->full_name);
	140
	141	hose = pcibios_alloc_controller(dev);
	142	if (!hose)
	143	return -ENOMEM;
	144
	145	hose->first_busno = 0;
	146	hose->last_busno = 0xff;
	147
	148	setup_pa_pxp(hose);
	149
	150	printk(KERN_INFO "Found PA-PXP PCI host bridge.\n");
	151
	152	/* Interpret the "ranges" property */
1e76875e	153	pci_process_bridge_OF_ranges(hose, dev, 1);
1e76875e OJ	154
	155	return 0;
	156	}
	157
1e76875e OJ	158	void __init pas_pci_init(void)
	159	{
	160	struct device_node np, root;
	161
	162	root = of_find_node_by_path("/");
	163	if (!root) {
	164	printk(KERN_CRIT "pas_pci_init: can't find root "
	165	"of device tree\n");
	166	return;
	167	}
	168
	169	for (np = NULL; (np = of_get_next_child(root, np)) != NULL;)
	170	if (np->name && !strcmp(np->name, "pxp") && !add_bridge(np))
	171	of_node_get(np);
	172
	173	of_node_put(root);
	174
1e76875e OJ	175	/* Setup the linkage between OF nodes and PHBs */
	176	pci_devs_phb_init();
	177
	178	/* Use the common resource allocation mechanism */
	179	pci_probe_only = 1;
	180	}