[deliverable/linux.git] / arch / powerpc / platforms / pasemi / setup.c

/*
 * Copyright (C) 2006-2007 PA Semi, Inc
 *
 * Authors: Kip Walker, PA Semi
 *	    Olof Johansson, PA Semi
 *
 * Maintained by: Olof Johansson <olof@lixom.net>
 *
 * Based on arch/powerpc/platforms/maple/setup.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/console.h>
#include <linux/pci.h>
#include <linux/of_platform.h>

#include <asm/prom.h>
#include <asm/system.h>
#include <asm/iommu.h>
#include <asm/machdep.h>
#include <asm/mpic.h>
#include <asm/smp.h>
#include <asm/time.h>
#include <asm/mmu.h>

#include <pcmcia/ss.h>
#include <pcmcia/cistpl.h>
#include <pcmcia/ds.h>

#include "pasemi.h"

#if !defined(CONFIG_SMP)
static void smp_send_stop(void) {}
#endif

/* SDC reset register, must be pre-mapped at reset time */
static void __iomem *reset_reg;

/* Various error status registers, must be pre-mapped at MCE time */

#define MAX_MCE_REGS	32
struct mce_regs {
	char *name;
	void __iomem *addr;
};

static struct mce_regs mce_regs[MAX_MCE_REGS];
static int num_mce_regs;


static void pas_restart(char *cmd)
{
	/* Need to put others cpu in hold loop so they're not sleeping */
	smp_send_stop();
	udelay(10000);
	printk("Restarting...\n");
	while (1)
		out_le32(reset_reg, 0x6000000);
}

#ifdef CONFIG_SMP
static DEFINE_SPINLOCK(timebase_lock);
static unsigned long timebase;

static void __devinit pas_give_timebase(void)
{
	spin_lock(&timebase_lock);
	mtspr(SPRN_TBCTL, TBCTL_FREEZE);
	isync();
	timebase = get_tb();
	spin_unlock(&timebase_lock);

	while (timebase)
		barrier();
	mtspr(SPRN_TBCTL, TBCTL_RESTART);
}

static void __devinit pas_take_timebase(void)
{
	while (!timebase)
		smp_rmb();

	spin_lock(&timebase_lock);
	set_tb(timebase >> 32, timebase & 0xffffffff);
	timebase = 0;
	spin_unlock(&timebase_lock);
}

struct smp_ops_t pas_smp_ops = {
	.probe		= smp_mpic_probe,
	.message_pass	= smp_mpic_message_pass,
	.kick_cpu	= smp_generic_kick_cpu,
	.setup_cpu	= smp_mpic_setup_cpu,
	.give_timebase	= pas_give_timebase,
	.take_timebase	= pas_take_timebase,
};
#endif /* CONFIG_SMP */

void __init pas_setup_arch(void)
{
#ifdef CONFIG_SMP
	/* Setup SMP callback */
	smp_ops = &pas_smp_ops;
#endif
	/* Lookup PCI hosts */
	pas_pci_init();

#ifdef CONFIG_DUMMY_CONSOLE
	conswitchp = &dummy_con;
#endif

	/* Remap SDC register for doing reset */
	/* XXXOJN This should maybe come out of the device tree */
	reset_reg = ioremap(0xfc101100, 4);
}

static int __init pas_setup_mce_regs(void)
{
	struct pci_dev *dev;
	int reg;

	if (!machine_is(pasemi))
		return -ENODEV;

	/* Remap various SoC status registers for use by the MCE handler */

	reg = 0;

	dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
	while (dev && reg < MAX_MCE_REGS) {
		mce_regs[reg].name = kasprintf(GFP_KERNEL,
						"mc%d_mcdebug_errsta", reg);
		mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
		dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
		reg++;
	}

	dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
	if (dev && reg+4 < MAX_MCE_REGS) {
		mce_regs[reg].name = "iobdbg_IntStatus1";
		mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
		reg++;
		mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
		mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
		reg++;
		mce_regs[reg].name = "iobiom_IntStatus";
		mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
		reg++;
		mce_regs[reg].name = "iobiom_IntDbgReg";
		mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
		reg++;
	}

	dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
	if (dev && reg+2 < MAX_MCE_REGS) {
		mce_regs[reg].name = "l2csts_IntStatus";
		mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
		reg++;
		mce_regs[reg].name = "l2csts_Cnt";
		mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
		reg++;
	}

	num_mce_regs = reg;

	return 0;
}
device_initcall(pas_setup_mce_regs);

static __init void pas_init_IRQ(void)
{
	struct device_node *np;
	struct device_node *root, *mpic_node;
	unsigned long openpic_addr;
	const unsigned int *opprop;
	int naddr, opplen;
	struct mpic *mpic;

	mpic_node = NULL;

	for_each_node_by_type(np, "interrupt-controller")
		if (of_device_is_compatible(np, "open-pic")) {
			mpic_node = np;
			break;
		}
	if (!mpic_node)
		for_each_node_by_type(np, "open-pic") {
			mpic_node = np;
			break;
		}
	if (!mpic_node) {
		printk(KERN_ERR
			"Failed to locate the MPIC interrupt controller\n");
		return;
	}

	/* Find address list in /platform-open-pic */
	root = of_find_node_by_path("/");
	naddr = of_n_addr_cells(root);
	opprop = of_get_property(root, "platform-open-pic", &opplen);
	if (!opprop) {
		printk(KERN_ERR "No platform-open-pic property.\n");
		of_node_put(root);
		return;
	}
	openpic_addr = of_read_number(opprop, naddr);
	printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);

	mpic = mpic_alloc(mpic_node, openpic_addr,
			  MPIC_PRIMARY|MPIC_LARGE_VECTORS,
			  0, 0, "PASEMI-OPIC");
	BUG_ON(!mpic);

	mpic_assign_isu(mpic, 0, openpic_addr + 0x10000);
	mpic_init(mpic);
	of_node_put(mpic_node);
	of_node_put(root);
}

static void __init pas_progress(char *s, unsigned short hex)
{
	printk("[%04x] : %s\n", hex, s ? s : "");
}


static int pas_machine_check_handler(struct pt_regs *regs)
{
	int cpu = smp_processor_id();
	unsigned long srr0, srr1, dsisr;
	int dump_slb = 0;
	int i;

	srr0 = regs->nip;
	srr1 = regs->msr;
	dsisr = mfspr(SPRN_DSISR);
	printk(KERN_ERR "Machine Check on CPU %d\n", cpu);
	printk(KERN_ERR "SRR0  0x%016lx SRR1 0x%016lx\n", srr0, srr1);
	printk(KERN_ERR "DSISR 0x%016lx DAR  0x%016lx\n", dsisr, regs->dar);
	printk(KERN_ERR "BER   0x%016lx MER  0x%016lx\n", mfspr(SPRN_PA6T_BER),
		mfspr(SPRN_PA6T_MER));
	printk(KERN_ERR "IER   0x%016lx DER  0x%016lx\n", mfspr(SPRN_PA6T_IER),
		mfspr(SPRN_PA6T_DER));
	printk(KERN_ERR "Cause:\n");

	if (srr1 & 0x200000)
		printk(KERN_ERR "Signalled by SDC\n");

	if (srr1 & 0x100000) {
		printk(KERN_ERR "Load/Store detected error:\n");
		if (dsisr & 0x8000)
			printk(KERN_ERR "D-cache ECC double-bit error or bus error\n");
		if (dsisr & 0x4000)
			printk(KERN_ERR "LSU snoop response error\n");
		if (dsisr & 0x2000) {
			printk(KERN_ERR "MMU SLB multi-hit or invalid B field\n");
			dump_slb = 1;
		}
		if (dsisr & 0x1000)
			printk(KERN_ERR "Recoverable Duptags\n");
		if (dsisr & 0x800)
			printk(KERN_ERR "Recoverable D-cache parity error count overflow\n");
		if (dsisr & 0x400)
			printk(KERN_ERR "TLB parity error count overflow\n");
	}

	if (srr1 & 0x80000)
		printk(KERN_ERR "Bus Error\n");

	if (srr1 & 0x40000) {
		printk(KERN_ERR "I-side SLB multiple hit\n");
		dump_slb = 1;
	}

	if (srr1 & 0x20000)
		printk(KERN_ERR "I-cache parity error hit\n");

	if (num_mce_regs == 0)
		printk(KERN_ERR "No MCE registers mapped yet, can't dump\n");
	else
		printk(KERN_ERR "SoC debug registers:\n");

	for (i = 0; i < num_mce_regs; i++)
		printk(KERN_ERR "%s: 0x%08x\n", mce_regs[i].name,
			in_le32(mce_regs[i].addr));

	if (dump_slb) {
		unsigned long e, v;
		int i;

		printk(KERN_ERR "slb contents:\n");
		for (i = 0; i < mmu_slb_size; i++) {
			asm volatile("slbmfee  %0,%1" : "=r" (e) : "r" (i));
			asm volatile("slbmfev  %0,%1" : "=r" (v) : "r" (i));
			printk(KERN_ERR "%02d %016lx %016lx\n", i, e, v);
		}
	}


	/* SRR1[62] is from MSR[62] if recoverable, so pass that back */
	return !!(srr1 & 0x2);
}

static void __init pas_init_early(void)
{
	iommu_init_early_pasemi();
}

#ifdef CONFIG_PCMCIA
static int pcmcia_notify(struct notifier_block *nb, unsigned long action,
			 void *data)
{
	struct device *dev = data;
	struct device *parent;
	struct pcmcia_device *pdev = to_pcmcia_dev(dev);

	/* We are only intereted in device addition */
	if (action != BUS_NOTIFY_ADD_DEVICE)
		return 0;

	parent = pdev->socket->dev.parent;

	/* We know electra_cf devices will always have of_node set, since
	 * electra_cf is an of_platform driver.
	 */
	if (!parent->archdata.of_node)
		return 0;

	if (!of_device_is_compatible(parent->archdata.of_node, "electra-cf"))
		return 0;

	/* We use the direct ops for localbus */
	dev->archdata.dma_ops = &dma_direct_ops;

	return 0;
}

static struct notifier_block pcmcia_notifier = {
	.notifier_call = pcmcia_notify,
};

static inline void pasemi_pcmcia_init(void)
{
	extern struct bus_type pcmcia_bus_type;

	bus_register_notifier(&pcmcia_bus_type, &pcmcia_notifier);
}

#else

static inline void pasemi_pcmcia_init(void)
{
}

#endif


static struct of_device_id pasemi_bus_ids[] = {
	/* Unfortunately needed for legacy firmwares */
	{ .type = "localbus", },
	{ .type = "sdc", },
	/* These are the proper entries, which newer firmware uses */
	{ .compatible = "pasemi,localbus", },
	{ .compatible = "pasemi,sdc", },
	{},
};

static int __init pasemi_publish_devices(void)
{
	if (!machine_is(pasemi))
		return 0;

	pasemi_pcmcia_init();

	/* Publish OF platform devices for SDC and other non-PCI devices */
	of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);

	return 0;
}
device_initcall(pasemi_publish_devices);


/*
 * Called very early, MMU is off, device-tree isn't unflattened
 */
static int __init pas_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	if (!of_flat_dt_is_compatible(root, "PA6T-1682M") &&
	    !of_flat_dt_is_compatible(root, "pasemi,pwrficient"))
		return 0;

	hpte_init_native();

	alloc_iobmap_l2();

	return 1;
}

define_machine(pasemi) {
	.name			= "PA Semi PWRficient",
	.probe			= pas_probe,
	.setup_arch		= pas_setup_arch,
	.init_early		= pas_init_early,
	.init_IRQ		= pas_init_IRQ,
	.get_irq		= mpic_get_irq,
	.restart		= pas_restart,
	.get_boot_time		= pas_get_boot_time,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= pas_progress,
	.machine_check_exception = pas_machine_check_handler,
};
Commit	Line	Data
1e76875e	1	/*
31c56d82	2	* Copyright (C) 2006-2007 PA Semi, Inc
1e76875e OJ	3	*
	4	* Authors: Kip Walker, PA Semi
	5	* Olof Johansson, PA Semi
	6	*
	7	* Maintained by: Olof Johansson <olof@lixom.net>
	8	*
	9	* Based on arch/powerpc/platforms/maple/setup.c
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*/
	24
1e76875e OJ	25	#include <linux/errno.h>
	26	#include <linux/kernel.h>
	27	#include <linux/delay.h>
	28	#include <linux/console.h>
12d04eef	29	#include <linux/pci.h>
5f867dc7	30	#include <linux/of_platform.h>
1e76875e OJ	31
	32	#include <asm/prom.h>
	33	#include <asm/system.h>
	34	#include <asm/iommu.h>
	35	#include <asm/machdep.h>
	36	#include <asm/mpic.h>
	37	#include <asm/smp.h>
	38	#include <asm/time.h>
584f8b71	39	#include <asm/mmu.h>
1e76875e	40
2b571a06 OJ	41	#include <pcmcia/ss.h>
	42	#include <pcmcia/cistpl.h>
	43	#include <pcmcia/ds.h>
	44
1e76875e OJ	45	#include "pasemi.h"
1e76875e OJ	46
32e2b55e OJ	47	#if !defined(CONFIG_SMP)
	48	static void smp_send_stop(void) {}
	49	#endif
	50
cd783416	51	/* SDC reset register, must be pre-mapped at reset time */
f620be99	52	static void __iomem *reset_reg;
1e76875e	53
cd783416 OJ	54	/* Various error status registers, must be pre-mapped at MCE time */
	55
	56	#define MAX_MCE_REGS 32
	57	struct mce_regs {
	58	char *name;
	59	void __iomem *addr;
	60	};
	61
	62	static struct mce_regs mce_regs[MAX_MCE_REGS];
	63	static int num_mce_regs;
	64
	65
f620be99	66	static void pas_restart(char *cmd)
1e76875e	67	{
32e2b55e OJ	68	/* Need to put others cpu in hold loop so they're not sleeping */
	69	smp_send_stop();
	70	udelay(10000);
f620be99 OJ	71	printk("Restarting...\n");
	72	while (1)
	73	out_le32(reset_reg, 0x6000000);
1e76875e OJ	74	}
	75
	76	#ifdef CONFIG_SMP
c388cfeb	77	static DEFINE_SPINLOCK(timebase_lock);
dc559f7c	78	static unsigned long timebase;
c388cfeb OJ	79
	80	static void __devinit pas_give_timebase(void)
	81	{
c388cfeb OJ	82	spin_lock(&timebase_lock);
c388cfeb OJ	83	mtspr(SPRN_TBCTL, TBCTL_FREEZE);
dc559f7c OJ	84	isync();
dc559f7c OJ	85	timebase = get_tb();
c388cfeb	86	spin_unlock(&timebase_lock);
dc559f7c OJ	87
	88	while (timebase)
	89	barrier();
	90	mtspr(SPRN_TBCTL, TBCTL_RESTART);
c388cfeb OJ	91	}
	92
	93	static void __devinit pas_take_timebase(void)
	94	{
dc559f7c OJ	95	while (!timebase)
	96	smp_rmb();
	97
	98	spin_lock(&timebase_lock);
	99	set_tb(timebase >> 32, timebase & 0xffffffff);
	100	timebase = 0;
	101	spin_unlock(&timebase_lock);
c388cfeb OJ	102	}
c388cfeb OJ	103
1e76875e OJ	104	struct smp_ops_t pas_smp_ops = {
	105	.probe = smp_mpic_probe,
	106	.message_pass = smp_mpic_message_pass,
	107	.kick_cpu = smp_generic_kick_cpu,
	108	.setup_cpu = smp_mpic_setup_cpu,
c388cfeb OJ	109	.give_timebase = pas_give_timebase,
c388cfeb OJ	110	.take_timebase = pas_take_timebase,
1e76875e OJ	111	};
	112	#endif /* CONFIG_SMP */
	113
	114	void __init pas_setup_arch(void)
	115	{
	116	#ifdef CONFIG_SMP
	117	/* Setup SMP callback */
	118	smp_ops = &pas_smp_ops;
	119	#endif
	120	/* Lookup PCI hosts */
	121	pas_pci_init();
	122
	123	#ifdef CONFIG_DUMMY_CONSOLE
	124	conswitchp = &dummy_con;
	125	#endif
	126
f620be99 OJ	127	/* Remap SDC register for doing reset */
	128	/* XXXOJN This should maybe come out of the device tree */
	129	reset_reg = ioremap(0xfc101100, 4);
1e76875e OJ	130	}
1e76875e OJ	131
cd783416 OJ	132	static int __init pas_setup_mce_regs(void)
	133	{
	134	struct pci_dev *dev;
	135	int reg;
	136
	137	if (!machine_is(pasemi))
	138	return -ENODEV;
	139
	140	/* Remap various SoC status registers for use by the MCE handler */
	141
	142	reg = 0;
	143
	144	dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
	145	while (dev && reg < MAX_MCE_REGS) {
	146	mce_regs[reg].name = kasprintf(GFP_KERNEL,
	147	"mc%d_mcdebug_errsta", reg);
	148	mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
	149	dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
	150	reg++;
	151	}
	152
	153	dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
	154	if (dev && reg+4 < MAX_MCE_REGS) {
	155	mce_regs[reg].name = "iobdbg_IntStatus1";
	156	mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
	157	reg++;
	158	mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
	159	mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
	160	reg++;
	161	mce_regs[reg].name = "iobiom_IntStatus";
	162	mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
	163	reg++;
	164	mce_regs[reg].name = "iobiom_IntDbgReg";
	165	mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
	166	reg++;
	167	}
	168
	169	dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
	170	if (dev && reg+2 < MAX_MCE_REGS) {
	171	mce_regs[reg].name = "l2csts_IntStatus";
	172	mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
	173	reg++;
	174	mce_regs[reg].name = "l2csts_Cnt";
	175	mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
	176	reg++;
	177	}
	178
	179	num_mce_regs = reg;
	180
	181	return 0;
	182	}
	183	device_initcall(pas_setup_mce_regs);
	184
1e76875e OJ	185	static __init void pas_init_IRQ(void)
	186	{
	187	struct device_node *np;
	188	struct device_node root, mpic_node;
	189	unsigned long openpic_addr;
	190	const unsigned int *opprop;
	191	int naddr, opplen;
	192	struct mpic *mpic;
	193
	194	mpic_node = NULL;
	195
	196	for_each_node_by_type(np, "interrupt-controller")
55b61fec	197	if (of_device_is_compatible(np, "open-pic")) {
1e76875e OJ	198	mpic_node = np;
	199	break;
	200	}
	201	if (!mpic_node)
	202	for_each_node_by_type(np, "open-pic") {
	203	mpic_node = np;
	204	break;
	205	}
	206	if (!mpic_node) {
	207	printk(KERN_ERR
	208	"Failed to locate the MPIC interrupt controller\n");
	209	return;
	210	}
	211
	212	/* Find address list in /platform-open-pic */
	213	root = of_find_node_by_path("/");
a8bda5dd	214	naddr = of_n_addr_cells(root);
e2eb6392	215	opprop = of_get_property(root, "platform-open-pic", &opplen);
1e76875e OJ	216	if (!opprop) {
	217	printk(KERN_ERR "No platform-open-pic property.\n");
	218	of_node_put(root);
	219	return;
	220	}
	221	openpic_addr = of_read_number(opprop, naddr);
	222	printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
1e76875e	223
7df2457d	224	mpic = mpic_alloc(mpic_node, openpic_addr,
de0c74e7	225	MPIC_PRIMARY\|MPIC_LARGE_VECTORS,
38958dd9	226	0, 0, "PASEMI-OPIC");
1e76875e OJ	227	BUG_ON(!mpic);
	228
	229	mpic_assign_isu(mpic, 0, openpic_addr + 0x10000);
	230	mpic_init(mpic);
	231	of_node_put(mpic_node);
	232	of_node_put(root);
	233	}
	234
	235	static void __init pas_progress(char *s, unsigned short hex)
	236	{
	237	printk("[%04x] : %s\n", hex, s ? s : "");
	238	}
	239
	240
bfed9d32 OJ	241	static int pas_machine_check_handler(struct pt_regs *regs)
	242	{
	243	int cpu = smp_processor_id();
	244	unsigned long srr0, srr1, dsisr;
cd783416 OJ	245	int dump_slb = 0;
cd783416 OJ	246	int i;
bfed9d32 OJ	247
	248	srr0 = regs->nip;
	249	srr1 = regs->msr;
	250	dsisr = mfspr(SPRN_DSISR);
	251	printk(KERN_ERR "Machine Check on CPU %d\n", cpu);
cd783416 OJ	252	printk(KERN_ERR "SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1);
	253	printk(KERN_ERR "DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar);
	254	printk(KERN_ERR "BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER),
	255	mfspr(SPRN_PA6T_MER));
	256	printk(KERN_ERR "IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER),
	257	mfspr(SPRN_PA6T_DER));
bfed9d32 OJ	258	printk(KERN_ERR "Cause:\n");
	259
	260	if (srr1 & 0x200000)
	261	printk(KERN_ERR "Signalled by SDC\n");
cd783416	262
bfed9d32 OJ	263	if (srr1 & 0x100000) {
	264	printk(KERN_ERR "Load/Store detected error:\n");
	265	if (dsisr & 0x8000)
	266	printk(KERN_ERR "D-cache ECC double-bit error or bus error\n");
	267	if (dsisr & 0x4000)
	268	printk(KERN_ERR "LSU snoop response error\n");
cd783416	269	if (dsisr & 0x2000) {
bfed9d32	270	printk(KERN_ERR "MMU SLB multi-hit or invalid B field\n");
cd783416 OJ	271	dump_slb = 1;
cd783416 OJ	272	}
bfed9d32 OJ	273	if (dsisr & 0x1000)
	274	printk(KERN_ERR "Recoverable Duptags\n");
	275	if (dsisr & 0x800)
	276	printk(KERN_ERR "Recoverable D-cache parity error count overflow\n");
	277	if (dsisr & 0x400)
	278	printk(KERN_ERR "TLB parity error count overflow\n");
	279	}
cd783416	280
bfed9d32 OJ	281	if (srr1 & 0x80000)
bfed9d32 OJ	282	printk(KERN_ERR "Bus Error\n");
cd783416 OJ	283
cd783416 OJ	284	if (srr1 & 0x40000) {
bfed9d32	285	printk(KERN_ERR "I-side SLB multiple hit\n");
cd783416 OJ	286	dump_slb = 1;
	287	}
	288
bfed9d32 OJ	289	if (srr1 & 0x20000)
	290	printk(KERN_ERR "I-cache parity error hit\n");
	291
cd783416 OJ	292	if (num_mce_regs == 0)
	293	printk(KERN_ERR "No MCE registers mapped yet, can't dump\n");
	294	else
	295	printk(KERN_ERR "SoC debug registers:\n");
	296
	297	for (i = 0; i < num_mce_regs; i++)
	298	printk(KERN_ERR "%s: 0x%08x\n", mce_regs[i].name,
	299	in_le32(mce_regs[i].addr));
	300
	301	if (dump_slb) {
	302	unsigned long e, v;
	303	int i;
	304
	305	printk(KERN_ERR "slb contents:\n");
584f8b71	306	for (i = 0; i < mmu_slb_size; i++) {
cd783416 OJ	307	asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i));
	308	asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i));
	309	printk(KERN_ERR "%02d %016lx %016lx\n", i, e, v);
	310	}
	311	}
	312
	313
bfed9d32 OJ	314	/* SRR1[62] is from MSR[62] if recoverable, so pass that back */
	315	return !!(srr1 & 0x2);
	316	}
	317
31c56d82 OJ	318	static void __init pas_init_early(void)
	319	{
	320	iommu_init_early_pasemi();
	321	}
	322
2b571a06 OJ	323	#ifdef CONFIG_PCMCIA
	324	static int pcmcia_notify(struct notifier_block *nb, unsigned long action,
	325	void *data)
	326	{
	327	struct device *dev = data;
	328	struct device *parent;
	329	struct pcmcia_device *pdev = to_pcmcia_dev(dev);
	330
	331	/* We are only intereted in device addition */
	332	if (action != BUS_NOTIFY_ADD_DEVICE)
	333	return 0;
	334
	335	parent = pdev->socket->dev.parent;
	336
	337	/* We know electra_cf devices will always have of_node set, since
	338	* electra_cf is an of_platform driver.
	339	*/
	340	if (!parent->archdata.of_node)
	341	return 0;
	342
	343	if (!of_device_is_compatible(parent->archdata.of_node, "electra-cf"))
	344	return 0;
	345
	346	/* We use the direct ops for localbus */
	347	dev->archdata.dma_ops = &dma_direct_ops;
	348
	349	return 0;
	350	}
	351
	352	static struct notifier_block pcmcia_notifier = {
	353	.notifier_call = pcmcia_notify,
	354	};
	355
	356	static inline void pasemi_pcmcia_init(void)
	357	{
	358	extern struct bus_type pcmcia_bus_type;
	359
	360	bus_register_notifier(&pcmcia_bus_type, &pcmcia_notifier);
	361	}
	362
	363	#else
	364
	365	static inline void pasemi_pcmcia_init(void)
	366	{
	367	}
	368
	369	#endif
	370
	371
b97d2791	372	static struct of_device_id pasemi_bus_ids[] = {
0d08a847	373	/* Unfortunately needed for legacy firmwares */
2b571a06	374	{ .type = "localbus", },
b97d2791	375	{ .type = "sdc", },
0d08a847 OJ	376	/* These are the proper entries, which newer firmware uses */
	377	{ .compatible = "pasemi,localbus", },
	378	{ .compatible = "pasemi,sdc", },
b97d2791 OJ	379	{},
	380	};
	381
	382	static int __init pasemi_publish_devices(void)
	383	{
90f7afef OJ	384	if (!machine_is(pasemi))
	385	return 0;
	386
2b571a06 OJ	387	pasemi_pcmcia_init();
2b571a06 OJ	388
90f7afef	389	/* Publish OF platform devices for SDC and other non-PCI devices */
b97d2791 OJ	390	of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);
	391
	392	return 0;
	393	}
	394	device_initcall(pasemi_publish_devices);
	395
bfed9d32	396
1e76875e OJ	397	/*
	398	* Called very early, MMU is off, device-tree isn't unflattened
	399	*/
	400	static int __init pas_probe(void)
	401	{
	402	unsigned long root = of_get_flat_dt_root();
	403
0d08a847 OJ	404	if (!of_flat_dt_is_compatible(root, "PA6T-1682M") &&
0d08a847 OJ	405	!of_flat_dt_is_compatible(root, "pasemi,pwrficient"))
1e76875e OJ	406	return 0;
	407
	408	hpte_init_native();
	409
31c56d82 OJ	410	alloc_iobmap_l2();
31c56d82 OJ	411
1e76875e OJ	412	return 1;
	413	}
	414
d4875a21	415	define_machine(pasemi) {
0d08a847	416	.name = "PA Semi PWRficient",
1e76875e OJ	417	.probe = pas_probe,
1e76875e OJ	418	.setup_arch = pas_setup_arch,
31c56d82	419	.init_early = pas_init_early,
1e76875e OJ	420	.init_IRQ = pas_init_IRQ,
1e76875e OJ	421	.get_irq = mpic_get_irq,
1e76875e	422	.restart = pas_restart,
1e76875e OJ	423	.get_boot_time = pas_get_boot_time,
1e76875e OJ	424	.calibrate_decr = generic_calibrate_decr,
1e76875e	425	.progress = pas_progress,
bfed9d32	426	.machine_check_exception = pas_machine_check_handler,
1e76875e	427	};