Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org) |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * Todo: - add support for the OF persistent properties | |
10 | */ | |
14cf11af PM |
11 | #include <linux/module.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/stddef.h> | |
14 | #include <linux/string.h> | |
15 | #include <linux/nvram.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/errno.h> | |
20 | #include <linux/adb.h> | |
21 | #include <linux/pmu.h> | |
22 | #include <linux/bootmem.h> | |
23 | #include <linux/completion.h> | |
24 | #include <linux/spinlock.h> | |
25 | #include <asm/sections.h> | |
26 | #include <asm/io.h> | |
27 | #include <asm/system.h> | |
28 | #include <asm/prom.h> | |
29 | #include <asm/machdep.h> | |
30 | #include <asm/nvram.h> | |
31 | ||
0ebfff14 BH |
32 | #include "pmac.h" |
33 | ||
14cf11af PM |
34 | #define DEBUG |
35 | ||
36 | #ifdef DEBUG | |
37 | #define DBG(x...) printk(x) | |
38 | #else | |
39 | #define DBG(x...) | |
40 | #endif | |
41 | ||
42 | #define NVRAM_SIZE 0x2000 /* 8kB of non-volatile RAM */ | |
43 | ||
44 | #define CORE99_SIGNATURE 0x5a | |
45 | #define CORE99_ADLER_START 0x14 | |
46 | ||
47 | /* On Core99, nvram is either a sharp, a micron or an AMD flash */ | |
48 | #define SM_FLASH_STATUS_DONE 0x80 | |
35499c01 PM |
49 | #define SM_FLASH_STATUS_ERR 0x38 |
50 | ||
14cf11af PM |
51 | #define SM_FLASH_CMD_ERASE_CONFIRM 0xd0 |
52 | #define SM_FLASH_CMD_ERASE_SETUP 0x20 | |
53 | #define SM_FLASH_CMD_RESET 0xff | |
54 | #define SM_FLASH_CMD_WRITE_SETUP 0x40 | |
55 | #define SM_FLASH_CMD_CLEAR_STATUS 0x50 | |
56 | #define SM_FLASH_CMD_READ_STATUS 0x70 | |
57 | ||
58 | /* CHRP NVRAM header */ | |
59 | struct chrp_header { | |
60 | u8 signature; | |
61 | u8 cksum; | |
62 | u16 len; | |
63 | char name[12]; | |
64 | u8 data[0]; | |
65 | }; | |
66 | ||
67 | struct core99_header { | |
68 | struct chrp_header hdr; | |
69 | u32 adler; | |
70 | u32 generation; | |
71 | u32 reserved[2]; | |
72 | }; | |
73 | ||
74 | /* | |
75 | * Read and write the non-volatile RAM on PowerMacs and CHRP machines. | |
76 | */ | |
77 | static int nvram_naddrs; | |
af308377 | 78 | static volatile unsigned char __iomem *nvram_data; |
35499c01 | 79 | static int is_core_99; |
14cf11af PM |
80 | static int core99_bank = 0; |
81 | static int nvram_partitions[3]; | |
35499c01 | 82 | // XXX Turn that into a sem |
14cf11af PM |
83 | static DEFINE_SPINLOCK(nv_lock); |
84 | ||
14cf11af PM |
85 | static int (*core99_write_bank)(int bank, u8* datas); |
86 | static int (*core99_erase_bank)(int bank); | |
87 | ||
88 | static char *nvram_image; | |
89 | ||
90 | ||
91 | static unsigned char core99_nvram_read_byte(int addr) | |
92 | { | |
93 | if (nvram_image == NULL) | |
94 | return 0xff; | |
95 | return nvram_image[addr]; | |
96 | } | |
97 | ||
98 | static void core99_nvram_write_byte(int addr, unsigned char val) | |
99 | { | |
100 | if (nvram_image == NULL) | |
101 | return; | |
102 | nvram_image[addr] = val; | |
103 | } | |
104 | ||
35499c01 PM |
105 | static ssize_t core99_nvram_read(char *buf, size_t count, loff_t *index) |
106 | { | |
107 | int i; | |
108 | ||
109 | if (nvram_image == NULL) | |
110 | return -ENODEV; | |
111 | if (*index > NVRAM_SIZE) | |
112 | return 0; | |
113 | ||
114 | i = *index; | |
115 | if (i + count > NVRAM_SIZE) | |
116 | count = NVRAM_SIZE - i; | |
117 | ||
118 | memcpy(buf, &nvram_image[i], count); | |
119 | *index = i + count; | |
120 | return count; | |
121 | } | |
122 | ||
123 | static ssize_t core99_nvram_write(char *buf, size_t count, loff_t *index) | |
124 | { | |
125 | int i; | |
126 | ||
127 | if (nvram_image == NULL) | |
128 | return -ENODEV; | |
129 | if (*index > NVRAM_SIZE) | |
130 | return 0; | |
131 | ||
132 | i = *index; | |
133 | if (i + count > NVRAM_SIZE) | |
134 | count = NVRAM_SIZE - i; | |
135 | ||
136 | memcpy(&nvram_image[i], buf, count); | |
137 | *index = i + count; | |
138 | return count; | |
139 | } | |
140 | ||
141 | static ssize_t core99_nvram_size(void) | |
142 | { | |
143 | if (nvram_image == NULL) | |
144 | return -ENODEV; | |
145 | return NVRAM_SIZE; | |
146 | } | |
147 | ||
148 | #ifdef CONFIG_PPC32 | |
af308377 | 149 | static volatile unsigned char __iomem *nvram_addr; |
35499c01 | 150 | static int nvram_mult; |
14cf11af PM |
151 | |
152 | static unsigned char direct_nvram_read_byte(int addr) | |
153 | { | |
154 | return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]); | |
155 | } | |
156 | ||
157 | static void direct_nvram_write_byte(int addr, unsigned char val) | |
158 | { | |
159 | out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val); | |
160 | } | |
161 | ||
162 | ||
163 | static unsigned char indirect_nvram_read_byte(int addr) | |
164 | { | |
165 | unsigned char val; | |
166 | unsigned long flags; | |
167 | ||
168 | spin_lock_irqsave(&nv_lock, flags); | |
169 | out_8(nvram_addr, addr >> 5); | |
170 | val = in_8(&nvram_data[(addr & 0x1f) << 4]); | |
171 | spin_unlock_irqrestore(&nv_lock, flags); | |
172 | ||
173 | return val; | |
174 | } | |
175 | ||
176 | static void indirect_nvram_write_byte(int addr, unsigned char val) | |
177 | { | |
178 | unsigned long flags; | |
179 | ||
180 | spin_lock_irqsave(&nv_lock, flags); | |
181 | out_8(nvram_addr, addr >> 5); | |
182 | out_8(&nvram_data[(addr & 0x1f) << 4], val); | |
183 | spin_unlock_irqrestore(&nv_lock, flags); | |
184 | } | |
185 | ||
186 | ||
187 | #ifdef CONFIG_ADB_PMU | |
188 | ||
189 | static void pmu_nvram_complete(struct adb_request *req) | |
190 | { | |
191 | if (req->arg) | |
192 | complete((struct completion *)req->arg); | |
193 | } | |
194 | ||
195 | static unsigned char pmu_nvram_read_byte(int addr) | |
196 | { | |
197 | struct adb_request req; | |
198 | DECLARE_COMPLETION(req_complete); | |
199 | ||
200 | req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL; | |
201 | if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM, | |
202 | (addr >> 8) & 0xff, addr & 0xff)) | |
203 | return 0xff; | |
204 | if (system_state == SYSTEM_RUNNING) | |
205 | wait_for_completion(&req_complete); | |
206 | while (!req.complete) | |
207 | pmu_poll(); | |
208 | return req.reply[0]; | |
209 | } | |
210 | ||
211 | static void pmu_nvram_write_byte(int addr, unsigned char val) | |
212 | { | |
213 | struct adb_request req; | |
214 | DECLARE_COMPLETION(req_complete); | |
215 | ||
216 | req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL; | |
217 | if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM, | |
218 | (addr >> 8) & 0xff, addr & 0xff, val)) | |
219 | return; | |
220 | if (system_state == SYSTEM_RUNNING) | |
221 | wait_for_completion(&req_complete); | |
222 | while (!req.complete) | |
223 | pmu_poll(); | |
224 | } | |
225 | ||
226 | #endif /* CONFIG_ADB_PMU */ | |
35499c01 | 227 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
228 | |
229 | static u8 chrp_checksum(struct chrp_header* hdr) | |
230 | { | |
231 | u8 *ptr; | |
232 | u16 sum = hdr->signature; | |
233 | for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++) | |
234 | sum += *ptr; | |
235 | while (sum > 0xFF) | |
236 | sum = (sum & 0xFF) + (sum>>8); | |
237 | return sum; | |
238 | } | |
239 | ||
240 | static u32 core99_calc_adler(u8 *buffer) | |
241 | { | |
242 | int cnt; | |
243 | u32 low, high; | |
244 | ||
245 | buffer += CORE99_ADLER_START; | |
246 | low = 1; | |
247 | high = 0; | |
248 | for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) { | |
249 | if ((cnt % 5000) == 0) { | |
250 | high %= 65521UL; | |
251 | high %= 65521UL; | |
252 | } | |
253 | low += buffer[cnt]; | |
254 | high += low; | |
255 | } | |
256 | low %= 65521UL; | |
257 | high %= 65521UL; | |
258 | ||
259 | return (high << 16) | low; | |
260 | } | |
261 | ||
262 | static u32 core99_check(u8* datas) | |
263 | { | |
264 | struct core99_header* hdr99 = (struct core99_header*)datas; | |
265 | ||
266 | if (hdr99->hdr.signature != CORE99_SIGNATURE) { | |
267 | DBG("Invalid signature\n"); | |
268 | return 0; | |
269 | } | |
270 | if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) { | |
271 | DBG("Invalid checksum\n"); | |
272 | return 0; | |
273 | } | |
274 | if (hdr99->adler != core99_calc_adler(datas)) { | |
275 | DBG("Invalid adler\n"); | |
276 | return 0; | |
277 | } | |
278 | return hdr99->generation; | |
279 | } | |
280 | ||
281 | static int sm_erase_bank(int bank) | |
282 | { | |
283 | int stat, i; | |
284 | unsigned long timeout; | |
285 | ||
af308377 | 286 | u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE; |
14cf11af PM |
287 | |
288 | DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank); | |
289 | ||
290 | out_8(base, SM_FLASH_CMD_ERASE_SETUP); | |
291 | out_8(base, SM_FLASH_CMD_ERASE_CONFIRM); | |
292 | timeout = 0; | |
293 | do { | |
294 | if (++timeout > 1000000) { | |
35499c01 | 295 | printk(KERN_ERR "nvram: Sharp/Micron flash erase timeout !\n"); |
14cf11af PM |
296 | break; |
297 | } | |
298 | out_8(base, SM_FLASH_CMD_READ_STATUS); | |
299 | stat = in_8(base); | |
300 | } while (!(stat & SM_FLASH_STATUS_DONE)); | |
301 | ||
302 | out_8(base, SM_FLASH_CMD_CLEAR_STATUS); | |
303 | out_8(base, SM_FLASH_CMD_RESET); | |
304 | ||
305 | for (i=0; i<NVRAM_SIZE; i++) | |
306 | if (base[i] != 0xff) { | |
307 | printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n"); | |
308 | return -ENXIO; | |
309 | } | |
310 | return 0; | |
311 | } | |
312 | ||
313 | static int sm_write_bank(int bank, u8* datas) | |
314 | { | |
315 | int i, stat = 0; | |
316 | unsigned long timeout; | |
317 | ||
af308377 | 318 | u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE; |
14cf11af PM |
319 | |
320 | DBG("nvram: Sharp/Micron Writing bank %d...\n", bank); | |
321 | ||
322 | for (i=0; i<NVRAM_SIZE; i++) { | |
323 | out_8(base+i, SM_FLASH_CMD_WRITE_SETUP); | |
324 | udelay(1); | |
325 | out_8(base+i, datas[i]); | |
326 | timeout = 0; | |
327 | do { | |
328 | if (++timeout > 1000000) { | |
329 | printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n"); | |
330 | break; | |
331 | } | |
332 | out_8(base, SM_FLASH_CMD_READ_STATUS); | |
333 | stat = in_8(base); | |
334 | } while (!(stat & SM_FLASH_STATUS_DONE)); | |
335 | if (!(stat & SM_FLASH_STATUS_DONE)) | |
336 | break; | |
337 | } | |
338 | out_8(base, SM_FLASH_CMD_CLEAR_STATUS); | |
339 | out_8(base, SM_FLASH_CMD_RESET); | |
340 | for (i=0; i<NVRAM_SIZE; i++) | |
341 | if (base[i] != datas[i]) { | |
342 | printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n"); | |
343 | return -ENXIO; | |
344 | } | |
345 | return 0; | |
346 | } | |
347 | ||
348 | static int amd_erase_bank(int bank) | |
349 | { | |
350 | int i, stat = 0; | |
351 | unsigned long timeout; | |
352 | ||
af308377 | 353 | u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE; |
14cf11af PM |
354 | |
355 | DBG("nvram: AMD Erasing bank %d...\n", bank); | |
356 | ||
357 | /* Unlock 1 */ | |
358 | out_8(base+0x555, 0xaa); | |
359 | udelay(1); | |
360 | /* Unlock 2 */ | |
361 | out_8(base+0x2aa, 0x55); | |
362 | udelay(1); | |
363 | ||
364 | /* Sector-Erase */ | |
365 | out_8(base+0x555, 0x80); | |
366 | udelay(1); | |
367 | out_8(base+0x555, 0xaa); | |
368 | udelay(1); | |
369 | out_8(base+0x2aa, 0x55); | |
370 | udelay(1); | |
371 | out_8(base, 0x30); | |
372 | udelay(1); | |
373 | ||
374 | timeout = 0; | |
375 | do { | |
376 | if (++timeout > 1000000) { | |
377 | printk(KERN_ERR "nvram: AMD flash erase timeout !\n"); | |
378 | break; | |
379 | } | |
380 | stat = in_8(base) ^ in_8(base); | |
381 | } while (stat != 0); | |
382 | ||
383 | /* Reset */ | |
384 | out_8(base, 0xf0); | |
385 | udelay(1); | |
386 | ||
387 | for (i=0; i<NVRAM_SIZE; i++) | |
388 | if (base[i] != 0xff) { | |
389 | printk(KERN_ERR "nvram: AMD flash erase failed !\n"); | |
390 | return -ENXIO; | |
391 | } | |
392 | return 0; | |
393 | } | |
394 | ||
395 | static int amd_write_bank(int bank, u8* datas) | |
396 | { | |
397 | int i, stat = 0; | |
398 | unsigned long timeout; | |
399 | ||
af308377 | 400 | u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE; |
14cf11af PM |
401 | |
402 | DBG("nvram: AMD Writing bank %d...\n", bank); | |
403 | ||
404 | for (i=0; i<NVRAM_SIZE; i++) { | |
405 | /* Unlock 1 */ | |
406 | out_8(base+0x555, 0xaa); | |
407 | udelay(1); | |
408 | /* Unlock 2 */ | |
409 | out_8(base+0x2aa, 0x55); | |
410 | udelay(1); | |
411 | ||
412 | /* Write single word */ | |
413 | out_8(base+0x555, 0xa0); | |
414 | udelay(1); | |
415 | out_8(base+i, datas[i]); | |
416 | ||
417 | timeout = 0; | |
418 | do { | |
419 | if (++timeout > 1000000) { | |
420 | printk(KERN_ERR "nvram: AMD flash write timeout !\n"); | |
421 | break; | |
422 | } | |
423 | stat = in_8(base) ^ in_8(base); | |
424 | } while (stat != 0); | |
425 | if (stat != 0) | |
426 | break; | |
427 | } | |
428 | ||
429 | /* Reset */ | |
430 | out_8(base, 0xf0); | |
431 | udelay(1); | |
432 | ||
433 | for (i=0; i<NVRAM_SIZE; i++) | |
434 | if (base[i] != datas[i]) { | |
435 | printk(KERN_ERR "nvram: AMD flash write failed !\n"); | |
436 | return -ENXIO; | |
437 | } | |
438 | return 0; | |
439 | } | |
440 | ||
441 | static void __init lookup_partitions(void) | |
442 | { | |
443 | u8 buffer[17]; | |
444 | int i, offset; | |
445 | struct chrp_header* hdr; | |
446 | ||
447 | if (pmac_newworld) { | |
448 | nvram_partitions[pmac_nvram_OF] = -1; | |
449 | nvram_partitions[pmac_nvram_XPRAM] = -1; | |
450 | nvram_partitions[pmac_nvram_NR] = -1; | |
451 | hdr = (struct chrp_header *)buffer; | |
452 | ||
453 | offset = 0; | |
454 | buffer[16] = 0; | |
455 | do { | |
456 | for (i=0;i<16;i++) | |
35499c01 | 457 | buffer[i] = ppc_md.nvram_read_val(offset+i); |
14cf11af PM |
458 | if (!strcmp(hdr->name, "common")) |
459 | nvram_partitions[pmac_nvram_OF] = offset + 0x10; | |
460 | if (!strcmp(hdr->name, "APL,MacOS75")) { | |
461 | nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10; | |
462 | nvram_partitions[pmac_nvram_NR] = offset + 0x110; | |
463 | } | |
464 | offset += (hdr->len * 0x10); | |
465 | } while(offset < NVRAM_SIZE); | |
466 | } else { | |
467 | nvram_partitions[pmac_nvram_OF] = 0x1800; | |
468 | nvram_partitions[pmac_nvram_XPRAM] = 0x1300; | |
469 | nvram_partitions[pmac_nvram_NR] = 0x1400; | |
470 | } | |
471 | DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]); | |
472 | DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]); | |
473 | DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]); | |
474 | } | |
475 | ||
476 | static void core99_nvram_sync(void) | |
477 | { | |
478 | struct core99_header* hdr99; | |
479 | unsigned long flags; | |
480 | ||
481 | if (!is_core_99 || !nvram_data || !nvram_image) | |
482 | return; | |
483 | ||
484 | spin_lock_irqsave(&nv_lock, flags); | |
485 | if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE, | |
486 | NVRAM_SIZE)) | |
487 | goto bail; | |
488 | ||
489 | DBG("Updating nvram...\n"); | |
490 | ||
491 | hdr99 = (struct core99_header*)nvram_image; | |
492 | hdr99->generation++; | |
493 | hdr99->hdr.signature = CORE99_SIGNATURE; | |
494 | hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr); | |
495 | hdr99->adler = core99_calc_adler(nvram_image); | |
496 | core99_bank = core99_bank ? 0 : 1; | |
497 | if (core99_erase_bank) | |
498 | if (core99_erase_bank(core99_bank)) { | |
499 | printk("nvram: Error erasing bank %d\n", core99_bank); | |
500 | goto bail; | |
501 | } | |
502 | if (core99_write_bank) | |
503 | if (core99_write_bank(core99_bank, nvram_image)) | |
504 | printk("nvram: Error writing bank %d\n", core99_bank); | |
505 | bail: | |
506 | spin_unlock_irqrestore(&nv_lock, flags); | |
507 | ||
508 | #ifdef DEBUG | |
509 | mdelay(2000); | |
510 | #endif | |
511 | } | |
512 | ||
cc5d0189 | 513 | static int __init core99_nvram_setup(struct device_node *dp, unsigned long addr) |
35499c01 PM |
514 | { |
515 | int i; | |
516 | u32 gen_bank0, gen_bank1; | |
517 | ||
518 | if (nvram_naddrs < 1) { | |
519 | printk(KERN_ERR "nvram: no address\n"); | |
520 | return -EINVAL; | |
521 | } | |
522 | nvram_image = alloc_bootmem(NVRAM_SIZE); | |
523 | if (nvram_image == NULL) { | |
524 | printk(KERN_ERR "nvram: can't allocate ram image\n"); | |
525 | return -ENOMEM; | |
526 | } | |
cc5d0189 | 527 | nvram_data = ioremap(addr, NVRAM_SIZE*2); |
35499c01 PM |
528 | nvram_naddrs = 1; /* Make sure we get the correct case */ |
529 | ||
530 | DBG("nvram: Checking bank 0...\n"); | |
531 | ||
532 | gen_bank0 = core99_check((u8 *)nvram_data); | |
533 | gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE); | |
534 | core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0; | |
535 | ||
536 | DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1); | |
537 | DBG("nvram: Active bank is: %d\n", core99_bank); | |
538 | ||
539 | for (i=0; i<NVRAM_SIZE; i++) | |
540 | nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE]; | |
541 | ||
542 | ppc_md.nvram_read_val = core99_nvram_read_byte; | |
543 | ppc_md.nvram_write_val = core99_nvram_write_byte; | |
544 | ppc_md.nvram_read = core99_nvram_read; | |
545 | ppc_md.nvram_write = core99_nvram_write; | |
546 | ppc_md.nvram_size = core99_nvram_size; | |
547 | ppc_md.nvram_sync = core99_nvram_sync; | |
3d1229d6 | 548 | ppc_md.machine_shutdown = core99_nvram_sync; |
35499c01 PM |
549 | /* |
550 | * Maybe we could be smarter here though making an exclusive list | |
551 | * of known flash chips is a bit nasty as older OF didn't provide us | |
552 | * with a useful "compatible" entry. A solution would be to really | |
553 | * identify the chip using flash id commands and base ourselves on | |
554 | * a list of known chips IDs | |
555 | */ | |
556 | if (device_is_compatible(dp, "amd-0137")) { | |
557 | core99_erase_bank = amd_erase_bank; | |
558 | core99_write_bank = amd_write_bank; | |
559 | } else { | |
560 | core99_erase_bank = sm_erase_bank; | |
561 | core99_write_bank = sm_write_bank; | |
562 | } | |
563 | return 0; | |
564 | } | |
565 | ||
566 | int __init pmac_nvram_init(void) | |
14cf11af PM |
567 | { |
568 | struct device_node *dp; | |
cc5d0189 BH |
569 | struct resource r1, r2; |
570 | unsigned int s1 = 0, s2 = 0; | |
35499c01 | 571 | int err = 0; |
14cf11af PM |
572 | |
573 | nvram_naddrs = 0; | |
574 | ||
cc5d0189 | 575 | dp = of_find_node_by_name(NULL, "nvram"); |
14cf11af PM |
576 | if (dp == NULL) { |
577 | printk(KERN_ERR "Can't find NVRAM device\n"); | |
35499c01 | 578 | return -ENODEV; |
14cf11af | 579 | } |
cc5d0189 BH |
580 | |
581 | /* Try to obtain an address */ | |
582 | if (of_address_to_resource(dp, 0, &r1) == 0) { | |
583 | nvram_naddrs = 1; | |
584 | s1 = (r1.end - r1.start) + 1; | |
585 | if (of_address_to_resource(dp, 1, &r2) == 0) { | |
586 | nvram_naddrs = 2; | |
587 | s2 = (r2.end - r2.start) + 1; | |
588 | } | |
589 | } | |
590 | ||
14cf11af | 591 | is_core_99 = device_is_compatible(dp, "nvram,flash"); |
cc5d0189 BH |
592 | if (is_core_99) { |
593 | err = core99_nvram_setup(dp, r1.start); | |
594 | goto bail; | |
595 | } | |
596 | ||
35499c01 | 597 | #ifdef CONFIG_PPC32 |
e8222502 | 598 | if (machine_is(chrp) && nvram_naddrs == 1) { |
cc5d0189 | 599 | nvram_data = ioremap(r1.start, s1); |
14cf11af PM |
600 | nvram_mult = 1; |
601 | ppc_md.nvram_read_val = direct_nvram_read_byte; | |
602 | ppc_md.nvram_write_val = direct_nvram_write_byte; | |
603 | } else if (nvram_naddrs == 1) { | |
cc5d0189 BH |
604 | nvram_data = ioremap(r1.start, s1); |
605 | nvram_mult = (s1 + NVRAM_SIZE - 1) / NVRAM_SIZE; | |
14cf11af PM |
606 | ppc_md.nvram_read_val = direct_nvram_read_byte; |
607 | ppc_md.nvram_write_val = direct_nvram_write_byte; | |
608 | } else if (nvram_naddrs == 2) { | |
cc5d0189 BH |
609 | nvram_addr = ioremap(r1.start, s1); |
610 | nvram_data = ioremap(r2.start, s2); | |
14cf11af PM |
611 | ppc_md.nvram_read_val = indirect_nvram_read_byte; |
612 | ppc_md.nvram_write_val = indirect_nvram_write_byte; | |
613 | } else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) { | |
614 | #ifdef CONFIG_ADB_PMU | |
615 | nvram_naddrs = -1; | |
616 | ppc_md.nvram_read_val = pmu_nvram_read_byte; | |
617 | ppc_md.nvram_write_val = pmu_nvram_write_byte; | |
618 | #endif /* CONFIG_ADB_PMU */ | |
cc5d0189 | 619 | } else { |
35499c01 | 620 | printk(KERN_ERR "Incompatible type of NVRAM\n"); |
cc5d0189 | 621 | err = -ENXIO; |
14cf11af | 622 | } |
cc5d0189 BH |
623 | #endif /* CONFIG_PPC32 */ |
624 | bail: | |
625 | of_node_put(dp); | |
626 | if (err == 0) | |
627 | lookup_partitions(); | |
35499c01 | 628 | return err; |
14cf11af PM |
629 | } |
630 | ||
631 | int pmac_get_partition(int partition) | |
632 | { | |
633 | return nvram_partitions[partition]; | |
634 | } | |
635 | ||
636 | u8 pmac_xpram_read(int xpaddr) | |
637 | { | |
35499c01 | 638 | int offset = pmac_get_partition(pmac_nvram_XPRAM); |
14cf11af | 639 | |
35499c01 | 640 | if (offset < 0 || xpaddr < 0 || xpaddr > 0x100) |
14cf11af PM |
641 | return 0xff; |
642 | ||
643 | return ppc_md.nvram_read_val(xpaddr + offset); | |
644 | } | |
645 | ||
646 | void pmac_xpram_write(int xpaddr, u8 data) | |
647 | { | |
35499c01 | 648 | int offset = pmac_get_partition(pmac_nvram_XPRAM); |
14cf11af | 649 | |
35499c01 | 650 | if (offset < 0 || xpaddr < 0 || xpaddr > 0x100) |
14cf11af PM |
651 | return; |
652 | ||
653 | ppc_md.nvram_write_val(xpaddr + offset, data); | |
654 | } | |
655 | ||
656 | EXPORT_SYMBOL(pmac_get_partition); | |
657 | EXPORT_SYMBOL(pmac_xpram_read); | |
658 | EXPORT_SYMBOL(pmac_xpram_write); |