[deliverable/linux.git] / arch / powerpc / platforms / powermac / nvram.c

/*
 *  arch/ppc/platforms/pmac_nvram.c
 *
 *  Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 *  Todo: - add support for the OF persistent properties
 */
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/string.h>
#include <linux/nvram.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/adb.h>
#include <linux/pmu.h>
#include <linux/bootmem.h>
#include <linux/completion.h>
#include <linux/spinlock.h>
#include <asm/sections.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/nvram.h>

#define DEBUG

#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif

#define NVRAM_SIZE		0x2000	/* 8kB of non-volatile RAM */

#define CORE99_SIGNATURE	0x5a
#define CORE99_ADLER_START	0x14

/* On Core99, nvram is either a sharp, a micron or an AMD flash */
#define SM_FLASH_STATUS_DONE	0x80
#define SM_FLASH_STATUS_ERR	0x38

#define SM_FLASH_CMD_ERASE_CONFIRM	0xd0
#define SM_FLASH_CMD_ERASE_SETUP	0x20
#define SM_FLASH_CMD_RESET		0xff
#define SM_FLASH_CMD_WRITE_SETUP	0x40
#define SM_FLASH_CMD_CLEAR_STATUS	0x50
#define SM_FLASH_CMD_READ_STATUS	0x70

/* CHRP NVRAM header */
struct chrp_header {
  u8		signature;
  u8		cksum;
  u16		len;
  char          name[12];
  u8		data[0];
};

struct core99_header {
  struct chrp_header	hdr;
  u32			adler;
  u32			generation;
  u32			reserved[2];
};

/*
 * Read and write the non-volatile RAM on PowerMacs and CHRP machines.
 */
static int nvram_naddrs;
static volatile unsigned char *nvram_data;
static int is_core_99;
static int core99_bank = 0;
static int nvram_partitions[3];
// XXX Turn that into a sem
static DEFINE_SPINLOCK(nv_lock);

extern int pmac_newworld;
extern int system_running;

static int (*core99_write_bank)(int bank, u8* datas);
static int (*core99_erase_bank)(int bank);

static char *nvram_image;


static unsigned char core99_nvram_read_byte(int addr)
{
	if (nvram_image == NULL)
		return 0xff;
	return nvram_image[addr];
}

static void core99_nvram_write_byte(int addr, unsigned char val)
{
	if (nvram_image == NULL)
		return;
	nvram_image[addr] = val;
}

static ssize_t core99_nvram_read(char *buf, size_t count, loff_t *index)
{
	int i;

	if (nvram_image == NULL)
		return -ENODEV;
	if (*index > NVRAM_SIZE)
		return 0;

	i = *index;
	if (i + count > NVRAM_SIZE)
		count = NVRAM_SIZE - i;

	memcpy(buf, &nvram_image[i], count);
	*index = i + count;
	return count;
}

static ssize_t core99_nvram_write(char *buf, size_t count, loff_t *index)
{
	int i;

	if (nvram_image == NULL)
		return -ENODEV;
	if (*index > NVRAM_SIZE)
		return 0;

	i = *index;
	if (i + count > NVRAM_SIZE)
		count = NVRAM_SIZE - i;

	memcpy(&nvram_image[i], buf, count);
	*index = i + count;
	return count;
}

static ssize_t core99_nvram_size(void)
{
	if (nvram_image == NULL)
		return -ENODEV;
	return NVRAM_SIZE;
}

#ifdef CONFIG_PPC32
static volatile unsigned char *nvram_addr;
static int nvram_mult;

static unsigned char direct_nvram_read_byte(int addr)
{
	return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
}

static void direct_nvram_write_byte(int addr, unsigned char val)
{
	out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
}


static unsigned char indirect_nvram_read_byte(int addr)
{
	unsigned char val;
	unsigned long flags;

	spin_lock_irqsave(&nv_lock, flags);
	out_8(nvram_addr, addr >> 5);
	val = in_8(&nvram_data[(addr & 0x1f) << 4]);
	spin_unlock_irqrestore(&nv_lock, flags);

	return val;
}

static void indirect_nvram_write_byte(int addr, unsigned char val)
{
	unsigned long flags;

	spin_lock_irqsave(&nv_lock, flags);
	out_8(nvram_addr, addr >> 5);
	out_8(&nvram_data[(addr & 0x1f) << 4], val);
	spin_unlock_irqrestore(&nv_lock, flags);
}


#ifdef CONFIG_ADB_PMU

static void pmu_nvram_complete(struct adb_request *req)
{
	if (req->arg)
		complete((struct completion *)req->arg);
}

static unsigned char pmu_nvram_read_byte(int addr)
{
	struct adb_request req;
	DECLARE_COMPLETION(req_complete); 
	
	req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
	if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
			(addr >> 8) & 0xff, addr & 0xff))
		return 0xff;
	if (system_state == SYSTEM_RUNNING)
		wait_for_completion(&req_complete);
	while (!req.complete)
		pmu_poll();
	return req.reply[0];
}

static void pmu_nvram_write_byte(int addr, unsigned char val)
{
	struct adb_request req;
	DECLARE_COMPLETION(req_complete); 
	
	req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
	if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
			(addr >> 8) & 0xff, addr & 0xff, val))
		return;
	if (system_state == SYSTEM_RUNNING)
		wait_for_completion(&req_complete);
	while (!req.complete)
		pmu_poll();
}

#endif /* CONFIG_ADB_PMU */
#endif /* CONFIG_PPC32 */

static u8 chrp_checksum(struct chrp_header* hdr)
{
	u8 *ptr;
	u16 sum = hdr->signature;
	for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
		sum += *ptr;
	while (sum > 0xFF)
		sum = (sum & 0xFF) + (sum>>8);
	return sum;
}

static u32 core99_calc_adler(u8 *buffer)
{
	int cnt;
	u32 low, high;

   	buffer += CORE99_ADLER_START;
	low = 1;
	high = 0;
	for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
		if ((cnt % 5000) == 0) {
			high  %= 65521UL;
			high %= 65521UL;
		}
		low += buffer[cnt];
		high += low;
	}
	low  %= 65521UL;
	high %= 65521UL;

	return (high << 16) | low;
}

static u32 core99_check(u8* datas)
{
	struct core99_header* hdr99 = (struct core99_header*)datas;

	if (hdr99->hdr.signature != CORE99_SIGNATURE) {
		DBG("Invalid signature\n");
		return 0;
	}
	if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
		DBG("Invalid checksum\n");
		return 0;
	}
	if (hdr99->adler != core99_calc_adler(datas)) {
		DBG("Invalid adler\n");
		return 0;
	}
	return hdr99->generation;
}

static int sm_erase_bank(int bank)
{
	int stat, i;
	unsigned long timeout;

	u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;

       	DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);

	out_8(base, SM_FLASH_CMD_ERASE_SETUP);
	out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
	timeout = 0;
	do {
		if (++timeout > 1000000) {
			printk(KERN_ERR "nvram: Sharp/Micron flash erase timeout !\n");
			break;
		}
		out_8(base, SM_FLASH_CMD_READ_STATUS);
		stat = in_8(base);
	} while (!(stat & SM_FLASH_STATUS_DONE));

	out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
	out_8(base, SM_FLASH_CMD_RESET);

	for (i=0; i<NVRAM_SIZE; i++)
		if (base[i] != 0xff) {
			printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
			return -ENXIO;
		}
	return 0;
}

static int sm_write_bank(int bank, u8* datas)
{
	int i, stat = 0;
	unsigned long timeout;

	u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;

       	DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);

	for (i=0; i<NVRAM_SIZE; i++) {
		out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
		udelay(1);
		out_8(base+i, datas[i]);
		timeout = 0;
		do {
			if (++timeout > 1000000) {
				printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
				break;
			}
			out_8(base, SM_FLASH_CMD_READ_STATUS);
			stat = in_8(base);
		} while (!(stat & SM_FLASH_STATUS_DONE));
		if (!(stat & SM_FLASH_STATUS_DONE))
			break;
	}
	out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
	out_8(base, SM_FLASH_CMD_RESET);
	for (i=0; i<NVRAM_SIZE; i++)
		if (base[i] != datas[i]) {
			printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
			return -ENXIO;
		}
	return 0;
}

static int amd_erase_bank(int bank)
{
	int i, stat = 0;
	unsigned long timeout;

	u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;

       	DBG("nvram: AMD Erasing bank %d...\n", bank);

	/* Unlock 1 */
	out_8(base+0x555, 0xaa);
	udelay(1);
	/* Unlock 2 */
	out_8(base+0x2aa, 0x55);
	udelay(1);

	/* Sector-Erase */
	out_8(base+0x555, 0x80);
	udelay(1);
	out_8(base+0x555, 0xaa);
	udelay(1);
	out_8(base+0x2aa, 0x55);
	udelay(1);
	out_8(base, 0x30);
	udelay(1);

	timeout = 0;
	do {
		if (++timeout > 1000000) {
			printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
			break;
		}
		stat = in_8(base) ^ in_8(base);
	} while (stat != 0);
	
	/* Reset */
	out_8(base, 0xf0);
	udelay(1);
	
	for (i=0; i<NVRAM_SIZE; i++)
		if (base[i] != 0xff) {
			printk(KERN_ERR "nvram: AMD flash erase failed !\n");
			return -ENXIO;
		}
	return 0;
}

static int amd_write_bank(int bank, u8* datas)
{
	int i, stat = 0;
	unsigned long timeout;

	u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;

       	DBG("nvram: AMD Writing bank %d...\n", bank);

	for (i=0; i<NVRAM_SIZE; i++) {
		/* Unlock 1 */
		out_8(base+0x555, 0xaa);
		udelay(1);
		/* Unlock 2 */
		out_8(base+0x2aa, 0x55);
		udelay(1);

		/* Write single word */
		out_8(base+0x555, 0xa0);
		udelay(1);
		out_8(base+i, datas[i]);
		
		timeout = 0;
		do {
			if (++timeout > 1000000) {
				printk(KERN_ERR "nvram: AMD flash write timeout !\n");
				break;
			}
			stat = in_8(base) ^ in_8(base);
		} while (stat != 0);
		if (stat != 0)
			break;
	}

	/* Reset */
	out_8(base, 0xf0);
	udelay(1);

	for (i=0; i<NVRAM_SIZE; i++)
		if (base[i] != datas[i]) {
			printk(KERN_ERR "nvram: AMD flash write failed !\n");
			return -ENXIO;
		}
	return 0;
}

static void __init lookup_partitions(void)
{
	u8 buffer[17];
	int i, offset;
	struct chrp_header* hdr;

	if (pmac_newworld) {
		nvram_partitions[pmac_nvram_OF] = -1;
		nvram_partitions[pmac_nvram_XPRAM] = -1;
		nvram_partitions[pmac_nvram_NR] = -1;
		hdr = (struct chrp_header *)buffer;

		offset = 0;
		buffer[16] = 0;
		do {
			for (i=0;i<16;i++)
				buffer[i] = ppc_md.nvram_read_val(offset+i);
			if (!strcmp(hdr->name, "common"))
				nvram_partitions[pmac_nvram_OF] = offset + 0x10;
			if (!strcmp(hdr->name, "APL,MacOS75")) {
				nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
				nvram_partitions[pmac_nvram_NR] = offset + 0x110;
			}
			offset += (hdr->len * 0x10);
		} while(offset < NVRAM_SIZE);
	} else {
		nvram_partitions[pmac_nvram_OF] = 0x1800;
		nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
		nvram_partitions[pmac_nvram_NR] = 0x1400;
	}
	DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
	DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
	DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
}

static void core99_nvram_sync(void)
{
	struct core99_header* hdr99;
	unsigned long flags;

	if (!is_core_99 || !nvram_data || !nvram_image)
		return;

	spin_lock_irqsave(&nv_lock, flags);
	if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
		NVRAM_SIZE))
		goto bail;

	DBG("Updating nvram...\n");

	hdr99 = (struct core99_header*)nvram_image;
	hdr99->generation++;
	hdr99->hdr.signature = CORE99_SIGNATURE;
	hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
	hdr99->adler = core99_calc_adler(nvram_image);
	core99_bank = core99_bank ? 0 : 1;
	if (core99_erase_bank)
		if (core99_erase_bank(core99_bank)) {
			printk("nvram: Error erasing bank %d\n", core99_bank);
			goto bail;
		}
	if (core99_write_bank)
		if (core99_write_bank(core99_bank, nvram_image))
			printk("nvram: Error writing bank %d\n", core99_bank);
 bail:
	spin_unlock_irqrestore(&nv_lock, flags);

#ifdef DEBUG
       	mdelay(2000);
#endif
}

static int __init core99_nvram_setup(struct device_node *dp)
{
	int i;
	u32 gen_bank0, gen_bank1;

	if (nvram_naddrs < 1) {
		printk(KERN_ERR "nvram: no address\n");
		return -EINVAL;
	}
	nvram_image = alloc_bootmem(NVRAM_SIZE);
	if (nvram_image == NULL) {
		printk(KERN_ERR "nvram: can't allocate ram image\n");
		return -ENOMEM;
	}
	nvram_data = ioremap(dp->addrs[0].address, NVRAM_SIZE*2);
	nvram_naddrs = 1; /* Make sure we get the correct case */

	DBG("nvram: Checking bank 0...\n");

	gen_bank0 = core99_check((u8 *)nvram_data);
	gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
	core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;

	DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
	DBG("nvram: Active bank is: %d\n", core99_bank);

	for (i=0; i<NVRAM_SIZE; i++)
		nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];

	ppc_md.nvram_read_val	= core99_nvram_read_byte;
	ppc_md.nvram_write_val	= core99_nvram_write_byte;
	ppc_md.nvram_read	= core99_nvram_read;
	ppc_md.nvram_write	= core99_nvram_write;
	ppc_md.nvram_size	= core99_nvram_size;
	ppc_md.nvram_sync	= core99_nvram_sync;
	ppc_md.machine_shutdown	= core99_nvram_sync;
	/* 
	 * Maybe we could be smarter here though making an exclusive list
	 * of known flash chips is a bit nasty as older OF didn't provide us
	 * with a useful "compatible" entry. A solution would be to really
	 * identify the chip using flash id commands and base ourselves on
	 * a list of known chips IDs
	 */
	if (device_is_compatible(dp, "amd-0137")) {
		core99_erase_bank = amd_erase_bank;
		core99_write_bank = amd_write_bank;
	} else {
		core99_erase_bank = sm_erase_bank;
		core99_write_bank = sm_write_bank;
	}
	return 0;
}

int __init pmac_nvram_init(void)
{
	struct device_node *dp;
	int err = 0;

	nvram_naddrs = 0;

	dp = find_devices("nvram");
	if (dp == NULL) {
		printk(KERN_ERR "Can't find NVRAM device\n");
		return -ENODEV;
	}
	nvram_naddrs = dp->n_addrs;
	is_core_99 = device_is_compatible(dp, "nvram,flash");
	if (is_core_99)
		err = core99_nvram_setup(dp);
#ifdef CONFIG_PPC32
	else if (_machine == _MACH_chrp && nvram_naddrs == 1) {
		nvram_data = ioremap(dp->addrs[0].address + isa_mem_base,
				     dp->addrs[0].size);
		nvram_mult = 1;
		ppc_md.nvram_read_val	= direct_nvram_read_byte;
		ppc_md.nvram_write_val	= direct_nvram_write_byte;
	} else if (nvram_naddrs == 1) {
		nvram_data = ioremap(dp->addrs[0].address, dp->addrs[0].size);
		nvram_mult = (dp->addrs[0].size + NVRAM_SIZE - 1) / NVRAM_SIZE;
		ppc_md.nvram_read_val	= direct_nvram_read_byte;
		ppc_md.nvram_write_val	= direct_nvram_write_byte;
	} else if (nvram_naddrs == 2) {
		nvram_addr = ioremap(dp->addrs[0].address, dp->addrs[0].size);
		nvram_data = ioremap(dp->addrs[1].address, dp->addrs[1].size);
		ppc_md.nvram_read_val	= indirect_nvram_read_byte;
		ppc_md.nvram_write_val	= indirect_nvram_write_byte;
	} else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
#ifdef CONFIG_ADB_PMU
		nvram_naddrs = -1;
		ppc_md.nvram_read_val	= pmu_nvram_read_byte;
		ppc_md.nvram_write_val	= pmu_nvram_write_byte;
#endif /* CONFIG_ADB_PMU */
	}
#endif
	else {
		printk(KERN_ERR "Incompatible type of NVRAM\n");
		return -ENXIO;
	}
	lookup_partitions();
	return err;
}

int pmac_get_partition(int partition)
{
	return nvram_partitions[partition];
}

u8 pmac_xpram_read(int xpaddr)
{
	int offset = pmac_get_partition(pmac_nvram_XPRAM);

	if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
		return 0xff;

	return ppc_md.nvram_read_val(xpaddr + offset);
}

void pmac_xpram_write(int xpaddr, u8 data)
{
	int offset = pmac_get_partition(pmac_nvram_XPRAM);

	if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
		return;

	ppc_md.nvram_write_val(xpaddr + offset, data);
}

EXPORT_SYMBOL(pmac_get_partition);
EXPORT_SYMBOL(pmac_xpram_read);
EXPORT_SYMBOL(pmac_xpram_write);
Commit	Line	Data
14cf11af PM	1	/*
	2	* arch/ppc/platforms/pmac_nvram.c
	3	*
	4	* Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*
	11	* Todo: - add support for the OF persistent properties
	12	*/
	13	#include <linux/config.h>
	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/stddef.h>
	17	#include <linux/string.h>
	18	#include <linux/nvram.h>
	19	#include <linux/init.h>
	20	#include <linux/slab.h>
	21	#include <linux/delay.h>
	22	#include <linux/errno.h>
	23	#include <linux/adb.h>
	24	#include <linux/pmu.h>
	25	#include <linux/bootmem.h>
	26	#include <linux/completion.h>
	27	#include <linux/spinlock.h>
	28	#include <asm/sections.h>
	29	#include <asm/io.h>
	30	#include <asm/system.h>
	31	#include <asm/prom.h>
	32	#include <asm/machdep.h>
	33	#include <asm/nvram.h>
	34
	35	#define DEBUG
	36
	37	#ifdef DEBUG
	38	#define DBG(x...) printk(x)
	39	#else
	40	#define DBG(x...)
	41	#endif
	42
	43	#define NVRAM_SIZE 0x2000 /* 8kB of non-volatile RAM */
	44
	45	#define CORE99_SIGNATURE 0x5a
	46	#define CORE99_ADLER_START 0x14
	47
	48	/* On Core99, nvram is either a sharp, a micron or an AMD flash */
	49	#define SM_FLASH_STATUS_DONE 0x80
35499c01 PM	50	#define SM_FLASH_STATUS_ERR 0x38
35499c01 PM	51
14cf11af PM	52	#define SM_FLASH_CMD_ERASE_CONFIRM 0xd0
	53	#define SM_FLASH_CMD_ERASE_SETUP 0x20
	54	#define SM_FLASH_CMD_RESET 0xff
	55	#define SM_FLASH_CMD_WRITE_SETUP 0x40
	56	#define SM_FLASH_CMD_CLEAR_STATUS 0x50
	57	#define SM_FLASH_CMD_READ_STATUS 0x70
	58
	59	/* CHRP NVRAM header */
	60	struct chrp_header {
	61	u8 signature;
	62	u8 cksum;
	63	u16 len;
	64	char name[12];
	65	u8 data[0];
	66	};
	67
	68	struct core99_header {
	69	struct chrp_header hdr;
	70	u32 adler;
	71	u32 generation;
	72	u32 reserved[2];
	73	};
	74
	75	/*
	76	* Read and write the non-volatile RAM on PowerMacs and CHRP machines.
	77	*/
	78	static int nvram_naddrs;
14cf11af	79	static volatile unsigned char *nvram_data;
35499c01	80	static int is_core_99;
14cf11af PM	81	static int core99_bank = 0;
14cf11af PM	82	static int nvram_partitions[3];
35499c01	83	// XXX Turn that into a sem
14cf11af PM	84	static DEFINE_SPINLOCK(nv_lock);
	85
	86	extern int pmac_newworld;
	87	extern int system_running;
	88
	89	static int (core99_write_bank)(int bank, u8 datas);
	90	static int (*core99_erase_bank)(int bank);
	91
	92	static char *nvram_image;
	93
	94
	95	static unsigned char core99_nvram_read_byte(int addr)
	96	{
	97	if (nvram_image == NULL)
	98	return 0xff;
	99	return nvram_image[addr];
	100	}
	101
	102	static void core99_nvram_write_byte(int addr, unsigned char val)
	103	{
	104	if (nvram_image == NULL)
	105	return;
	106	nvram_image[addr] = val;
	107	}
	108
35499c01 PM	109	static ssize_t core99_nvram_read(char buf, size_t count, loff_t index)
	110	{
	111	int i;
	112
	113	if (nvram_image == NULL)
	114	return -ENODEV;
	115	if (*index > NVRAM_SIZE)
	116	return 0;
	117
	118	i = *index;
	119	if (i + count > NVRAM_SIZE)
	120	count = NVRAM_SIZE - i;
	121
	122	memcpy(buf, &nvram_image[i], count);
	123	*index = i + count;
	124	return count;
	125	}
	126
	127	static ssize_t core99_nvram_write(char buf, size_t count, loff_t index)
	128	{
	129	int i;
	130
	131	if (nvram_image == NULL)
	132	return -ENODEV;
	133	if (*index > NVRAM_SIZE)
	134	return 0;
	135
	136	i = *index;
	137	if (i + count > NVRAM_SIZE)
	138	count = NVRAM_SIZE - i;
	139
	140	memcpy(&nvram_image[i], buf, count);
	141	*index = i + count;
	142	return count;
	143	}
	144
	145	static ssize_t core99_nvram_size(void)
	146	{
	147	if (nvram_image == NULL)
	148	return -ENODEV;
	149	return NVRAM_SIZE;
	150	}
	151
	152	#ifdef CONFIG_PPC32
	153	static volatile unsigned char *nvram_addr;
	154	static int nvram_mult;
14cf11af PM	155
	156	static unsigned char direct_nvram_read_byte(int addr)
	157	{
	158	return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
	159	}
	160
	161	static void direct_nvram_write_byte(int addr, unsigned char val)
	162	{
	163	out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
	164	}
	165
	166
	167	static unsigned char indirect_nvram_read_byte(int addr)
	168	{
	169	unsigned char val;
	170	unsigned long flags;
	171
	172	spin_lock_irqsave(&nv_lock, flags);
	173	out_8(nvram_addr, addr >> 5);
	174	val = in_8(&nvram_data[(addr & 0x1f) << 4]);
	175	spin_unlock_irqrestore(&nv_lock, flags);
	176
	177	return val;
	178	}
	179
	180	static void indirect_nvram_write_byte(int addr, unsigned char val)
	181	{
	182	unsigned long flags;
	183
	184	spin_lock_irqsave(&nv_lock, flags);
	185	out_8(nvram_addr, addr >> 5);
	186	out_8(&nvram_data[(addr & 0x1f) << 4], val);
	187	spin_unlock_irqrestore(&nv_lock, flags);
	188	}
	189
	190
	191	#ifdef CONFIG_ADB_PMU
	192
	193	static void pmu_nvram_complete(struct adb_request *req)
	194	{
	195	if (req->arg)
	196	complete((struct completion *)req->arg);
	197	}
	198
	199	static unsigned char pmu_nvram_read_byte(int addr)
	200	{
	201	struct adb_request req;
	202	DECLARE_COMPLETION(req_complete);
	203
	204	req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
	205	if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
	206	(addr >> 8) & 0xff, addr & 0xff))
	207	return 0xff;
	208	if (system_state == SYSTEM_RUNNING)
	209	wait_for_completion(&req_complete);
	210	while (!req.complete)
	211	pmu_poll();
	212	return req.reply[0];
	213	}
	214
	215	static void pmu_nvram_write_byte(int addr, unsigned char val)
	216	{
	217	struct adb_request req;
	218	DECLARE_COMPLETION(req_complete);
219
220	req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
221	if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
222	(addr >> 8) & 0xff, addr & 0xff, val))
223	return;
224	if (system_state == SYSTEM_RUNNING)
225	wait_for_completion(&req_complete);
226	while (!req.complete)
227	pmu_poll();
228	}
229
230	#endif /* CONFIG_ADB_PMU */
35499c01	231	#endif /* CONFIG_PPC32 */
14cf11af PM	232
	233	static u8 chrp_checksum(struct chrp_header* hdr)
	234	{
	235	u8 *ptr;
	236	u16 sum = hdr->signature;
	237	for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
	238	sum += *ptr;
	239	while (sum > 0xFF)
	240	sum = (sum & 0xFF) + (sum>>8);
	241	return sum;
	242	}
	243
	244	static u32 core99_calc_adler(u8 *buffer)
	245	{
	246	int cnt;
	247	u32 low, high;
	248
	249	buffer += CORE99_ADLER_START;
	250	low = 1;
	251	high = 0;
	252	for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
	253	if ((cnt % 5000) == 0) {
	254	high %= 65521UL;
	255	high %= 65521UL;
	256	}
	257	low += buffer[cnt];
	258	high += low;
	259	}
	260	low %= 65521UL;
	261	high %= 65521UL;
	262
	263	return (high << 16) \| low;
	264	}
	265
	266	static u32 core99_check(u8* datas)
	267	{
	268	struct core99_header* hdr99 = (struct core99_header*)datas;
	269
	270	if (hdr99->hdr.signature != CORE99_SIGNATURE) {
	271	DBG("Invalid signature\n");
	272	return 0;
	273	}
	274	if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
	275	DBG("Invalid checksum\n");
	276	return 0;
	277	}
	278	if (hdr99->adler != core99_calc_adler(datas)) {
	279	DBG("Invalid adler\n");
	280	return 0;
	281	}
	282	return hdr99->generation;
	283	}
	284
	285	static int sm_erase_bank(int bank)
	286	{
	287	int stat, i;
	288	unsigned long timeout;
	289
	290	u8* base = (u8 )nvram_data + core99_bankNVRAM_SIZE;
	291
	292	DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
	293
	294	out_8(base, SM_FLASH_CMD_ERASE_SETUP);
	295	out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
296	timeout = 0;
297	do {
298	if (++timeout > 1000000) {
35499c01	299	printk(KERN_ERR "nvram: Sharp/Micron flash erase timeout !\n");
14cf11af PM	300	break;
	301	}
	302	out_8(base, SM_FLASH_CMD_READ_STATUS);
	303	stat = in_8(base);
	304	} while (!(stat & SM_FLASH_STATUS_DONE));
	305
	306	out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
	307	out_8(base, SM_FLASH_CMD_RESET);
	308
	309	for (i=0; i<NVRAM_SIZE; i++)
	310	if (base[i] != 0xff) {
	311	printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
	312	return -ENXIO;
	313	}
	314	return 0;
	315	}
	316
	317	static int sm_write_bank(int bank, u8* datas)
	318	{
	319	int i, stat = 0;
	320	unsigned long timeout;
	321
	322	u8* base = (u8 )nvram_data + core99_bankNVRAM_SIZE;
	323
	324	DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
	325
	326	for (i=0; i<NVRAM_SIZE; i++) {
	327	out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
	328	udelay(1);
	329	out_8(base+i, datas[i]);
	330	timeout = 0;
	331	do {
	332	if (++timeout > 1000000) {
	333	printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
	334	break;
	335	}
	336	out_8(base, SM_FLASH_CMD_READ_STATUS);
	337	stat = in_8(base);
	338	} while (!(stat & SM_FLASH_STATUS_DONE));
	339	if (!(stat & SM_FLASH_STATUS_DONE))
	340	break;
	341	}
	342	out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
	343	out_8(base, SM_FLASH_CMD_RESET);
	344	for (i=0; i<NVRAM_SIZE; i++)
	345	if (base[i] != datas[i]) {
	346	printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
	347	return -ENXIO;
	348	}
	349	return 0;
	350	}
	351
	352	static int amd_erase_bank(int bank)
	353	{
	354	int i, stat = 0;
	355	unsigned long timeout;
	356
	357	u8* base = (u8 )nvram_data + core99_bankNVRAM_SIZE;
	358
	359	DBG("nvram: AMD Erasing bank %d...\n", bank);
	360
	361	/* Unlock 1 */
	362	out_8(base+0x555, 0xaa);
	363	udelay(1);
364	/* Unlock 2 */
365	out_8(base+0x2aa, 0x55);
366	udelay(1);
367
368	/* Sector-Erase */
369	out_8(base+0x555, 0x80);
370	udelay(1);
371	out_8(base+0x555, 0xaa);
372	udelay(1);
373	out_8(base+0x2aa, 0x55);
374	udelay(1);
375	out_8(base, 0x30);
376	udelay(1);
377
378	timeout = 0;
379	do {
380	if (++timeout > 1000000) {
381	printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
382	break;
383	}
384	stat = in_8(base) ^ in_8(base);
385	} while (stat != 0);
386
387	/* Reset */
388	out_8(base, 0xf0);
389	udelay(1);
390
391	for (i=0; i<NVRAM_SIZE; i++)
392	if (base[i] != 0xff) {
393	printk(KERN_ERR "nvram: AMD flash erase failed !\n");
394	return -ENXIO;
395	}
396	return 0;
397	}
398
399	static int amd_write_bank(int bank, u8* datas)
400	{
401	int i, stat = 0;
402	unsigned long timeout;
403
404	u8* base = (u8 )nvram_data + core99_bankNVRAM_SIZE;
405
406	DBG("nvram: AMD Writing bank %d...\n", bank);
407
408	for (i=0; i<NVRAM_SIZE; i++) {
409	/* Unlock 1 */
410	out_8(base+0x555, 0xaa);
411	udelay(1);
412	/* Unlock 2 */
413	out_8(base+0x2aa, 0x55);
414	udelay(1);
415
416	/* Write single word */
417	out_8(base+0x555, 0xa0);
418	udelay(1);
419	out_8(base+i, datas[i]);
420
421	timeout = 0;
422	do {
423	if (++timeout > 1000000) {
424	printk(KERN_ERR "nvram: AMD flash write timeout !\n");
425	break;
426	}
427	stat = in_8(base) ^ in_8(base);
428	} while (stat != 0);
429	if (stat != 0)
430	break;
431	}
432
433	/* Reset */
434	out_8(base, 0xf0);
435	udelay(1);
436
437	for (i=0; i<NVRAM_SIZE; i++)
438	if (base[i] != datas[i]) {
439	printk(KERN_ERR "nvram: AMD flash write failed !\n");
440	return -ENXIO;
441	}
442	return 0;
443	}
444
445	static void __init lookup_partitions(void)
446	{
447	u8 buffer[17];
448	int i, offset;
449	struct chrp_header* hdr;
450
451	if (pmac_newworld) {
452	nvram_partitions[pmac_nvram_OF] = -1;
453	nvram_partitions[pmac_nvram_XPRAM] = -1;
454	nvram_partitions[pmac_nvram_NR] = -1;
455	hdr = (struct chrp_header *)buffer;
456
457	offset = 0;
458	buffer[16] = 0;
459	do {
460	for (i=0;i<16;i++)
35499c01	461	buffer[i] = ppc_md.nvram_read_val(offset+i);
14cf11af PM	462	if (!strcmp(hdr->name, "common"))
	463	nvram_partitions[pmac_nvram_OF] = offset + 0x10;
	464	if (!strcmp(hdr->name, "APL,MacOS75")) {
	465	nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
	466	nvram_partitions[pmac_nvram_NR] = offset + 0x110;
	467	}
	468	offset += (hdr->len * 0x10);
	469	} while(offset < NVRAM_SIZE);
	470	} else {
	471	nvram_partitions[pmac_nvram_OF] = 0x1800;
	472	nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
	473	nvram_partitions[pmac_nvram_NR] = 0x1400;
	474	}
	475	DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
	476	DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
	477	DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
	478	}
	479
	480	static void core99_nvram_sync(void)
	481	{
	482	struct core99_header* hdr99;
	483	unsigned long flags;
	484
	485	if (!is_core_99 \|\| !nvram_data \|\| !nvram_image)
	486	return;
	487
	488	spin_lock_irqsave(&nv_lock, flags);
	489	if (!memcmp(nvram_image, (u8)nvram_data + core99_bankNVRAM_SIZE,
	490	NVRAM_SIZE))
	491	goto bail;
	492
	493	DBG("Updating nvram...\n");
	494
	495	hdr99 = (struct core99_header*)nvram_image;
	496	hdr99->generation++;
	497	hdr99->hdr.signature = CORE99_SIGNATURE;
	498	hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
	499	hdr99->adler = core99_calc_adler(nvram_image);
	500	core99_bank = core99_bank ? 0 : 1;
	501	if (core99_erase_bank)
	502	if (core99_erase_bank(core99_bank)) {
	503	printk("nvram: Error erasing bank %d\n", core99_bank);
	504	goto bail;
	505	}
	506	if (core99_write_bank)
	507	if (core99_write_bank(core99_bank, nvram_image))
	508	printk("nvram: Error writing bank %d\n", core99_bank);
	509	bail:
	510	spin_unlock_irqrestore(&nv_lock, flags);
	511
	512	#ifdef DEBUG
	513	mdelay(2000);
	514	#endif
	515	}
	516
35499c01 PM	517	static int __init core99_nvram_setup(struct device_node *dp)
	518	{
	519	int i;
	520	u32 gen_bank0, gen_bank1;
	521
	522	if (nvram_naddrs < 1) {
	523	printk(KERN_ERR "nvram: no address\n");
	524	return -EINVAL;
	525	}
	526	nvram_image = alloc_bootmem(NVRAM_SIZE);
	527	if (nvram_image == NULL) {
	528	printk(KERN_ERR "nvram: can't allocate ram image\n");
	529	return -ENOMEM;
	530	}
	531	nvram_data = ioremap(dp->addrs[0].address, NVRAM_SIZE*2);
	532	nvram_naddrs = 1; /* Make sure we get the correct case */
	533
	534	DBG("nvram: Checking bank 0...\n");
	535
	536	gen_bank0 = core99_check((u8 *)nvram_data);
	537	gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
	538	core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;
	539
	540	DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
	541	DBG("nvram: Active bank is: %d\n", core99_bank);
	542
	543	for (i=0; i<NVRAM_SIZE; i++)
	544	nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];
	545
	546	ppc_md.nvram_read_val = core99_nvram_read_byte;
	547	ppc_md.nvram_write_val = core99_nvram_write_byte;
	548	ppc_md.nvram_read = core99_nvram_read;
	549	ppc_md.nvram_write = core99_nvram_write;
	550	ppc_md.nvram_size = core99_nvram_size;
	551	ppc_md.nvram_sync = core99_nvram_sync;
3d1229d6	552	ppc_md.machine_shutdown = core99_nvram_sync;
35499c01 PM	553	/*
	554	* Maybe we could be smarter here though making an exclusive list
	555	* of known flash chips is a bit nasty as older OF didn't provide us
	556	* with a useful "compatible" entry. A solution would be to really
	557	* identify the chip using flash id commands and base ourselves on
	558	* a list of known chips IDs
	559	*/
	560	if (device_is_compatible(dp, "amd-0137")) {
	561	core99_erase_bank = amd_erase_bank;
	562	core99_write_bank = amd_write_bank;
	563	} else {
	564	core99_erase_bank = sm_erase_bank;
	565	core99_write_bank = sm_write_bank;
	566	}
	567	return 0;
	568	}
	569
	570	int __init pmac_nvram_init(void)
14cf11af PM	571	{
14cf11af PM	572	struct device_node *dp;
35499c01	573	int err = 0;
14cf11af PM	574
	575	nvram_naddrs = 0;
	576
	577	dp = find_devices("nvram");
	578	if (dp == NULL) {
	579	printk(KERN_ERR "Can't find NVRAM device\n");
35499c01	580	return -ENODEV;
14cf11af PM	581	}
	582	nvram_naddrs = dp->n_addrs;
	583	is_core_99 = device_is_compatible(dp, "nvram,flash");
35499c01 PM	584	if (is_core_99)
	585	err = core99_nvram_setup(dp);
	586	#ifdef CONFIG_PPC32
	587	else if (_machine == _MACH_chrp && nvram_naddrs == 1) {
14cf11af PM	588	nvram_data = ioremap(dp->addrs[0].address + isa_mem_base,
	589	dp->addrs[0].size);
	590	nvram_mult = 1;
	591	ppc_md.nvram_read_val = direct_nvram_read_byte;
	592	ppc_md.nvram_write_val = direct_nvram_write_byte;
	593	} else if (nvram_naddrs == 1) {
	594	nvram_data = ioremap(dp->addrs[0].address, dp->addrs[0].size);
	595	nvram_mult = (dp->addrs[0].size + NVRAM_SIZE - 1) / NVRAM_SIZE;
	596	ppc_md.nvram_read_val = direct_nvram_read_byte;
	597	ppc_md.nvram_write_val = direct_nvram_write_byte;
	598	} else if (nvram_naddrs == 2) {
	599	nvram_addr = ioremap(dp->addrs[0].address, dp->addrs[0].size);
	600	nvram_data = ioremap(dp->addrs[1].address, dp->addrs[1].size);
	601	ppc_md.nvram_read_val = indirect_nvram_read_byte;
	602	ppc_md.nvram_write_val = indirect_nvram_write_byte;
	603	} else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
	604	#ifdef CONFIG_ADB_PMU
	605	nvram_naddrs = -1;
	606	ppc_md.nvram_read_val = pmu_nvram_read_byte;
	607	ppc_md.nvram_write_val = pmu_nvram_write_byte;
	608	#endif /* CONFIG_ADB_PMU */
35499c01 PM	609	}
	610	#endif
	611	else {
	612	printk(KERN_ERR "Incompatible type of NVRAM\n");
	613	return -ENXIO;
14cf11af PM	614	}
14cf11af PM	615	lookup_partitions();
35499c01	616	return err;
14cf11af PM	617	}
	618
	619	int pmac_get_partition(int partition)
	620	{
	621	return nvram_partitions[partition];
	622	}
	623
	624	u8 pmac_xpram_read(int xpaddr)
	625	{
35499c01	626	int offset = pmac_get_partition(pmac_nvram_XPRAM);
14cf11af	627
35499c01	628	if (offset < 0 \|\| xpaddr < 0 \|\| xpaddr > 0x100)
14cf11af PM	629	return 0xff;
	630
	631	return ppc_md.nvram_read_val(xpaddr + offset);
	632	}
	633
	634	void pmac_xpram_write(int xpaddr, u8 data)
	635	{
35499c01	636	int offset = pmac_get_partition(pmac_nvram_XPRAM);
14cf11af	637
35499c01	638	if (offset < 0 \|\| xpaddr < 0 \|\| xpaddr > 0x100)
14cf11af PM	639	return;
	640
	641	ppc_md.nvram_write_val(xpaddr + offset, data);
	642	}
	643
	644	EXPORT_SYMBOL(pmac_get_partition);
	645	EXPORT_SYMBOL(pmac_xpram_read);
	646	EXPORT_SYMBOL(pmac_xpram_write);