Commit | Line | Data |
---|---|---|
14cf11af PM |
1 | /* |
2 | * Support for PCI bridges found on Power Macintoshes. | |
14cf11af | 3 | * |
1beb6a7d | 4 | * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org) |
14cf11af PM |
5 | * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/string.h> | |
17 | #include <linux/init.h> | |
6e99e458 | 18 | #include <linux/irq.h> |
98d9f30c | 19 | #include <linux/of_pci.h> |
14cf11af PM |
20 | |
21 | #include <asm/sections.h> | |
22 | #include <asm/io.h> | |
23 | #include <asm/prom.h> | |
24 | #include <asm/pci-bridge.h> | |
25 | #include <asm/machdep.h> | |
26 | #include <asm/pmac_feature.h> | |
830825d6 | 27 | #include <asm/grackle.h> |
3c3f42d6 | 28 | #include <asm/ppc-pci.h> |
14cf11af | 29 | |
e63f26d3 DA |
30 | #include "pmac.h" |
31 | ||
14cf11af PM |
32 | #undef DEBUG |
33 | ||
34 | #ifdef DEBUG | |
35 | #define DBG(x...) printk(x) | |
36 | #else | |
37 | #define DBG(x...) | |
38 | #endif | |
39 | ||
14cf11af PM |
40 | /* XXX Could be per-controller, but I don't think we risk anything by |
41 | * assuming we won't have both UniNorth and Bandit */ | |
42 | static int has_uninorth; | |
35499c01 | 43 | #ifdef CONFIG_PPC64 |
14cf11af | 44 | static struct pci_controller *u3_agp; |
0ebfff14 BH |
45 | #else |
46 | static int has_second_ohare; | |
35499c01 | 47 | #endif /* CONFIG_PPC64 */ |
14cf11af | 48 | |
14cf11af PM |
49 | extern int pcibios_assign_bus_offset; |
50 | ||
51 | struct device_node *k2_skiplist[2]; | |
52 | ||
53 | /* | |
54 | * Magic constants for enabling cache coherency in the bandit/PSX bridge. | |
55 | */ | |
56 | #define BANDIT_DEVID_2 8 | |
57 | #define BANDIT_REVID 3 | |
58 | ||
59 | #define BANDIT_DEVNUM 11 | |
60 | #define BANDIT_MAGIC 0x50 | |
61 | #define BANDIT_COHERENT 0x40 | |
62 | ||
63 | static int __init fixup_one_level_bus_range(struct device_node *node, int higher) | |
64 | { | |
65 | for (; node != 0;node = node->sibling) { | |
018a3d1d JK |
66 | const int * bus_range; |
67 | const unsigned int *class_code; | |
14cf11af PM |
68 | int len; |
69 | ||
70 | /* For PCI<->PCI bridges or CardBus bridges, we go down */ | |
e2eb6392 | 71 | class_code = of_get_property(node, "class-code", NULL); |
14cf11af PM |
72 | if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && |
73 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) | |
74 | continue; | |
e2eb6392 | 75 | bus_range = of_get_property(node, "bus-range", &len); |
14cf11af PM |
76 | if (bus_range != NULL && len > 2 * sizeof(int)) { |
77 | if (bus_range[1] > higher) | |
78 | higher = bus_range[1]; | |
79 | } | |
80 | higher = fixup_one_level_bus_range(node->child, higher); | |
81 | } | |
82 | return higher; | |
83 | } | |
84 | ||
85 | /* This routine fixes the "bus-range" property of all bridges in the | |
86 | * system since they tend to have their "last" member wrong on macs | |
87 | * | |
88 | * Note that the bus numbers manipulated here are OF bus numbers, they | |
89 | * are not Linux bus numbers. | |
90 | */ | |
91 | static void __init fixup_bus_range(struct device_node *bridge) | |
92 | { | |
018a3d1d JK |
93 | int *bus_range, len; |
94 | struct property *prop; | |
14cf11af PM |
95 | |
96 | /* Lookup the "bus-range" property for the hose */ | |
018a3d1d JK |
97 | prop = of_find_property(bridge, "bus-range", &len); |
98 | if (prop == NULL || prop->length < 2 * sizeof(int)) | |
14cf11af | 99 | return; |
018a3d1d | 100 | |
1a38147e | 101 | bus_range = prop->value; |
14cf11af PM |
102 | bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); |
103 | } | |
104 | ||
105 | /* | |
106 | * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. | |
107 | * | |
108 | * The "Bandit" version is present in all early PCI PowerMacs, | |
109 | * and up to the first ones using Grackle. Some machines may | |
110 | * have 2 bandit controllers (2 PCI busses). | |
111 | * | |
112 | * "Chaos" is used in some "Bandit"-type machines as a bridge | |
113 | * for the separate display bus. It is accessed the same | |
114 | * way as bandit, but cannot be probed for devices. It therefore | |
115 | * has its own config access functions. | |
116 | * | |
117 | * The "UniNorth" version is present in all Core99 machines | |
118 | * (iBook, G4, new IMacs, and all the recent Apple machines). | |
119 | * It contains 3 controllers in one ASIC. | |
120 | * | |
121 | * The U3 is the bridge used on G5 machines. It contains an | |
122 | * AGP bus which is dealt with the old UniNorth access routines | |
123 | * and a HyperTransport bus which uses its own set of access | |
124 | * functions. | |
125 | */ | |
126 | ||
127 | #define MACRISC_CFA0(devfn, off) \ | |
1beb6a7d BH |
128 | ((1 << (unsigned int)PCI_SLOT(dev_fn)) \ |
129 | | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ | |
130 | | (((unsigned int)(off)) & 0xFCUL)) | |
14cf11af PM |
131 | |
132 | #define MACRISC_CFA1(bus, devfn, off) \ | |
1beb6a7d BH |
133 | ((((unsigned int)(bus)) << 16) \ |
134 | |(((unsigned int)(devfn)) << 8) \ | |
135 | |(((unsigned int)(off)) & 0xFCUL) \ | |
14cf11af PM |
136 | |1UL) |
137 | ||
b98fa508 RH |
138 | static void __iomem *macrisc_cfg_map_bus(struct pci_bus *bus, |
139 | unsigned int dev_fn, | |
140 | int offset) | |
14cf11af PM |
141 | { |
142 | unsigned int caddr; | |
b98fa508 | 143 | struct pci_controller *hose; |
14cf11af | 144 | |
b98fa508 RH |
145 | hose = pci_bus_to_host(bus); |
146 | if (hose == NULL) | |
147 | return NULL; | |
148 | ||
149 | if (bus->number == hose->first_busno) { | |
14cf11af | 150 | if (dev_fn < (11 << 3)) |
de125bf3 | 151 | return NULL; |
14cf11af PM |
152 | caddr = MACRISC_CFA0(dev_fn, offset); |
153 | } else | |
b98fa508 | 154 | caddr = MACRISC_CFA1(bus->number, dev_fn, offset); |
14cf11af PM |
155 | |
156 | /* Uninorth will return garbage if we don't read back the value ! */ | |
157 | do { | |
158 | out_le32(hose->cfg_addr, caddr); | |
159 | } while (in_le32(hose->cfg_addr) != caddr); | |
160 | ||
161 | offset &= has_uninorth ? 0x07 : 0x03; | |
de125bf3 | 162 | return hose->cfg_data + offset; |
14cf11af PM |
163 | } |
164 | ||
14cf11af PM |
165 | static struct pci_ops macrisc_pci_ops = |
166 | { | |
b98fa508 RH |
167 | .map_bus = macrisc_cfg_map_bus, |
168 | .read = pci_generic_config_read, | |
169 | .write = pci_generic_config_write, | |
14cf11af PM |
170 | }; |
171 | ||
35499c01 | 172 | #ifdef CONFIG_PPC32 |
14cf11af | 173 | /* |
3c3f42d6 | 174 | * Verify that a specific (bus, dev_fn) exists on chaos |
14cf11af | 175 | */ |
b98fa508 RH |
176 | static void __iomem *chaos_map_bus(struct pci_bus *bus, unsigned int devfn, |
177 | int offset) | |
14cf11af PM |
178 | { |
179 | struct device_node *np; | |
018a3d1d | 180 | const u32 *vendor, *device; |
14cf11af | 181 | |
1beb6a7d | 182 | if (offset >= 0x100) |
b98fa508 | 183 | return NULL; |
98d9f30c | 184 | np = of_pci_find_child_device(bus->dev.of_node, devfn); |
14cf11af | 185 | if (np == NULL) |
b98fa508 | 186 | return NULL; |
14cf11af | 187 | |
e2eb6392 SR |
188 | vendor = of_get_property(np, "vendor-id", NULL); |
189 | device = of_get_property(np, "device-id", NULL); | |
14cf11af | 190 | if (vendor == NULL || device == NULL) |
b98fa508 | 191 | return NULL; |
14cf11af PM |
192 | |
193 | if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) | |
194 | && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) | |
b98fa508 | 195 | return NULL; |
14cf11af | 196 | |
b98fa508 | 197 | return macrisc_cfg_map_bus(bus, devfn, offset); |
14cf11af PM |
198 | } |
199 | ||
200 | static struct pci_ops chaos_pci_ops = | |
201 | { | |
b98fa508 RH |
202 | .map_bus = chaos_map_bus, |
203 | .read = pci_generic_config_read, | |
204 | .write = pci_generic_config_write, | |
14cf11af PM |
205 | }; |
206 | ||
35499c01 | 207 | static void __init setup_chaos(struct pci_controller *hose, |
cc5d0189 | 208 | struct resource *addr) |
35499c01 PM |
209 | { |
210 | /* assume a `chaos' bridge */ | |
211 | hose->ops = &chaos_pci_ops; | |
cc5d0189 BH |
212 | hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); |
213 | hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); | |
35499c01 | 214 | } |
35499c01 PM |
215 | #endif /* CONFIG_PPC32 */ |
216 | ||
217 | #ifdef CONFIG_PPC64 | |
14cf11af PM |
218 | /* |
219 | * These versions of U3 HyperTransport config space access ops do not | |
220 | * implement self-view of the HT host yet | |
221 | */ | |
222 | ||
223 | /* | |
224 | * This function deals with some "special cases" devices. | |
225 | * | |
226 | * 0 -> No special case | |
25985edc | 227 | * 1 -> Skip the device but act as if the access was successful |
14cf11af PM |
228 | * (return 0xff's on reads, eventually, cache config space |
229 | * accesses in a later version) | |
af901ca1 | 230 | * -1 -> Hide the device (unsuccessful access) |
14cf11af PM |
231 | */ |
232 | static int u3_ht_skip_device(struct pci_controller *hose, | |
233 | struct pci_bus *bus, unsigned int devfn) | |
234 | { | |
235 | struct device_node *busdn, *dn; | |
236 | int i; | |
237 | ||
238 | /* We only allow config cycles to devices that are in OF device-tree | |
239 | * as we are apparently having some weird things going on with some | |
444532d4 BH |
240 | * revs of K2 on recent G5s, except for the host bridge itself, which |
241 | * is missing from the tree but we know we can probe. | |
14cf11af PM |
242 | */ |
243 | if (bus->self) | |
244 | busdn = pci_device_to_OF_node(bus->self); | |
444532d4 BH |
245 | else if (devfn == 0) |
246 | return 0; | |
14cf11af | 247 | else |
44ef3390 | 248 | busdn = hose->dn; |
14cf11af | 249 | for (dn = busdn->child; dn; dn = dn->sibling) |
e07102db | 250 | if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn) |
14cf11af PM |
251 | break; |
252 | if (dn == NULL) | |
253 | return -1; | |
254 | ||
255 | /* | |
256 | * When a device in K2 is powered down, we die on config | |
257 | * cycle accesses. Fix that here. | |
258 | */ | |
259 | for (i=0; i<2; i++) | |
260 | if (k2_skiplist[i] == dn) | |
261 | return 1; | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
266 | #define U3_HT_CFA0(devfn, off) \ | |
1beb6a7d | 267 | ((((unsigned int)devfn) << 8) | offset) |
14cf11af PM |
268 | #define U3_HT_CFA1(bus, devfn, off) \ |
269 | (U3_HT_CFA0(devfn, off) \ | |
1beb6a7d | 270 | + (((unsigned int)bus) << 16) \ |
14cf11af PM |
271 | + 0x01000000UL) |
272 | ||
444532d4 BH |
273 | static void __iomem *u3_ht_cfg_access(struct pci_controller *hose, u8 bus, |
274 | u8 devfn, u8 offset, int *swap) | |
14cf11af | 275 | { |
444532d4 | 276 | *swap = 1; |
14cf11af | 277 | if (bus == hose->first_busno) { |
444532d4 BH |
278 | if (devfn != 0) |
279 | return hose->cfg_data + U3_HT_CFA0(devfn, offset); | |
280 | *swap = 0; | |
281 | return ((void __iomem *)hose->cfg_addr) + (offset << 2); | |
14cf11af | 282 | } else |
de125bf3 | 283 | return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); |
14cf11af PM |
284 | } |
285 | ||
286 | static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, | |
287 | int offset, int len, u32 *val) | |
288 | { | |
3c3f42d6 | 289 | struct pci_controller *hose; |
444532d4 BH |
290 | void __iomem *addr; |
291 | int swap; | |
14cf11af | 292 | |
3c3f42d6 PM |
293 | hose = pci_bus_to_host(bus); |
294 | if (hose == NULL) | |
14cf11af | 295 | return PCIBIOS_DEVICE_NOT_FOUND; |
1beb6a7d BH |
296 | if (offset >= 0x100) |
297 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
444532d4 | 298 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); |
14cf11af PM |
299 | if (!addr) |
300 | return PCIBIOS_DEVICE_NOT_FOUND; | |
301 | ||
302 | switch (u3_ht_skip_device(hose, bus, devfn)) { | |
303 | case 0: | |
304 | break; | |
305 | case 1: | |
3c3f42d6 PM |
306 | switch (len) { |
307 | case 1: | |
308 | *val = 0xff; break; | |
309 | case 2: | |
310 | *val = 0xffff; break; | |
311 | default: | |
312 | *val = 0xfffffffful; break; | |
313 | } | |
314 | return PCIBIOS_SUCCESSFUL; | |
14cf11af PM |
315 | default: |
316 | return PCIBIOS_DEVICE_NOT_FOUND; | |
3c3f42d6 PM |
317 | } |
318 | ||
14cf11af PM |
319 | /* |
320 | * Note: the caller has already checked that offset is | |
321 | * suitably aligned and that len is 1, 2 or 4. | |
322 | */ | |
323 | switch (len) { | |
324 | case 1: | |
de125bf3 | 325 | *val = in_8(addr); |
14cf11af PM |
326 | break; |
327 | case 2: | |
444532d4 | 328 | *val = swap ? in_le16(addr) : in_be16(addr); |
14cf11af PM |
329 | break; |
330 | default: | |
444532d4 | 331 | *val = swap ? in_le32(addr) : in_be32(addr); |
14cf11af PM |
332 | break; |
333 | } | |
334 | return PCIBIOS_SUCCESSFUL; | |
335 | } | |
336 | ||
337 | static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, | |
338 | int offset, int len, u32 val) | |
339 | { | |
3c3f42d6 | 340 | struct pci_controller *hose; |
444532d4 BH |
341 | void __iomem *addr; |
342 | int swap; | |
14cf11af | 343 | |
3c3f42d6 PM |
344 | hose = pci_bus_to_host(bus); |
345 | if (hose == NULL) | |
14cf11af | 346 | return PCIBIOS_DEVICE_NOT_FOUND; |
1beb6a7d BH |
347 | if (offset >= 0x100) |
348 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
444532d4 | 349 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); |
14cf11af PM |
350 | if (!addr) |
351 | return PCIBIOS_DEVICE_NOT_FOUND; | |
352 | ||
353 | switch (u3_ht_skip_device(hose, bus, devfn)) { | |
354 | case 0: | |
355 | break; | |
356 | case 1: | |
357 | return PCIBIOS_SUCCESSFUL; | |
358 | default: | |
359 | return PCIBIOS_DEVICE_NOT_FOUND; | |
360 | } | |
361 | ||
362 | /* | |
363 | * Note: the caller has already checked that offset is | |
364 | * suitably aligned and that len is 1, 2 or 4. | |
365 | */ | |
366 | switch (len) { | |
367 | case 1: | |
de125bf3 | 368 | out_8(addr, val); |
14cf11af PM |
369 | break; |
370 | case 2: | |
444532d4 | 371 | swap ? out_le16(addr, val) : out_be16(addr, val); |
14cf11af PM |
372 | break; |
373 | default: | |
444532d4 | 374 | swap ? out_le32(addr, val) : out_be32(addr, val); |
14cf11af PM |
375 | break; |
376 | } | |
377 | return PCIBIOS_SUCCESSFUL; | |
378 | } | |
379 | ||
380 | static struct pci_ops u3_ht_pci_ops = | |
381 | { | |
3fac10e7 NL |
382 | .read = u3_ht_read_config, |
383 | .write = u3_ht_write_config, | |
14cf11af | 384 | }; |
1beb6a7d BH |
385 | |
386 | #define U4_PCIE_CFA0(devfn, off) \ | |
387 | ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \ | |
388 | | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ | |
389 | | ((((unsigned int)(off)) >> 8) << 28) \ | |
390 | | (((unsigned int)(off)) & 0xfcU)) | |
391 | ||
392 | #define U4_PCIE_CFA1(bus, devfn, off) \ | |
393 | ((((unsigned int)(bus)) << 16) \ | |
394 | |(((unsigned int)(devfn)) << 8) \ | |
395 | | ((((unsigned int)(off)) >> 8) << 28) \ | |
396 | |(((unsigned int)(off)) & 0xfcU) \ | |
397 | |1UL) | |
398 | ||
b98fa508 RH |
399 | static void __iomem *u4_pcie_cfg_map_bus(struct pci_bus *bus, |
400 | unsigned int dev_fn, | |
401 | int offset) | |
1beb6a7d | 402 | { |
b98fa508 | 403 | struct pci_controller *hose; |
1beb6a7d BH |
404 | unsigned int caddr; |
405 | ||
b98fa508 RH |
406 | if (offset >= 0x1000) |
407 | return NULL; | |
408 | ||
409 | hose = pci_bus_to_host(bus); | |
410 | if (!hose) | |
411 | return NULL; | |
412 | ||
413 | if (bus->number == hose->first_busno) { | |
1beb6a7d BH |
414 | caddr = U4_PCIE_CFA0(dev_fn, offset); |
415 | } else | |
b98fa508 | 416 | caddr = U4_PCIE_CFA1(bus->number, dev_fn, offset); |
1beb6a7d BH |
417 | |
418 | /* Uninorth will return garbage if we don't read back the value ! */ | |
419 | do { | |
420 | out_le32(hose->cfg_addr, caddr); | |
421 | } while (in_le32(hose->cfg_addr) != caddr); | |
422 | ||
423 | offset &= 0x03; | |
de125bf3 | 424 | return hose->cfg_data + offset; |
1beb6a7d BH |
425 | } |
426 | ||
1beb6a7d BH |
427 | static struct pci_ops u4_pcie_pci_ops = |
428 | { | |
b98fa508 RH |
429 | .map_bus = u4_pcie_cfg_map_bus, |
430 | .read = pci_generic_config_read, | |
431 | .write = pci_generic_config_write, | |
1beb6a7d BH |
432 | }; |
433 | ||
cad5cef6 | 434 | static void pmac_pci_fixup_u4_of_node(struct pci_dev *dev) |
16fa42af BH |
435 | { |
436 | /* Apple's device-tree "hides" the root complex virtual P2P bridge | |
437 | * on U4. However, Linux sees it, causing the PCI <-> OF matching | |
438 | * code to fail to properly match devices below it. This works around | |
439 | * it by setting the node of the bridge to point to the PHB node, | |
440 | * which is not entirely correct but fixes the matching code and | |
441 | * doesn't break anything else. It's also the simplest possible fix. | |
442 | */ | |
443 | if (dev->dev.of_node == NULL) | |
444 | dev->dev.of_node = pcibios_get_phb_of_node(dev->bus); | |
445 | } | |
446 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, 0x5b, pmac_pci_fixup_u4_of_node); | |
447 | ||
35499c01 | 448 | #endif /* CONFIG_PPC64 */ |
14cf11af | 449 | |
35499c01 | 450 | #ifdef CONFIG_PPC32 |
14cf11af PM |
451 | /* |
452 | * For a bandit bridge, turn on cache coherency if necessary. | |
453 | * N.B. we could clean this up using the hose ops directly. | |
454 | */ | |
3c3f42d6 | 455 | static void __init init_bandit(struct pci_controller *bp) |
14cf11af PM |
456 | { |
457 | unsigned int vendev, magic; | |
458 | int rev; | |
459 | ||
460 | /* read the word at offset 0 in config space for device 11 */ | |
461 | out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); | |
462 | udelay(2); | |
463 | vendev = in_le32(bp->cfg_data); | |
464 | if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + | |
465 | PCI_VENDOR_ID_APPLE) { | |
466 | /* read the revision id */ | |
467 | out_le32(bp->cfg_addr, | |
468 | (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); | |
469 | udelay(2); | |
470 | rev = in_8(bp->cfg_data); | |
471 | if (rev != BANDIT_REVID) | |
472 | printk(KERN_WARNING | |
473 | "Unknown revision %d for bandit\n", rev); | |
474 | } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { | |
475 | printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); | |
476 | return; | |
477 | } | |
478 | ||
479 | /* read the word at offset 0x50 */ | |
480 | out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); | |
481 | udelay(2); | |
482 | magic = in_le32(bp->cfg_data); | |
483 | if ((magic & BANDIT_COHERENT) != 0) | |
484 | return; | |
485 | magic |= BANDIT_COHERENT; | |
486 | udelay(2); | |
487 | out_le32(bp->cfg_data, magic); | |
488 | printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); | |
489 | } | |
490 | ||
14cf11af PM |
491 | /* |
492 | * Tweak the PCI-PCI bridge chip on the blue & white G3s. | |
493 | */ | |
3c3f42d6 | 494 | static void __init init_p2pbridge(void) |
14cf11af PM |
495 | { |
496 | struct device_node *p2pbridge; | |
497 | struct pci_controller* hose; | |
498 | u8 bus, devfn; | |
499 | u16 val; | |
500 | ||
501 | /* XXX it would be better here to identify the specific | |
502 | PCI-PCI bridge chip we have. */ | |
30686ba6 SR |
503 | p2pbridge = of_find_node_by_name(NULL, "pci-bridge"); |
504 | if (p2pbridge == NULL | |
14cf11af PM |
505 | || p2pbridge->parent == NULL |
506 | || strcmp(p2pbridge->parent->name, "pci") != 0) | |
30686ba6 | 507 | goto done; |
14cf11af PM |
508 | if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { |
509 | DBG("Can't find PCI infos for PCI<->PCI bridge\n"); | |
30686ba6 | 510 | goto done; |
14cf11af PM |
511 | } |
512 | /* Warning: At this point, we have not yet renumbered all busses. | |
513 | * So we must use OF walking to find out hose | |
514 | */ | |
515 | hose = pci_find_hose_for_OF_device(p2pbridge); | |
516 | if (!hose) { | |
517 | DBG("Can't find hose for PCI<->PCI bridge\n"); | |
30686ba6 | 518 | goto done; |
14cf11af PM |
519 | } |
520 | if (early_read_config_word(hose, bus, devfn, | |
521 | PCI_BRIDGE_CONTROL, &val) < 0) { | |
cc5d0189 BH |
522 | printk(KERN_ERR "init_p2pbridge: couldn't read bridge" |
523 | " control\n"); | |
30686ba6 | 524 | goto done; |
14cf11af PM |
525 | } |
526 | val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; | |
527 | early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); | |
30686ba6 SR |
528 | done: |
529 | of_node_put(p2pbridge); | |
14cf11af PM |
530 | } |
531 | ||
0ebfff14 BH |
532 | static void __init init_second_ohare(void) |
533 | { | |
534 | struct device_node *np = of_find_node_by_name(NULL, "pci106b,7"); | |
535 | unsigned char bus, devfn; | |
536 | unsigned short cmd; | |
537 | ||
538 | if (np == NULL) | |
539 | return; | |
540 | ||
541 | /* This must run before we initialize the PICs since the second | |
542 | * ohare hosts a PIC that will be accessed there. | |
543 | */ | |
544 | if (pci_device_from_OF_node(np, &bus, &devfn) == 0) { | |
545 | struct pci_controller* hose = | |
546 | pci_find_hose_for_OF_device(np); | |
547 | if (!hose) { | |
548 | printk(KERN_ERR "Can't find PCI hose for OHare2 !\n"); | |
afcb0654 | 549 | of_node_put(np); |
0ebfff14 BH |
550 | return; |
551 | } | |
552 | early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); | |
553 | cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; | |
554 | cmd &= ~PCI_COMMAND_IO; | |
555 | early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); | |
556 | } | |
557 | has_second_ohare = 1; | |
afcb0654 | 558 | of_node_put(np); |
0ebfff14 BH |
559 | } |
560 | ||
14cf11af PM |
561 | /* |
562 | * Some Apple desktop machines have a NEC PD720100A USB2 controller | |
563 | * on the motherboard. Open Firmware, on these, will disable the | |
564 | * EHCI part of it so it behaves like a pair of OHCI's. This fixup | |
565 | * code re-enables it ;) | |
566 | */ | |
3c3f42d6 | 567 | static void __init fixup_nec_usb2(void) |
14cf11af PM |
568 | { |
569 | struct device_node *nec; | |
570 | ||
ccdb8ed3 | 571 | for_each_node_by_name(nec, "usb") { |
14cf11af | 572 | struct pci_controller *hose; |
018a3d1d JK |
573 | u32 data; |
574 | const u32 *prop; | |
14cf11af | 575 | u8 bus, devfn; |
35499c01 | 576 | |
e2eb6392 | 577 | prop = of_get_property(nec, "vendor-id", NULL); |
14cf11af PM |
578 | if (prop == NULL) |
579 | continue; | |
580 | if (0x1033 != *prop) | |
581 | continue; | |
e2eb6392 | 582 | prop = of_get_property(nec, "device-id", NULL); |
14cf11af PM |
583 | if (prop == NULL) |
584 | continue; | |
585 | if (0x0035 != *prop) | |
586 | continue; | |
e2eb6392 | 587 | prop = of_get_property(nec, "reg", NULL); |
14cf11af PM |
588 | if (prop == NULL) |
589 | continue; | |
590 | devfn = (prop[0] >> 8) & 0xff; | |
591 | bus = (prop[0] >> 16) & 0xff; | |
592 | if (PCI_FUNC(devfn) != 0) | |
593 | continue; | |
594 | hose = pci_find_hose_for_OF_device(nec); | |
595 | if (!hose) | |
596 | continue; | |
597 | early_read_config_dword(hose, bus, devfn, 0xe4, &data); | |
598 | if (data & 1UL) { | |
cc5d0189 BH |
599 | printk("Found NEC PD720100A USB2 chip with disabled" |
600 | " EHCI, fixing up...\n"); | |
14cf11af PM |
601 | data &= ~1UL; |
602 | early_write_config_dword(hose, bus, devfn, 0xe4, data); | |
14cf11af PM |
603 | } |
604 | } | |
605 | } | |
606 | ||
35499c01 | 607 | static void __init setup_bandit(struct pci_controller *hose, |
cc5d0189 | 608 | struct resource *addr) |
14cf11af PM |
609 | { |
610 | hose->ops = ¯isc_pci_ops; | |
cc5d0189 BH |
611 | hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); |
612 | hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); | |
14cf11af PM |
613 | init_bandit(hose); |
614 | } | |
615 | ||
35499c01 | 616 | static int __init setup_uninorth(struct pci_controller *hose, |
cc5d0189 | 617 | struct resource *addr) |
14cf11af | 618 | { |
0e47ff1c | 619 | pci_add_flags(PCI_REASSIGN_ALL_BUS); |
35499c01 PM |
620 | has_uninorth = 1; |
621 | hose->ops = ¯isc_pci_ops; | |
cc5d0189 BH |
622 | hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); |
623 | hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); | |
35499c01 | 624 | /* We "know" that the bridge at f2000000 has the PCI slots. */ |
cc5d0189 | 625 | return addr->start == 0xf2000000; |
14cf11af | 626 | } |
cc5d0189 | 627 | #endif /* CONFIG_PPC32 */ |
14cf11af | 628 | |
35499c01 | 629 | #ifdef CONFIG_PPC64 |
14cf11af PM |
630 | static void __init setup_u3_agp(struct pci_controller* hose) |
631 | { | |
632 | /* On G5, we move AGP up to high bus number so we don't need | |
633 | * to reassign bus numbers for HT. If we ever have P2P bridges | |
35499c01 | 634 | * on AGP, we'll have to move pci_assign_all_busses to the |
14cf11af PM |
635 | * pci_controller structure so we enable it for AGP and not for |
636 | * HT childs. | |
637 | * We hard code the address because of the different size of | |
638 | * the reg address cell, we shall fix that by killing struct | |
639 | * reg_property and using some accessor functions instead | |
640 | */ | |
3c3f42d6 | 641 | hose->first_busno = 0xf0; |
14cf11af PM |
642 | hose->last_busno = 0xff; |
643 | has_uninorth = 1; | |
644 | hose->ops = ¯isc_pci_ops; | |
645 | hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); | |
646 | hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); | |
14cf11af PM |
647 | u3_agp = hose; |
648 | } | |
649 | ||
1beb6a7d BH |
650 | static void __init setup_u4_pcie(struct pci_controller* hose) |
651 | { | |
652 | /* We currently only implement the "non-atomic" config space, to | |
653 | * be optimised later. | |
654 | */ | |
655 | hose->ops = &u4_pcie_pci_ops; | |
656 | hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); | |
657 | hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); | |
658 | ||
659 | /* The bus contains a bridge from root -> device, we need to | |
660 | * make it visible on bus 0 so that we pick the right type | |
661 | * of config cycles. If we didn't, we would have to force all | |
662 | * config cycles to be type 1. So we override the "bus-range" | |
663 | * property here | |
664 | */ | |
665 | hose->first_busno = 0x00; | |
666 | hose->last_busno = 0xff; | |
d0264ce7 BH |
667 | } |
668 | ||
669 | static void __init parse_region_decode(struct pci_controller *hose, | |
670 | u32 decode) | |
671 | { | |
672 | unsigned long base, end, next = -1; | |
673 | int i, cur = -1; | |
674 | ||
675 | /* Iterate through all bits. We ignore the last bit as this region is | |
676 | * reserved for the ROM among other niceties | |
677 | */ | |
678 | for (i = 0; i < 31; i++) { | |
679 | if ((decode & (0x80000000 >> i)) == 0) | |
680 | continue; | |
681 | if (i < 16) { | |
682 | base = 0xf0000000 | (((u32)i) << 24); | |
683 | end = base + 0x00ffffff; | |
684 | } else { | |
685 | base = ((u32)i-16) << 28; | |
686 | end = base + 0x0fffffff; | |
687 | } | |
688 | if (base != next) { | |
689 | if (++cur >= 3) { | |
690 | printk(KERN_WARNING "PCI: Too many ranges !\n"); | |
691 | break; | |
692 | } | |
693 | hose->mem_resources[cur].flags = IORESOURCE_MEM; | |
694 | hose->mem_resources[cur].name = hose->dn->full_name; | |
695 | hose->mem_resources[cur].start = base; | |
696 | hose->mem_resources[cur].end = end; | |
3fd47f06 | 697 | hose->mem_offset[cur] = 0; |
d0264ce7 BH |
698 | DBG(" %d: 0x%08lx-0x%08lx\n", cur, base, end); |
699 | } else { | |
700 | DBG(" : -0x%08lx\n", end); | |
701 | hose->mem_resources[cur].end = end; | |
702 | } | |
703 | next = end + 1; | |
704 | } | |
1beb6a7d BH |
705 | } |
706 | ||
14cf11af PM |
707 | static void __init setup_u3_ht(struct pci_controller* hose) |
708 | { | |
44ef3390 | 709 | struct device_node *np = hose->dn; |
444532d4 | 710 | struct resource cfg_res, self_res; |
d0264ce7 | 711 | u32 decode; |
1beb6a7d | 712 | |
14cf11af PM |
713 | hose->ops = &u3_ht_pci_ops; |
714 | ||
444532d4 BH |
715 | /* Get base addresses from OF tree |
716 | */ | |
717 | if (of_address_to_resource(np, 0, &cfg_res) || | |
718 | of_address_to_resource(np, 1, &self_res)) { | |
719 | printk(KERN_ERR "PCI: Failed to get U3/U4 HT resources !\n"); | |
720 | return; | |
721 | } | |
722 | ||
723 | /* Map external cfg space access into cfg_data and self registers | |
724 | * into cfg_addr | |
14cf11af | 725 | */ |
444532d4 | 726 | hose->cfg_data = ioremap(cfg_res.start, 0x02000000); |
28f65c11 | 727 | hose->cfg_addr = ioremap(self_res.start, resource_size(&self_res)); |
14cf11af PM |
728 | |
729 | /* | |
d0264ce7 BH |
730 | * /ht node doesn't expose a "ranges" property, we read the register |
731 | * that controls the decoding logic and use that for memory regions. | |
732 | * The IO region is hard coded since it is fixed in HW as well. | |
14cf11af PM |
733 | */ |
734 | hose->io_base_phys = 0xf4000000; | |
35499c01 | 735 | hose->pci_io_size = 0x00400000; |
14cf11af PM |
736 | hose->io_resource.name = np->full_name; |
737 | hose->io_resource.start = 0; | |
738 | hose->io_resource.end = 0x003fffff; | |
739 | hose->io_resource.flags = IORESOURCE_IO; | |
14cf11af PM |
740 | hose->first_busno = 0; |
741 | hose->last_busno = 0xef; | |
14cf11af | 742 | |
d0264ce7 BH |
743 | /* Note: fix offset when cfg_addr becomes a void * */ |
744 | decode = in_be32(hose->cfg_addr + 0x80); | |
745 | ||
746 | DBG("PCI: Apple HT bridge decode register: 0x%08x\n", decode); | |
747 | ||
748 | /* NOTE: The decode register setup is a bit weird... region | |
749 | * 0xf8000000 for example is marked as enabled in there while it's | |
750 | & actually the memory controller registers. | |
751 | * That means that we are incorrectly attributing it to HT. | |
752 | * | |
753 | * In a similar vein, region 0xf4000000 is actually the HT IO space but | |
754 | * also marked as enabled in here and 0xf9000000 is used by some other | |
755 | * internal bits of the northbridge. | |
756 | * | |
757 | * Unfortunately, we can't just mask out those bit as we would end | |
758 | * up with more regions than we can cope (linux can only cope with | |
759 | * 3 memory regions for a PHB at this stage). | |
760 | * | |
761 | * So for now, we just do a little hack. We happen to -know- that | |
762 | * Apple firmware doesn't assign things below 0xfa000000 for that | |
763 | * bridge anyway so we mask out all bits we don't want. | |
14cf11af | 764 | */ |
d0264ce7 BH |
765 | decode &= 0x003fffff; |
766 | ||
767 | /* Now parse the resulting bits and build resources */ | |
768 | parse_region_decode(hose, decode); | |
14cf11af | 769 | } |
cc5d0189 | 770 | #endif /* CONFIG_PPC64 */ |
14cf11af PM |
771 | |
772 | /* | |
773 | * We assume that if we have a G3 powermac, we have one bridge called | |
774 | * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, | |
775 | * if we have one or more bandit or chaos bridges, we don't have a MPC106. | |
776 | */ | |
09b55f76 | 777 | static int __init pmac_add_bridge(struct device_node *dev) |
14cf11af PM |
778 | { |
779 | int len; | |
780 | struct pci_controller *hose; | |
cc5d0189 | 781 | struct resource rsrc; |
35499c01 | 782 | char *disp_name; |
018a3d1d | 783 | const int *bus_range; |
cc5d0189 | 784 | int primary = 1, has_address = 0; |
14cf11af PM |
785 | |
786 | DBG("Adding PCI host bridge %s\n", dev->full_name); | |
787 | ||
cc5d0189 BH |
788 | /* Fetch host bridge registers address */ |
789 | has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); | |
790 | ||
791 | /* Get bus range if any */ | |
e2eb6392 | 792 | bus_range = of_get_property(dev, "bus-range", &len); |
35499c01 | 793 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
b5166cc2 BH |
794 | printk(KERN_WARNING "Can't get bus-range for %s, assume" |
795 | " bus 0\n", dev->full_name); | |
35499c01 PM |
796 | } |
797 | ||
b5166cc2 | 798 | hose = pcibios_alloc_controller(dev); |
35499c01 PM |
799 | if (!hose) |
800 | return -ENOMEM; | |
35499c01 PM |
801 | hose->first_busno = bus_range ? bus_range[0] : 0; |
802 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
e63f26d3 | 803 | hose->controller_ops = pmac_pci_controller_ops; |
14cf11af PM |
804 | |
805 | disp_name = NULL; | |
cc5d0189 BH |
806 | |
807 | /* 64 bits only bridges */ | |
b5166cc2 | 808 | #ifdef CONFIG_PPC64 |
55b61fec | 809 | if (of_device_is_compatible(dev, "u3-agp")) { |
35499c01 PM |
810 | setup_u3_agp(hose); |
811 | disp_name = "U3-AGP"; | |
812 | primary = 0; | |
55b61fec | 813 | } else if (of_device_is_compatible(dev, "u3-ht")) { |
35499c01 PM |
814 | setup_u3_ht(hose); |
815 | disp_name = "U3-HT"; | |
816 | primary = 1; | |
55b61fec | 817 | } else if (of_device_is_compatible(dev, "u4-pcie")) { |
1beb6a7d BH |
818 | setup_u4_pcie(hose); |
819 | disp_name = "U4-PCIE"; | |
820 | primary = 0; | |
35499c01 | 821 | } |
1beb6a7d BH |
822 | printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:" |
823 | " %d->%d\n", disp_name, hose->first_busno, hose->last_busno); | |
cc5d0189 BH |
824 | #endif /* CONFIG_PPC64 */ |
825 | ||
826 | /* 32 bits only bridges */ | |
827 | #ifdef CONFIG_PPC32 | |
55b61fec | 828 | if (of_device_is_compatible(dev, "uni-north")) { |
cc5d0189 | 829 | primary = setup_uninorth(hose, &rsrc); |
35499c01 | 830 | disp_name = "UniNorth"; |
3c3f42d6 | 831 | } else if (strcmp(dev->name, "pci") == 0) { |
35499c01 PM |
832 | /* XXX assume this is a mpc106 (grackle) */ |
833 | setup_grackle(hose); | |
834 | disp_name = "Grackle (MPC106)"; | |
835 | } else if (strcmp(dev->name, "bandit") == 0) { | |
cc5d0189 | 836 | setup_bandit(hose, &rsrc); |
35499c01 PM |
837 | disp_name = "Bandit"; |
838 | } else if (strcmp(dev->name, "chaos") == 0) { | |
cc5d0189 | 839 | setup_chaos(hose, &rsrc); |
35499c01 PM |
840 | disp_name = "Chaos"; |
841 | primary = 0; | |
842 | } | |
685143ac | 843 | printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. " |
cc5d0189 | 844 | "Firmware bus number: %d->%d\n", |
685143ac GKH |
845 | disp_name, (unsigned long long)rsrc.start, hose->first_busno, |
846 | hose->last_busno); | |
cc5d0189 BH |
847 | #endif /* CONFIG_PPC32 */ |
848 | ||
35499c01 PM |
849 | DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", |
850 | hose, hose->cfg_addr, hose->cfg_data); | |
851 | ||
852 | /* Interpret the "ranges" property */ | |
853 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
854 | pci_process_bridge_OF_ranges(hose, dev, primary); | |
855 | ||
856 | /* Fixup "bus-range" OF property */ | |
857 | fixup_bus_range(dev); | |
14cf11af PM |
858 | |
859 | return 0; | |
860 | } | |
861 | ||
cad5cef6 | 862 | void pmac_pci_irq_fixup(struct pci_dev *dev) |
14cf11af | 863 | { |
6e99e458 | 864 | #ifdef CONFIG_PPC32 |
f90bb153 BH |
865 | /* Fixup interrupt for the modem/ethernet combo controller. |
866 | * on machines with a second ohare chip. | |
867 | * The number in the device tree (27) is bogus (correct for | |
868 | * the ethernet-only board but not the combo ethernet/modem | |
869 | * board). The real interrupt is 28 on the second controller | |
870 | * -> 28+32 = 60. | |
871 | */ | |
872 | if (has_second_ohare && | |
873 | dev->vendor == PCI_VENDOR_ID_DEC && | |
874 | dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) { | |
875 | dev->irq = irq_create_mapping(NULL, 60); | |
ec775d0e | 876 | irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); |
14cf11af | 877 | } |
f90bb153 | 878 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
879 | } |
880 | ||
35499c01 | 881 | void __init pmac_pci_init(void) |
3c3f42d6 PM |
882 | { |
883 | struct device_node *np, *root; | |
884 | struct device_node *ht = NULL; | |
885 | ||
0e47ff1c | 886 | pci_set_flags(PCI_CAN_SKIP_ISA_ALIGN); |
3fd94c6b | 887 | |
3c3f42d6 PM |
888 | root = of_find_node_by_path("/"); |
889 | if (root == NULL) { | |
35499c01 PM |
890 | printk(KERN_CRIT "pmac_pci_init: can't find root " |
891 | "of device tree\n"); | |
3c3f42d6 PM |
892 | return; |
893 | } | |
894 | for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { | |
895 | if (np->name == NULL) | |
896 | continue; | |
897 | if (strcmp(np->name, "bandit") == 0 | |
898 | || strcmp(np->name, "chaos") == 0 | |
899 | || strcmp(np->name, "pci") == 0) { | |
09b55f76 | 900 | if (pmac_add_bridge(np) == 0) |
3c3f42d6 PM |
901 | of_node_get(np); |
902 | } | |
903 | if (strcmp(np->name, "ht") == 0) { | |
904 | of_node_get(np); | |
905 | ht = np; | |
906 | } | |
907 | } | |
908 | of_node_put(root); | |
909 | ||
35499c01 | 910 | #ifdef CONFIG_PPC64 |
3c3f42d6 PM |
911 | /* Probe HT last as it relies on the agp resources to be already |
912 | * setup | |
913 | */ | |
09b55f76 | 914 | if (ht && pmac_add_bridge(ht) != 0) |
3c3f42d6 PM |
915 | of_node_put(ht); |
916 | ||
35499c01 PM |
917 | /* Setup the linkage between OF nodes and PHBs */ |
918 | pci_devs_phb_init(); | |
919 | ||
920 | /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We | |
921 | * assume there is no P2P bridge on the AGP bus, which should be a | |
1beb6a7d BH |
922 | * safe assumptions for now. We should do something better in the |
923 | * future though | |
35499c01 PM |
924 | */ |
925 | if (u3_agp) { | |
44ef3390 | 926 | struct device_node *np = u3_agp->dn; |
35499c01 PM |
927 | PCI_DN(np)->busno = 0xf0; |
928 | for (np = np->child; np; np = np->sibling) | |
929 | PCI_DN(np)->busno = 0xf0; | |
930 | } | |
35499c01 PM |
931 | /* pmac_check_ht_link(); */ |
932 | ||
35499c01 | 933 | #else /* CONFIG_PPC64 */ |
3c3f42d6 | 934 | init_p2pbridge(); |
0ebfff14 | 935 | init_second_ohare(); |
3c3f42d6 | 936 | fixup_nec_usb2(); |
35499c01 | 937 | |
3c3f42d6 PM |
938 | /* We are still having some issues with the Xserve G4, enabling |
939 | * some offset between bus number and domains for now when we | |
940 | * assign all busses should help for now | |
941 | */ | |
0e47ff1c | 942 | if (pci_has_flag(PCI_REASSIGN_ALL_BUS)) |
3c3f42d6 | 943 | pcibios_assign_bus_offset = 0x10; |
35499c01 | 944 | #endif |
3c3f42d6 PM |
945 | } |
946 | ||
bc0826cf | 947 | #ifdef CONFIG_PPC32 |
e63f26d3 | 948 | static bool pmac_pci_enable_device_hook(struct pci_dev *dev) |
14cf11af PM |
949 | { |
950 | struct device_node* node; | |
951 | int updatecfg = 0; | |
952 | int uninorth_child; | |
953 | ||
954 | node = pci_device_to_OF_node(dev); | |
955 | ||
956 | /* We don't want to enable USB controllers absent from the OF tree | |
957 | * (iBook second controller) | |
958 | */ | |
959 | if (dev->vendor == PCI_VENDOR_ID_APPLE | |
c67808ee | 960 | && dev->class == PCI_CLASS_SERIAL_USB_OHCI |
14cf11af PM |
961 | && !node) { |
962 | printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", | |
963 | pci_name(dev)); | |
c88c2a18 | 964 | return false; |
14cf11af PM |
965 | } |
966 | ||
967 | if (!node) | |
c88c2a18 | 968 | return true; |
14cf11af PM |
969 | |
970 | uninorth_child = node->parent && | |
55b61fec | 971 | of_device_is_compatible(node->parent, "uni-north"); |
35499c01 | 972 | |
14cf11af PM |
973 | /* Firewire & GMAC were disabled after PCI probe, the driver is |
974 | * claiming them, we must re-enable them now. | |
975 | */ | |
976 | if (uninorth_child && !strcmp(node->name, "firewire") && | |
55b61fec SR |
977 | (of_device_is_compatible(node, "pci106b,18") || |
978 | of_device_is_compatible(node, "pci106b,30") || | |
979 | of_device_is_compatible(node, "pci11c1,5811"))) { | |
14cf11af PM |
980 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); |
981 | pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); | |
982 | updatecfg = 1; | |
983 | } | |
984 | if (uninorth_child && !strcmp(node->name, "ethernet") && | |
55b61fec | 985 | of_device_is_compatible(node, "gmac")) { |
14cf11af PM |
986 | pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); |
987 | updatecfg = 1; | |
988 | } | |
989 | ||
549beb9b BH |
990 | /* |
991 | * Fixup various header fields on 32 bits. We don't do that on | |
992 | * 64 bits as some of these have strange values behind the HT | |
993 | * bridge and we must not, for example, enable MWI or set the | |
994 | * cache line size on them. | |
995 | */ | |
14cf11af PM |
996 | if (updatecfg) { |
997 | u16 cmd; | |
35499c01 | 998 | |
14cf11af | 999 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
35499c01 PM |
1000 | cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
1001 | | PCI_COMMAND_INVALIDATE; | |
1002 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1003 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); | |
549beb9b | 1004 | |
35499c01 PM |
1005 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, |
1006 | L1_CACHE_BYTES >> 2); | |
14cf11af PM |
1007 | } |
1008 | ||
c88c2a18 | 1009 | return true; |
14cf11af PM |
1010 | } |
1011 | ||
cad5cef6 | 1012 | void pmac_pci_fixup_ohci(struct pci_dev *dev) |
bc0826cf BH |
1013 | { |
1014 | struct device_node *node = pci_device_to_OF_node(dev); | |
1015 | ||
1016 | /* We don't want to assign resources to USB controllers | |
1017 | * absent from the OF tree (iBook second controller) | |
1018 | */ | |
1019 | if (dev->class == PCI_CLASS_SERIAL_USB_OHCI && !node) | |
1020 | dev->resource[0].flags = 0; | |
1021 | } | |
1022 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_ANY_ID, pmac_pci_fixup_ohci); | |
1023 | ||
14cf11af PM |
1024 | /* We power down some devices after they have been probed. They'll |
1025 | * be powered back on later on | |
1026 | */ | |
35499c01 | 1027 | void __init pmac_pcibios_after_init(void) |
14cf11af PM |
1028 | { |
1029 | struct device_node* nd; | |
1030 | ||
30686ba6 | 1031 | for_each_node_by_name(nd, "firewire") { |
55b61fec SR |
1032 | if (nd->parent && (of_device_is_compatible(nd, "pci106b,18") || |
1033 | of_device_is_compatible(nd, "pci106b,30") || | |
1034 | of_device_is_compatible(nd, "pci11c1,5811")) | |
1035 | && of_device_is_compatible(nd->parent, "uni-north")) { | |
14cf11af PM |
1036 | pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); |
1037 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); | |
1038 | } | |
14cf11af | 1039 | } |
30686ba6 | 1040 | for_each_node_by_name(nd, "ethernet") { |
55b61fec SR |
1041 | if (nd->parent && of_device_is_compatible(nd, "gmac") |
1042 | && of_device_is_compatible(nd->parent, "uni-north")) | |
14cf11af | 1043 | pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); |
14cf11af PM |
1044 | } |
1045 | } | |
1046 | ||
14cf11af PM |
1047 | void pmac_pci_fixup_cardbus(struct pci_dev* dev) |
1048 | { | |
e8222502 | 1049 | if (!machine_is(powermac)) |
14cf11af PM |
1050 | return; |
1051 | /* | |
1052 | * Fix the interrupt routing on the various cardbus bridges | |
1053 | * used on powerbooks | |
1054 | */ | |
1055 | if (dev->vendor != PCI_VENDOR_ID_TI) | |
1056 | return; | |
1057 | if (dev->device == PCI_DEVICE_ID_TI_1130 || | |
1058 | dev->device == PCI_DEVICE_ID_TI_1131) { | |
1059 | u8 val; | |
35499c01 | 1060 | /* Enable PCI interrupt */ |
14cf11af PM |
1061 | if (pci_read_config_byte(dev, 0x91, &val) == 0) |
1062 | pci_write_config_byte(dev, 0x91, val | 0x30); | |
1063 | /* Disable ISA interrupt mode */ | |
1064 | if (pci_read_config_byte(dev, 0x92, &val) == 0) | |
1065 | pci_write_config_byte(dev, 0x92, val & ~0x06); | |
1066 | } | |
1067 | if (dev->device == PCI_DEVICE_ID_TI_1210 || | |
1068 | dev->device == PCI_DEVICE_ID_TI_1211 || | |
1069 | dev->device == PCI_DEVICE_ID_TI_1410 || | |
1070 | dev->device == PCI_DEVICE_ID_TI_1510) { | |
1071 | u8 val; | |
1072 | /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA | |
1073 | signal out the MFUNC0 pin */ | |
1074 | if (pci_read_config_byte(dev, 0x8c, &val) == 0) | |
1075 | pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); | |
1076 | /* Disable ISA interrupt mode */ | |
1077 | if (pci_read_config_byte(dev, 0x92, &val) == 0) | |
1078 | pci_write_config_byte(dev, 0x92, val & ~0x06); | |
1079 | } | |
1080 | } | |
1081 | ||
1082 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); | |
1083 | ||
1084 | void pmac_pci_fixup_pciata(struct pci_dev* dev) | |
1085 | { | |
1086 | u8 progif = 0; | |
1087 | ||
1088 | /* | |
1089 | * On PowerMacs, we try to switch any PCI ATA controller to | |
1090 | * fully native mode | |
1091 | */ | |
e8222502 | 1092 | if (!machine_is(powermac)) |
14cf11af | 1093 | return; |
e8222502 | 1094 | |
14cf11af PM |
1095 | /* Some controllers don't have the class IDE */ |
1096 | if (dev->vendor == PCI_VENDOR_ID_PROMISE) | |
1097 | switch(dev->device) { | |
1098 | case PCI_DEVICE_ID_PROMISE_20246: | |
1099 | case PCI_DEVICE_ID_PROMISE_20262: | |
1100 | case PCI_DEVICE_ID_PROMISE_20263: | |
1101 | case PCI_DEVICE_ID_PROMISE_20265: | |
1102 | case PCI_DEVICE_ID_PROMISE_20267: | |
1103 | case PCI_DEVICE_ID_PROMISE_20268: | |
1104 | case PCI_DEVICE_ID_PROMISE_20269: | |
1105 | case PCI_DEVICE_ID_PROMISE_20270: | |
1106 | case PCI_DEVICE_ID_PROMISE_20271: | |
1107 | case PCI_DEVICE_ID_PROMISE_20275: | |
1108 | case PCI_DEVICE_ID_PROMISE_20276: | |
1109 | case PCI_DEVICE_ID_PROMISE_20277: | |
1110 | goto good; | |
1111 | } | |
1112 | /* Others, check PCI class */ | |
1113 | if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) | |
1114 | return; | |
1115 | good: | |
1116 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
1117 | if ((progif & 5) != 5) { | |
6d98bda7 | 1118 | printk(KERN_INFO "PCI: %s Forcing PCI IDE into native mode\n", |
1beb6a7d | 1119 | pci_name(dev)); |
14cf11af PM |
1120 | (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); |
1121 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
1122 | (progif & 5) != 5) | |
1123 | printk(KERN_ERR "Rewrite of PROGIF failed !\n"); | |
6d98bda7 BH |
1124 | else { |
1125 | /* Clear IO BARs, they will be reassigned */ | |
1126 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0); | |
1127 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0); | |
1128 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0); | |
1129 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, 0); | |
1130 | } | |
14cf11af PM |
1131 | } |
1132 | } | |
6d98bda7 | 1133 | DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); |
bc0826cf | 1134 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
1135 | |
1136 | /* | |
1137 | * Disable second function on K2-SATA, it's broken | |
1138 | * and disable IO BARs on first one | |
1139 | */ | |
1140 | static void fixup_k2_sata(struct pci_dev* dev) | |
1141 | { | |
1142 | int i; | |
1143 | u16 cmd; | |
1144 | ||
1145 | if (PCI_FUNC(dev->devfn) > 0) { | |
1146 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1147 | cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); | |
1148 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1149 | for (i = 0; i < 6; i++) { | |
1150 | dev->resource[i].start = dev->resource[i].end = 0; | |
1151 | dev->resource[i].flags = 0; | |
1beb6a7d BH |
1152 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, |
1153 | 0); | |
14cf11af PM |
1154 | } |
1155 | } else { | |
1156 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1157 | cmd &= ~PCI_COMMAND_IO; | |
1158 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1159 | for (i = 0; i < 5; i++) { | |
1160 | dev->resource[i].start = dev->resource[i].end = 0; | |
1161 | dev->resource[i].flags = 0; | |
1beb6a7d BH |
1162 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, |
1163 | 0); | |
14cf11af PM |
1164 | } |
1165 | } | |
1166 | } | |
1167 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata); | |
1168 | ||
cede3930 BH |
1169 | /* |
1170 | * On U4 (aka CPC945) the PCIe root complex "P2P" bridge resource ranges aren't | |
1171 | * configured by the firmware. The bridge itself seems to ignore them but it | |
1172 | * causes problems with Linux which then re-assigns devices below the bridge, | |
1173 | * thus changing addresses of those devices from what was in the device-tree, | |
1174 | * which sucks when those are video cards using offb | |
1175 | * | |
1176 | * We could just mark it transparent but I prefer fixing up the resources to | |
1177 | * properly show what's going on here, as I have some doubts about having them | |
1178 | * badly configured potentially being an issue for DMA. | |
1179 | * | |
1180 | * We leave PIO alone, it seems to be fine | |
1181 | * | |
1182 | * Oh and there's another funny bug. The OF properties advertize the region | |
1183 | * 0xf1000000..0xf1ffffff as being forwarded as memory space. But that's | |
1184 | * actually not true, this region is the memory mapped config space. So we | |
1185 | * also need to filter it out or we'll map things in the wrong place. | |
1186 | */ | |
1187 | static void fixup_u4_pcie(struct pci_dev* dev) | |
1188 | { | |
1189 | struct pci_controller *host = pci_bus_to_host(dev->bus); | |
1190 | struct resource *region = NULL; | |
1191 | u32 reg; | |
1192 | int i; | |
1193 | ||
1194 | /* Only do that on PowerMac */ | |
1195 | if (!machine_is(powermac)) | |
1196 | return; | |
1197 | ||
1198 | /* Find the largest MMIO region */ | |
1199 | for (i = 0; i < 3; i++) { | |
1200 | struct resource *r = &host->mem_resources[i]; | |
1201 | if (!(r->flags & IORESOURCE_MEM)) | |
1202 | continue; | |
1203 | /* Skip the 0xf0xxxxxx..f2xxxxxx regions, we know they | |
1204 | * are reserved by HW for other things | |
1205 | */ | |
1206 | if (r->start >= 0xf0000000 && r->start < 0xf3000000) | |
1207 | continue; | |
28f65c11 | 1208 | if (!region || resource_size(r) > resource_size(region)) |
cede3930 BH |
1209 | region = r; |
1210 | } | |
1211 | /* Nothing found, bail */ | |
1212 | if (region == 0) | |
1213 | return; | |
1214 | ||
1215 | /* Print things out */ | |
1216 | printk(KERN_INFO "PCI: Fixup U4 PCIe bridge range: %pR\n", region); | |
1217 | ||
1218 | /* Fixup bridge config space. We know it's a Mac, resource aren't | |
1219 | * offset so let's just blast them as-is. We also know that they | |
1220 | * fit in 32 bits | |
1221 | */ | |
1222 | reg = ((region->start >> 16) & 0xfff0) | (region->end & 0xfff00000); | |
1223 | pci_write_config_dword(dev, PCI_MEMORY_BASE, reg); | |
1224 | pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0); | |
1225 | pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); | |
1226 | pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0); | |
1227 | } | |
1228 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_U4_PCIE, fixup_u4_pcie); | |
ba9c8f22 DA |
1229 | |
1230 | #ifdef CONFIG_PPC64 | |
e63f26d3 | 1231 | static int pmac_pci_probe_mode(struct pci_bus *bus) |
ba9c8f22 DA |
1232 | { |
1233 | struct device_node *node = pci_bus_to_OF_node(bus); | |
1234 | ||
1235 | /* We need to use normal PCI probing for the AGP bus, | |
1236 | * since the device for the AGP bridge isn't in the tree. | |
1237 | * Same for the PCIe host on U4 and the HT host bridge. | |
1238 | */ | |
1239 | if (bus->self == NULL && (of_device_is_compatible(node, "u3-agp") || | |
1240 | of_device_is_compatible(node, "u4-pcie") || | |
1241 | of_device_is_compatible(node, "u3-ht"))) | |
1242 | return PCI_PROBE_NORMAL; | |
1243 | return PCI_PROBE_DEVTREE; | |
1244 | } | |
1245 | #endif /* CONFIG_PPC64 */ | |
e63f26d3 DA |
1246 | |
1247 | struct pci_controller_ops pmac_pci_controller_ops = { | |
1248 | #ifdef CONFIG_PPC64 | |
1249 | .probe_mode = pmac_pci_probe_mode, | |
1250 | #endif | |
1251 | #ifdef CONFIG_PPC32 | |
1252 | .enable_device_hook = pmac_pci_enable_device_hook, | |
1253 | #endif | |
1254 | }; | |
1255 |