Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * Support for PCI bridges found on Power Macintoshes. | |
14cf11af | 3 | * |
1beb6a7d | 4 | * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org) |
14cf11af PM |
5 | * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/string.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/bootmem.h> | |
19 | ||
20 | #include <asm/sections.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/prom.h> | |
23 | #include <asm/pci-bridge.h> | |
24 | #include <asm/machdep.h> | |
25 | #include <asm/pmac_feature.h> | |
830825d6 | 26 | #include <asm/grackle.h> |
3c3f42d6 | 27 | #ifdef CONFIG_PPC64 |
1beb6a7d | 28 | //#include <asm/iommu.h> |
3c3f42d6 PM |
29 | #include <asm/ppc-pci.h> |
30 | #endif | |
14cf11af PM |
31 | |
32 | #undef DEBUG | |
33 | ||
34 | #ifdef DEBUG | |
35 | #define DBG(x...) printk(x) | |
36 | #else | |
37 | #define DBG(x...) | |
38 | #endif | |
39 | ||
40 | static int add_bridge(struct device_node *dev); | |
14cf11af PM |
41 | |
42 | /* XXX Could be per-controller, but I don't think we risk anything by | |
43 | * assuming we won't have both UniNorth and Bandit */ | |
44 | static int has_uninorth; | |
35499c01 | 45 | #ifdef CONFIG_PPC64 |
14cf11af | 46 | static struct pci_controller *u3_agp; |
1beb6a7d | 47 | static struct pci_controller *u4_pcie; |
35499c01 PM |
48 | static struct pci_controller *u3_ht; |
49 | #endif /* CONFIG_PPC64 */ | |
14cf11af PM |
50 | |
51 | extern u8 pci_cache_line_size; | |
52 | extern int pcibios_assign_bus_offset; | |
53 | ||
54 | struct device_node *k2_skiplist[2]; | |
55 | ||
56 | /* | |
57 | * Magic constants for enabling cache coherency in the bandit/PSX bridge. | |
58 | */ | |
59 | #define BANDIT_DEVID_2 8 | |
60 | #define BANDIT_REVID 3 | |
61 | ||
62 | #define BANDIT_DEVNUM 11 | |
63 | #define BANDIT_MAGIC 0x50 | |
64 | #define BANDIT_COHERENT 0x40 | |
65 | ||
66 | static int __init fixup_one_level_bus_range(struct device_node *node, int higher) | |
67 | { | |
68 | for (; node != 0;node = node->sibling) { | |
69 | int * bus_range; | |
70 | unsigned int *class_code; | |
71 | int len; | |
72 | ||
73 | /* For PCI<->PCI bridges or CardBus bridges, we go down */ | |
74 | class_code = (unsigned int *) get_property(node, "class-code", NULL); | |
75 | if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && | |
76 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) | |
77 | continue; | |
78 | bus_range = (int *) get_property(node, "bus-range", &len); | |
79 | if (bus_range != NULL && len > 2 * sizeof(int)) { | |
80 | if (bus_range[1] > higher) | |
81 | higher = bus_range[1]; | |
82 | } | |
83 | higher = fixup_one_level_bus_range(node->child, higher); | |
84 | } | |
85 | return higher; | |
86 | } | |
87 | ||
88 | /* This routine fixes the "bus-range" property of all bridges in the | |
89 | * system since they tend to have their "last" member wrong on macs | |
90 | * | |
91 | * Note that the bus numbers manipulated here are OF bus numbers, they | |
92 | * are not Linux bus numbers. | |
93 | */ | |
94 | static void __init fixup_bus_range(struct device_node *bridge) | |
95 | { | |
96 | int * bus_range; | |
97 | int len; | |
98 | ||
99 | /* Lookup the "bus-range" property for the hose */ | |
100 | bus_range = (int *) get_property(bridge, "bus-range", &len); | |
1beb6a7d | 101 | if (bus_range == NULL || len < 2 * sizeof(int)) |
14cf11af | 102 | return; |
14cf11af PM |
103 | bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); |
104 | } | |
105 | ||
106 | /* | |
107 | * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. | |
108 | * | |
109 | * The "Bandit" version is present in all early PCI PowerMacs, | |
110 | * and up to the first ones using Grackle. Some machines may | |
111 | * have 2 bandit controllers (2 PCI busses). | |
112 | * | |
113 | * "Chaos" is used in some "Bandit"-type machines as a bridge | |
114 | * for the separate display bus. It is accessed the same | |
115 | * way as bandit, but cannot be probed for devices. It therefore | |
116 | * has its own config access functions. | |
117 | * | |
118 | * The "UniNorth" version is present in all Core99 machines | |
119 | * (iBook, G4, new IMacs, and all the recent Apple machines). | |
120 | * It contains 3 controllers in one ASIC. | |
121 | * | |
122 | * The U3 is the bridge used on G5 machines. It contains an | |
123 | * AGP bus which is dealt with the old UniNorth access routines | |
124 | * and a HyperTransport bus which uses its own set of access | |
125 | * functions. | |
126 | */ | |
127 | ||
128 | #define MACRISC_CFA0(devfn, off) \ | |
1beb6a7d BH |
129 | ((1 << (unsigned int)PCI_SLOT(dev_fn)) \ |
130 | | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ | |
131 | | (((unsigned int)(off)) & 0xFCUL)) | |
14cf11af PM |
132 | |
133 | #define MACRISC_CFA1(bus, devfn, off) \ | |
1beb6a7d BH |
134 | ((((unsigned int)(bus)) << 16) \ |
135 | |(((unsigned int)(devfn)) << 8) \ | |
136 | |(((unsigned int)(off)) & 0xFCUL) \ | |
14cf11af PM |
137 | |1UL) |
138 | ||
139 | static unsigned long macrisc_cfg_access(struct pci_controller* hose, | |
140 | u8 bus, u8 dev_fn, u8 offset) | |
141 | { | |
142 | unsigned int caddr; | |
143 | ||
144 | if (bus == hose->first_busno) { | |
145 | if (dev_fn < (11 << 3)) | |
146 | return 0; | |
147 | caddr = MACRISC_CFA0(dev_fn, offset); | |
148 | } else | |
149 | caddr = MACRISC_CFA1(bus, dev_fn, offset); | |
150 | ||
151 | /* Uninorth will return garbage if we don't read back the value ! */ | |
152 | do { | |
153 | out_le32(hose->cfg_addr, caddr); | |
154 | } while (in_le32(hose->cfg_addr) != caddr); | |
155 | ||
156 | offset &= has_uninorth ? 0x07 : 0x03; | |
157 | return ((unsigned long)hose->cfg_data) + offset; | |
158 | } | |
159 | ||
160 | static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, | |
161 | int offset, int len, u32 *val) | |
162 | { | |
3c3f42d6 | 163 | struct pci_controller *hose; |
14cf11af PM |
164 | unsigned long addr; |
165 | ||
3c3f42d6 PM |
166 | hose = pci_bus_to_host(bus); |
167 | if (hose == NULL) | |
168 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1beb6a7d BH |
169 | if (offset >= 0x100) |
170 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
14cf11af PM |
171 | addr = macrisc_cfg_access(hose, bus->number, devfn, offset); |
172 | if (!addr) | |
173 | return PCIBIOS_DEVICE_NOT_FOUND; | |
174 | /* | |
175 | * Note: the caller has already checked that offset is | |
176 | * suitably aligned and that len is 1, 2 or 4. | |
177 | */ | |
178 | switch (len) { | |
179 | case 1: | |
180 | *val = in_8((u8 *)addr); | |
181 | break; | |
182 | case 2: | |
183 | *val = in_le16((u16 *)addr); | |
184 | break; | |
185 | default: | |
186 | *val = in_le32((u32 *)addr); | |
187 | break; | |
188 | } | |
189 | return PCIBIOS_SUCCESSFUL; | |
190 | } | |
191 | ||
192 | static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, | |
193 | int offset, int len, u32 val) | |
194 | { | |
3c3f42d6 | 195 | struct pci_controller *hose; |
14cf11af PM |
196 | unsigned long addr; |
197 | ||
3c3f42d6 PM |
198 | hose = pci_bus_to_host(bus); |
199 | if (hose == NULL) | |
200 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1beb6a7d BH |
201 | if (offset >= 0x100) |
202 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
14cf11af PM |
203 | addr = macrisc_cfg_access(hose, bus->number, devfn, offset); |
204 | if (!addr) | |
205 | return PCIBIOS_DEVICE_NOT_FOUND; | |
206 | /* | |
207 | * Note: the caller has already checked that offset is | |
208 | * suitably aligned and that len is 1, 2 or 4. | |
209 | */ | |
210 | switch (len) { | |
211 | case 1: | |
212 | out_8((u8 *)addr, val); | |
213 | (void) in_8((u8 *)addr); | |
214 | break; | |
215 | case 2: | |
216 | out_le16((u16 *)addr, val); | |
217 | (void) in_le16((u16 *)addr); | |
218 | break; | |
219 | default: | |
220 | out_le32((u32 *)addr, val); | |
221 | (void) in_le32((u32 *)addr); | |
222 | break; | |
223 | } | |
224 | return PCIBIOS_SUCCESSFUL; | |
225 | } | |
226 | ||
227 | static struct pci_ops macrisc_pci_ops = | |
228 | { | |
229 | macrisc_read_config, | |
230 | macrisc_write_config | |
231 | }; | |
232 | ||
35499c01 | 233 | #ifdef CONFIG_PPC32 |
14cf11af | 234 | /* |
3c3f42d6 | 235 | * Verify that a specific (bus, dev_fn) exists on chaos |
14cf11af | 236 | */ |
1beb6a7d | 237 | static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset) |
14cf11af PM |
238 | { |
239 | struct device_node *np; | |
240 | u32 *vendor, *device; | |
241 | ||
1beb6a7d BH |
242 | if (offset >= 0x100) |
243 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
14cf11af PM |
244 | np = pci_busdev_to_OF_node(bus, devfn); |
245 | if (np == NULL) | |
246 | return PCIBIOS_DEVICE_NOT_FOUND; | |
247 | ||
248 | vendor = (u32 *)get_property(np, "vendor-id", NULL); | |
249 | device = (u32 *)get_property(np, "device-id", NULL); | |
250 | if (vendor == NULL || device == NULL) | |
251 | return PCIBIOS_DEVICE_NOT_FOUND; | |
252 | ||
253 | if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) | |
254 | && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) | |
255 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
256 | ||
257 | return PCIBIOS_SUCCESSFUL; | |
258 | } | |
259 | ||
260 | static int | |
261 | chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
262 | int len, u32 *val) | |
263 | { | |
264 | int result = chaos_validate_dev(bus, devfn, offset); | |
265 | if (result == PCIBIOS_BAD_REGISTER_NUMBER) | |
266 | *val = ~0U; | |
267 | if (result != PCIBIOS_SUCCESSFUL) | |
268 | return result; | |
269 | return macrisc_read_config(bus, devfn, offset, len, val); | |
270 | } | |
271 | ||
272 | static int | |
273 | chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
274 | int len, u32 val) | |
275 | { | |
276 | int result = chaos_validate_dev(bus, devfn, offset); | |
277 | if (result != PCIBIOS_SUCCESSFUL) | |
278 | return result; | |
279 | return macrisc_write_config(bus, devfn, offset, len, val); | |
280 | } | |
281 | ||
282 | static struct pci_ops chaos_pci_ops = | |
283 | { | |
284 | chaos_read_config, | |
285 | chaos_write_config | |
286 | }; | |
287 | ||
35499c01 | 288 | static void __init setup_chaos(struct pci_controller *hose, |
cc5d0189 | 289 | struct resource *addr) |
35499c01 PM |
290 | { |
291 | /* assume a `chaos' bridge */ | |
292 | hose->ops = &chaos_pci_ops; | |
cc5d0189 BH |
293 | hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); |
294 | hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); | |
35499c01 | 295 | } |
35499c01 PM |
296 | #endif /* CONFIG_PPC32 */ |
297 | ||
298 | #ifdef CONFIG_PPC64 | |
14cf11af PM |
299 | /* |
300 | * These versions of U3 HyperTransport config space access ops do not | |
301 | * implement self-view of the HT host yet | |
302 | */ | |
303 | ||
304 | /* | |
305 | * This function deals with some "special cases" devices. | |
306 | * | |
307 | * 0 -> No special case | |
308 | * 1 -> Skip the device but act as if the access was successfull | |
309 | * (return 0xff's on reads, eventually, cache config space | |
310 | * accesses in a later version) | |
311 | * -1 -> Hide the device (unsuccessful acess) | |
312 | */ | |
313 | static int u3_ht_skip_device(struct pci_controller *hose, | |
314 | struct pci_bus *bus, unsigned int devfn) | |
315 | { | |
316 | struct device_node *busdn, *dn; | |
317 | int i; | |
318 | ||
319 | /* We only allow config cycles to devices that are in OF device-tree | |
320 | * as we are apparently having some weird things going on with some | |
321 | * revs of K2 on recent G5s | |
322 | */ | |
323 | if (bus->self) | |
324 | busdn = pci_device_to_OF_node(bus->self); | |
325 | else | |
326 | busdn = hose->arch_data; | |
327 | for (dn = busdn->child; dn; dn = dn->sibling) | |
e07102db | 328 | if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn) |
14cf11af PM |
329 | break; |
330 | if (dn == NULL) | |
331 | return -1; | |
332 | ||
333 | /* | |
334 | * When a device in K2 is powered down, we die on config | |
335 | * cycle accesses. Fix that here. | |
336 | */ | |
337 | for (i=0; i<2; i++) | |
338 | if (k2_skiplist[i] == dn) | |
339 | return 1; | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
344 | #define U3_HT_CFA0(devfn, off) \ | |
1beb6a7d | 345 | ((((unsigned int)devfn) << 8) | offset) |
14cf11af PM |
346 | #define U3_HT_CFA1(bus, devfn, off) \ |
347 | (U3_HT_CFA0(devfn, off) \ | |
1beb6a7d | 348 | + (((unsigned int)bus) << 16) \ |
14cf11af PM |
349 | + 0x01000000UL) |
350 | ||
351 | static unsigned long u3_ht_cfg_access(struct pci_controller* hose, | |
352 | u8 bus, u8 devfn, u8 offset) | |
353 | { | |
354 | if (bus == hose->first_busno) { | |
355 | /* For now, we don't self probe U3 HT bridge */ | |
356 | if (PCI_SLOT(devfn) == 0) | |
357 | return 0; | |
cc5d0189 BH |
358 | return ((unsigned long)hose->cfg_data) + |
359 | U3_HT_CFA0(devfn, offset); | |
14cf11af | 360 | } else |
cc5d0189 BH |
361 | return ((unsigned long)hose->cfg_data) + |
362 | U3_HT_CFA1(bus, devfn, offset); | |
14cf11af PM |
363 | } |
364 | ||
365 | static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, | |
366 | int offset, int len, u32 *val) | |
367 | { | |
3c3f42d6 | 368 | struct pci_controller *hose; |
14cf11af PM |
369 | unsigned long addr; |
370 | ||
3c3f42d6 PM |
371 | hose = pci_bus_to_host(bus); |
372 | if (hose == NULL) | |
14cf11af | 373 | return PCIBIOS_DEVICE_NOT_FOUND; |
1beb6a7d BH |
374 | if (offset >= 0x100) |
375 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
14cf11af PM |
376 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); |
377 | if (!addr) | |
378 | return PCIBIOS_DEVICE_NOT_FOUND; | |
379 | ||
380 | switch (u3_ht_skip_device(hose, bus, devfn)) { | |
381 | case 0: | |
382 | break; | |
383 | case 1: | |
3c3f42d6 PM |
384 | switch (len) { |
385 | case 1: | |
386 | *val = 0xff; break; | |
387 | case 2: | |
388 | *val = 0xffff; break; | |
389 | default: | |
390 | *val = 0xfffffffful; break; | |
391 | } | |
392 | return PCIBIOS_SUCCESSFUL; | |
14cf11af PM |
393 | default: |
394 | return PCIBIOS_DEVICE_NOT_FOUND; | |
3c3f42d6 PM |
395 | } |
396 | ||
14cf11af PM |
397 | /* |
398 | * Note: the caller has already checked that offset is | |
399 | * suitably aligned and that len is 1, 2 or 4. | |
400 | */ | |
401 | switch (len) { | |
402 | case 1: | |
403 | *val = in_8((u8 *)addr); | |
404 | break; | |
405 | case 2: | |
406 | *val = in_le16((u16 *)addr); | |
407 | break; | |
408 | default: | |
409 | *val = in_le32((u32 *)addr); | |
410 | break; | |
411 | } | |
412 | return PCIBIOS_SUCCESSFUL; | |
413 | } | |
414 | ||
415 | static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, | |
416 | int offset, int len, u32 val) | |
417 | { | |
3c3f42d6 | 418 | struct pci_controller *hose; |
14cf11af PM |
419 | unsigned long addr; |
420 | ||
3c3f42d6 PM |
421 | hose = pci_bus_to_host(bus); |
422 | if (hose == NULL) | |
14cf11af | 423 | return PCIBIOS_DEVICE_NOT_FOUND; |
1beb6a7d BH |
424 | if (offset >= 0x100) |
425 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
14cf11af PM |
426 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); |
427 | if (!addr) | |
428 | return PCIBIOS_DEVICE_NOT_FOUND; | |
429 | ||
430 | switch (u3_ht_skip_device(hose, bus, devfn)) { | |
431 | case 0: | |
432 | break; | |
433 | case 1: | |
434 | return PCIBIOS_SUCCESSFUL; | |
435 | default: | |
436 | return PCIBIOS_DEVICE_NOT_FOUND; | |
437 | } | |
438 | ||
439 | /* | |
440 | * Note: the caller has already checked that offset is | |
441 | * suitably aligned and that len is 1, 2 or 4. | |
442 | */ | |
443 | switch (len) { | |
444 | case 1: | |
445 | out_8((u8 *)addr, val); | |
446 | (void) in_8((u8 *)addr); | |
447 | break; | |
448 | case 2: | |
449 | out_le16((u16 *)addr, val); | |
450 | (void) in_le16((u16 *)addr); | |
451 | break; | |
452 | default: | |
453 | out_le32((u32 *)addr, val); | |
454 | (void) in_le32((u32 *)addr); | |
455 | break; | |
456 | } | |
457 | return PCIBIOS_SUCCESSFUL; | |
458 | } | |
459 | ||
460 | static struct pci_ops u3_ht_pci_ops = | |
461 | { | |
462 | u3_ht_read_config, | |
463 | u3_ht_write_config | |
464 | }; | |
1beb6a7d BH |
465 | |
466 | #define U4_PCIE_CFA0(devfn, off) \ | |
467 | ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \ | |
468 | | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ | |
469 | | ((((unsigned int)(off)) >> 8) << 28) \ | |
470 | | (((unsigned int)(off)) & 0xfcU)) | |
471 | ||
472 | #define U4_PCIE_CFA1(bus, devfn, off) \ | |
473 | ((((unsigned int)(bus)) << 16) \ | |
474 | |(((unsigned int)(devfn)) << 8) \ | |
475 | | ((((unsigned int)(off)) >> 8) << 28) \ | |
476 | |(((unsigned int)(off)) & 0xfcU) \ | |
477 | |1UL) | |
478 | ||
479 | static unsigned long u4_pcie_cfg_access(struct pci_controller* hose, | |
480 | u8 bus, u8 dev_fn, int offset) | |
481 | { | |
482 | unsigned int caddr; | |
483 | ||
484 | if (bus == hose->first_busno) { | |
485 | caddr = U4_PCIE_CFA0(dev_fn, offset); | |
486 | } else | |
487 | caddr = U4_PCIE_CFA1(bus, dev_fn, offset); | |
488 | ||
489 | /* Uninorth will return garbage if we don't read back the value ! */ | |
490 | do { | |
491 | out_le32(hose->cfg_addr, caddr); | |
492 | } while (in_le32(hose->cfg_addr) != caddr); | |
493 | ||
494 | offset &= 0x03; | |
495 | return ((unsigned long)hose->cfg_data) + offset; | |
496 | } | |
497 | ||
498 | static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, | |
499 | int offset, int len, u32 *val) | |
500 | { | |
501 | struct pci_controller *hose; | |
502 | unsigned long addr; | |
503 | ||
504 | hose = pci_bus_to_host(bus); | |
505 | if (hose == NULL) | |
506 | return PCIBIOS_DEVICE_NOT_FOUND; | |
507 | if (offset >= 0x1000) | |
508 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
509 | addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); | |
510 | if (!addr) | |
511 | return PCIBIOS_DEVICE_NOT_FOUND; | |
512 | /* | |
513 | * Note: the caller has already checked that offset is | |
514 | * suitably aligned and that len is 1, 2 or 4. | |
515 | */ | |
516 | switch (len) { | |
517 | case 1: | |
518 | *val = in_8((u8 *)addr); | |
519 | break; | |
520 | case 2: | |
521 | *val = in_le16((u16 *)addr); | |
522 | break; | |
523 | default: | |
524 | *val = in_le32((u32 *)addr); | |
525 | break; | |
526 | } | |
527 | return PCIBIOS_SUCCESSFUL; | |
528 | } | |
529 | ||
530 | static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, | |
531 | int offset, int len, u32 val) | |
532 | { | |
533 | struct pci_controller *hose; | |
534 | unsigned long addr; | |
535 | ||
536 | hose = pci_bus_to_host(bus); | |
537 | if (hose == NULL) | |
538 | return PCIBIOS_DEVICE_NOT_FOUND; | |
539 | if (offset >= 0x1000) | |
540 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
541 | addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); | |
542 | if (!addr) | |
543 | return PCIBIOS_DEVICE_NOT_FOUND; | |
544 | /* | |
545 | * Note: the caller has already checked that offset is | |
546 | * suitably aligned and that len is 1, 2 or 4. | |
547 | */ | |
548 | switch (len) { | |
549 | case 1: | |
550 | out_8((u8 *)addr, val); | |
551 | (void) in_8((u8 *)addr); | |
552 | break; | |
553 | case 2: | |
554 | out_le16((u16 *)addr, val); | |
555 | (void) in_le16((u16 *)addr); | |
556 | break; | |
557 | default: | |
558 | out_le32((u32 *)addr, val); | |
559 | (void) in_le32((u32 *)addr); | |
560 | break; | |
561 | } | |
562 | return PCIBIOS_SUCCESSFUL; | |
563 | } | |
564 | ||
565 | static struct pci_ops u4_pcie_pci_ops = | |
566 | { | |
567 | u4_pcie_read_config, | |
568 | u4_pcie_write_config | |
569 | }; | |
570 | ||
35499c01 | 571 | #endif /* CONFIG_PPC64 */ |
14cf11af | 572 | |
35499c01 | 573 | #ifdef CONFIG_PPC32 |
14cf11af PM |
574 | /* |
575 | * For a bandit bridge, turn on cache coherency if necessary. | |
576 | * N.B. we could clean this up using the hose ops directly. | |
577 | */ | |
3c3f42d6 | 578 | static void __init init_bandit(struct pci_controller *bp) |
14cf11af PM |
579 | { |
580 | unsigned int vendev, magic; | |
581 | int rev; | |
582 | ||
583 | /* read the word at offset 0 in config space for device 11 */ | |
584 | out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); | |
585 | udelay(2); | |
586 | vendev = in_le32(bp->cfg_data); | |
587 | if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + | |
588 | PCI_VENDOR_ID_APPLE) { | |
589 | /* read the revision id */ | |
590 | out_le32(bp->cfg_addr, | |
591 | (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); | |
592 | udelay(2); | |
593 | rev = in_8(bp->cfg_data); | |
594 | if (rev != BANDIT_REVID) | |
595 | printk(KERN_WARNING | |
596 | "Unknown revision %d for bandit\n", rev); | |
597 | } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { | |
598 | printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); | |
599 | return; | |
600 | } | |
601 | ||
602 | /* read the word at offset 0x50 */ | |
603 | out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); | |
604 | udelay(2); | |
605 | magic = in_le32(bp->cfg_data); | |
606 | if ((magic & BANDIT_COHERENT) != 0) | |
607 | return; | |
608 | magic |= BANDIT_COHERENT; | |
609 | udelay(2); | |
610 | out_le32(bp->cfg_data, magic); | |
611 | printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); | |
612 | } | |
613 | ||
14cf11af PM |
614 | /* |
615 | * Tweak the PCI-PCI bridge chip on the blue & white G3s. | |
616 | */ | |
3c3f42d6 | 617 | static void __init init_p2pbridge(void) |
14cf11af PM |
618 | { |
619 | struct device_node *p2pbridge; | |
620 | struct pci_controller* hose; | |
621 | u8 bus, devfn; | |
622 | u16 val; | |
623 | ||
624 | /* XXX it would be better here to identify the specific | |
625 | PCI-PCI bridge chip we have. */ | |
626 | if ((p2pbridge = find_devices("pci-bridge")) == 0 | |
627 | || p2pbridge->parent == NULL | |
628 | || strcmp(p2pbridge->parent->name, "pci") != 0) | |
629 | return; | |
630 | if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { | |
631 | DBG("Can't find PCI infos for PCI<->PCI bridge\n"); | |
632 | return; | |
633 | } | |
634 | /* Warning: At this point, we have not yet renumbered all busses. | |
635 | * So we must use OF walking to find out hose | |
636 | */ | |
637 | hose = pci_find_hose_for_OF_device(p2pbridge); | |
638 | if (!hose) { | |
639 | DBG("Can't find hose for PCI<->PCI bridge\n"); | |
640 | return; | |
641 | } | |
642 | if (early_read_config_word(hose, bus, devfn, | |
643 | PCI_BRIDGE_CONTROL, &val) < 0) { | |
cc5d0189 BH |
644 | printk(KERN_ERR "init_p2pbridge: couldn't read bridge" |
645 | " control\n"); | |
14cf11af PM |
646 | return; |
647 | } | |
648 | val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; | |
649 | early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); | |
650 | } | |
651 | ||
652 | /* | |
653 | * Some Apple desktop machines have a NEC PD720100A USB2 controller | |
654 | * on the motherboard. Open Firmware, on these, will disable the | |
655 | * EHCI part of it so it behaves like a pair of OHCI's. This fixup | |
656 | * code re-enables it ;) | |
657 | */ | |
3c3f42d6 | 658 | static void __init fixup_nec_usb2(void) |
14cf11af PM |
659 | { |
660 | struct device_node *nec; | |
661 | ||
662 | for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) { | |
663 | struct pci_controller *hose; | |
664 | u32 data, *prop; | |
665 | u8 bus, devfn; | |
35499c01 | 666 | |
14cf11af PM |
667 | prop = (u32 *)get_property(nec, "vendor-id", NULL); |
668 | if (prop == NULL) | |
669 | continue; | |
670 | if (0x1033 != *prop) | |
671 | continue; | |
672 | prop = (u32 *)get_property(nec, "device-id", NULL); | |
673 | if (prop == NULL) | |
674 | continue; | |
675 | if (0x0035 != *prop) | |
676 | continue; | |
677 | prop = (u32 *)get_property(nec, "reg", NULL); | |
678 | if (prop == NULL) | |
679 | continue; | |
680 | devfn = (prop[0] >> 8) & 0xff; | |
681 | bus = (prop[0] >> 16) & 0xff; | |
682 | if (PCI_FUNC(devfn) != 0) | |
683 | continue; | |
684 | hose = pci_find_hose_for_OF_device(nec); | |
685 | if (!hose) | |
686 | continue; | |
687 | early_read_config_dword(hose, bus, devfn, 0xe4, &data); | |
688 | if (data & 1UL) { | |
cc5d0189 BH |
689 | printk("Found NEC PD720100A USB2 chip with disabled" |
690 | " EHCI, fixing up...\n"); | |
14cf11af PM |
691 | data &= ~1UL; |
692 | early_write_config_dword(hose, bus, devfn, 0xe4, data); | |
cc5d0189 BH |
693 | early_write_config_byte(hose, bus, |
694 | devfn | 2, PCI_INTERRUPT_LINE, | |
14cf11af PM |
695 | nec->intrs[0].line); |
696 | } | |
697 | } | |
698 | } | |
699 | ||
35499c01 | 700 | static void __init setup_bandit(struct pci_controller *hose, |
cc5d0189 | 701 | struct resource *addr) |
14cf11af PM |
702 | { |
703 | hose->ops = ¯isc_pci_ops; | |
cc5d0189 BH |
704 | hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); |
705 | hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); | |
14cf11af PM |
706 | init_bandit(hose); |
707 | } | |
708 | ||
35499c01 | 709 | static int __init setup_uninorth(struct pci_controller *hose, |
cc5d0189 | 710 | struct resource *addr) |
14cf11af | 711 | { |
35499c01 PM |
712 | pci_assign_all_buses = 1; |
713 | has_uninorth = 1; | |
714 | hose->ops = ¯isc_pci_ops; | |
cc5d0189 BH |
715 | hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); |
716 | hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); | |
35499c01 | 717 | /* We "know" that the bridge at f2000000 has the PCI slots. */ |
cc5d0189 | 718 | return addr->start == 0xf2000000; |
14cf11af | 719 | } |
cc5d0189 | 720 | #endif /* CONFIG_PPC32 */ |
14cf11af | 721 | |
35499c01 | 722 | #ifdef CONFIG_PPC64 |
14cf11af PM |
723 | static void __init setup_u3_agp(struct pci_controller* hose) |
724 | { | |
725 | /* On G5, we move AGP up to high bus number so we don't need | |
726 | * to reassign bus numbers for HT. If we ever have P2P bridges | |
35499c01 | 727 | * on AGP, we'll have to move pci_assign_all_busses to the |
14cf11af PM |
728 | * pci_controller structure so we enable it for AGP and not for |
729 | * HT childs. | |
730 | * We hard code the address because of the different size of | |
731 | * the reg address cell, we shall fix that by killing struct | |
732 | * reg_property and using some accessor functions instead | |
733 | */ | |
3c3f42d6 | 734 | hose->first_busno = 0xf0; |
14cf11af PM |
735 | hose->last_busno = 0xff; |
736 | has_uninorth = 1; | |
737 | hose->ops = ¯isc_pci_ops; | |
738 | hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); | |
739 | hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); | |
14cf11af PM |
740 | u3_agp = hose; |
741 | } | |
742 | ||
1beb6a7d BH |
743 | static void __init setup_u4_pcie(struct pci_controller* hose) |
744 | { | |
745 | /* We currently only implement the "non-atomic" config space, to | |
746 | * be optimised later. | |
747 | */ | |
748 | hose->ops = &u4_pcie_pci_ops; | |
749 | hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); | |
750 | hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); | |
751 | ||
752 | /* The bus contains a bridge from root -> device, we need to | |
753 | * make it visible on bus 0 so that we pick the right type | |
754 | * of config cycles. If we didn't, we would have to force all | |
755 | * config cycles to be type 1. So we override the "bus-range" | |
756 | * property here | |
757 | */ | |
758 | hose->first_busno = 0x00; | |
759 | hose->last_busno = 0xff; | |
760 | u4_pcie = hose; | |
761 | } | |
762 | ||
14cf11af PM |
763 | static void __init setup_u3_ht(struct pci_controller* hose) |
764 | { | |
765 | struct device_node *np = (struct device_node *)hose->arch_data; | |
1beb6a7d | 766 | struct pci_controller *other = NULL; |
14cf11af PM |
767 | int i, cur; |
768 | ||
1beb6a7d | 769 | |
14cf11af PM |
770 | hose->ops = &u3_ht_pci_ops; |
771 | ||
772 | /* We hard code the address because of the different size of | |
773 | * the reg address cell, we shall fix that by killing struct | |
774 | * reg_property and using some accessor functions instead | |
775 | */ | |
b5166cc2 BH |
776 | hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, |
777 | 0x02000000); | |
14cf11af PM |
778 | |
779 | /* | |
b5166cc2 BH |
780 | * /ht node doesn't expose a "ranges" property, so we "remove" |
781 | * regions that have been allocated to AGP. So far, this version of | |
782 | * the code doesn't assign any of the 0xfxxxxxxx "fine" memory regions | |
783 | * to /ht. We need to fix that sooner or later by either parsing all | |
784 | * child "ranges" properties or figuring out the U3 address space | |
785 | * decoding logic and then read its configuration register (if any). | |
14cf11af PM |
786 | */ |
787 | hose->io_base_phys = 0xf4000000; | |
35499c01 | 788 | hose->pci_io_size = 0x00400000; |
14cf11af PM |
789 | hose->io_resource.name = np->full_name; |
790 | hose->io_resource.start = 0; | |
791 | hose->io_resource.end = 0x003fffff; | |
792 | hose->io_resource.flags = IORESOURCE_IO; | |
793 | hose->pci_mem_offset = 0; | |
794 | hose->first_busno = 0; | |
795 | hose->last_busno = 0xef; | |
796 | hose->mem_resources[0].name = np->full_name; | |
797 | hose->mem_resources[0].start = 0x80000000; | |
798 | hose->mem_resources[0].end = 0xefffffff; | |
799 | hose->mem_resources[0].flags = IORESOURCE_MEM; | |
800 | ||
35499c01 PM |
801 | u3_ht = hose; |
802 | ||
1beb6a7d BH |
803 | if (u3_agp != NULL) |
804 | other = u3_agp; | |
805 | else if (u4_pcie != NULL) | |
806 | other = u4_pcie; | |
807 | ||
808 | if (other == NULL) { | |
809 | DBG("U3/4 has no AGP/PCIE, using full resource range\n"); | |
14cf11af PM |
810 | return; |
811 | } | |
812 | ||
1beb6a7d BH |
813 | /* Fixup bus range vs. PCIE */ |
814 | if (u4_pcie) | |
815 | hose->last_busno = u4_pcie->first_busno - 1; | |
816 | ||
b5166cc2 BH |
817 | /* We "remove" the AGP resources from the resources allocated to HT, |
818 | * that is we create "holes". However, that code does assumptions | |
819 | * that so far happen to be true (cross fingers...), typically that | |
820 | * resources in the AGP node are properly ordered | |
14cf11af PM |
821 | */ |
822 | cur = 0; | |
823 | for (i=0; i<3; i++) { | |
1beb6a7d | 824 | struct resource *res = &other->mem_resources[i]; |
14cf11af PM |
825 | if (res->flags != IORESOURCE_MEM) |
826 | continue; | |
827 | /* We don't care about "fine" resources */ | |
828 | if (res->start >= 0xf0000000) | |
829 | continue; | |
b5166cc2 BH |
830 | /* Check if it's just a matter of "shrinking" us in one |
831 | * direction | |
832 | */ | |
14cf11af PM |
833 | if (hose->mem_resources[cur].start == res->start) { |
834 | DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n", | |
b5166cc2 BH |
835 | cur, hose->mem_resources[cur].start, |
836 | res->end + 1); | |
14cf11af PM |
837 | hose->mem_resources[cur].start = res->end + 1; |
838 | continue; | |
839 | } | |
840 | if (hose->mem_resources[cur].end == res->end) { | |
841 | DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n", | |
b5166cc2 BH |
842 | cur, hose->mem_resources[cur].end, |
843 | res->start - 1); | |
14cf11af PM |
844 | hose->mem_resources[cur].end = res->start - 1; |
845 | continue; | |
846 | } | |
847 | /* No, it's not the case, we need a hole */ | |
848 | if (cur == 2) { | |
b5166cc2 BH |
849 | /* not enough resources for a hole, we drop part |
850 | * of the range | |
851 | */ | |
852 | printk(KERN_WARNING "Running out of resources" | |
853 | " for /ht host !\n"); | |
14cf11af PM |
854 | hose->mem_resources[cur].end = res->start - 1; |
855 | continue; | |
35499c01 | 856 | } |
14cf11af | 857 | cur++; |
3c3f42d6 | 858 | DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n", |
14cf11af PM |
859 | cur-1, res->start - 1, cur, res->end + 1); |
860 | hose->mem_resources[cur].name = np->full_name; | |
861 | hose->mem_resources[cur].flags = IORESOURCE_MEM; | |
862 | hose->mem_resources[cur].start = res->end + 1; | |
863 | hose->mem_resources[cur].end = hose->mem_resources[cur-1].end; | |
864 | hose->mem_resources[cur-1].end = res->start - 1; | |
865 | } | |
866 | } | |
cc5d0189 | 867 | #endif /* CONFIG_PPC64 */ |
14cf11af PM |
868 | |
869 | /* | |
870 | * We assume that if we have a G3 powermac, we have one bridge called | |
871 | * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, | |
872 | * if we have one or more bandit or chaos bridges, we don't have a MPC106. | |
873 | */ | |
874 | static int __init add_bridge(struct device_node *dev) | |
875 | { | |
876 | int len; | |
877 | struct pci_controller *hose; | |
cc5d0189 | 878 | struct resource rsrc; |
35499c01 | 879 | char *disp_name; |
14cf11af | 880 | int *bus_range; |
cc5d0189 | 881 | int primary = 1, has_address = 0; |
14cf11af PM |
882 | |
883 | DBG("Adding PCI host bridge %s\n", dev->full_name); | |
884 | ||
cc5d0189 BH |
885 | /* Fetch host bridge registers address */ |
886 | has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); | |
887 | ||
888 | /* Get bus range if any */ | |
35499c01 PM |
889 | bus_range = (int *) get_property(dev, "bus-range", &len); |
890 | if (bus_range == NULL || len < 2 * sizeof(int)) { | |
b5166cc2 BH |
891 | printk(KERN_WARNING "Can't get bus-range for %s, assume" |
892 | " bus 0\n", dev->full_name); | |
35499c01 PM |
893 | } |
894 | ||
b5166cc2 BH |
895 | /* XXX Different prototypes, to be merged */ |
896 | #ifdef CONFIG_PPC64 | |
897 | hose = pcibios_alloc_controller(dev); | |
898 | #else | |
35499c01 | 899 | hose = pcibios_alloc_controller(); |
b5166cc2 | 900 | #endif |
35499c01 PM |
901 | if (!hose) |
902 | return -ENOMEM; | |
903 | hose->arch_data = dev; | |
904 | hose->first_busno = bus_range ? bus_range[0] : 0; | |
905 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
14cf11af PM |
906 | |
907 | disp_name = NULL; | |
cc5d0189 BH |
908 | |
909 | /* 64 bits only bridges */ | |
b5166cc2 | 910 | #ifdef CONFIG_PPC64 |
35499c01 PM |
911 | if (device_is_compatible(dev, "u3-agp")) { |
912 | setup_u3_agp(hose); | |
913 | disp_name = "U3-AGP"; | |
914 | primary = 0; | |
915 | } else if (device_is_compatible(dev, "u3-ht")) { | |
916 | setup_u3_ht(hose); | |
917 | disp_name = "U3-HT"; | |
918 | primary = 1; | |
1beb6a7d BH |
919 | } else if (device_is_compatible(dev, "u4-pcie")) { |
920 | setup_u4_pcie(hose); | |
921 | disp_name = "U4-PCIE"; | |
922 | primary = 0; | |
35499c01 | 923 | } |
1beb6a7d BH |
924 | printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:" |
925 | " %d->%d\n", disp_name, hose->first_busno, hose->last_busno); | |
cc5d0189 BH |
926 | #endif /* CONFIG_PPC64 */ |
927 | ||
928 | /* 32 bits only bridges */ | |
929 | #ifdef CONFIG_PPC32 | |
14cf11af | 930 | if (device_is_compatible(dev, "uni-north")) { |
cc5d0189 | 931 | primary = setup_uninorth(hose, &rsrc); |
35499c01 | 932 | disp_name = "UniNorth"; |
3c3f42d6 | 933 | } else if (strcmp(dev->name, "pci") == 0) { |
35499c01 PM |
934 | /* XXX assume this is a mpc106 (grackle) */ |
935 | setup_grackle(hose); | |
936 | disp_name = "Grackle (MPC106)"; | |
937 | } else if (strcmp(dev->name, "bandit") == 0) { | |
cc5d0189 | 938 | setup_bandit(hose, &rsrc); |
35499c01 PM |
939 | disp_name = "Bandit"; |
940 | } else if (strcmp(dev->name, "chaos") == 0) { | |
cc5d0189 | 941 | setup_chaos(hose, &rsrc); |
35499c01 PM |
942 | disp_name = "Chaos"; |
943 | primary = 0; | |
944 | } | |
cc5d0189 BH |
945 | printk(KERN_INFO "Found %s PCI host bridge at 0x%08lx. " |
946 | "Firmware bus number: %d->%d\n", | |
947 | disp_name, rsrc.start, hose->first_busno, hose->last_busno); | |
948 | #endif /* CONFIG_PPC32 */ | |
949 | ||
35499c01 PM |
950 | DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", |
951 | hose, hose->cfg_addr, hose->cfg_data); | |
952 | ||
953 | /* Interpret the "ranges" property */ | |
954 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
955 | pci_process_bridge_OF_ranges(hose, dev, primary); | |
956 | ||
957 | /* Fixup "bus-range" OF property */ | |
958 | fixup_bus_range(dev); | |
14cf11af PM |
959 | |
960 | return 0; | |
961 | } | |
962 | ||
cc5d0189 | 963 | static void __init pcibios_fixup_OF_interrupts(void) |
14cf11af PM |
964 | { |
965 | struct pci_dev* dev = NULL; | |
966 | ||
967 | /* | |
968 | * Open Firmware often doesn't initialize the | |
969 | * PCI_INTERRUPT_LINE config register properly, so we | |
970 | * should find the device node and apply the interrupt | |
971 | * obtained from the OF device-tree | |
972 | */ | |
973 | for_each_pci_dev(dev) { | |
974 | struct device_node *node; | |
975 | node = pci_device_to_OF_node(dev); | |
976 | /* this is the node, see if it has interrupts */ | |
977 | if (node && node->n_intrs > 0) | |
978 | dev->irq = node->intrs[0].line; | |
979 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); | |
980 | } | |
981 | } | |
982 | ||
cc5d0189 | 983 | void __init pmac_pcibios_fixup(void) |
14cf11af PM |
984 | { |
985 | /* Fixup interrupts according to OF tree */ | |
986 | pcibios_fixup_OF_interrupts(); | |
987 | } | |
988 | ||
35499c01 PM |
989 | #ifdef CONFIG_PPC64 |
990 | static void __init pmac_fixup_phb_resources(void) | |
991 | { | |
992 | struct pci_controller *hose, *tmp; | |
993 | ||
994 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
995 | printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n", | |
996 | hose->global_number, | |
997 | hose->io_resource.start, hose->io_resource.end); | |
998 | } | |
999 | } | |
1000 | #endif | |
1001 | ||
1002 | void __init pmac_pci_init(void) | |
3c3f42d6 PM |
1003 | { |
1004 | struct device_node *np, *root; | |
1005 | struct device_node *ht = NULL; | |
1006 | ||
1007 | root = of_find_node_by_path("/"); | |
1008 | if (root == NULL) { | |
35499c01 PM |
1009 | printk(KERN_CRIT "pmac_pci_init: can't find root " |
1010 | "of device tree\n"); | |
3c3f42d6 PM |
1011 | return; |
1012 | } | |
1013 | for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { | |
1014 | if (np->name == NULL) | |
1015 | continue; | |
1016 | if (strcmp(np->name, "bandit") == 0 | |
1017 | || strcmp(np->name, "chaos") == 0 | |
1018 | || strcmp(np->name, "pci") == 0) { | |
1019 | if (add_bridge(np) == 0) | |
1020 | of_node_get(np); | |
1021 | } | |
1022 | if (strcmp(np->name, "ht") == 0) { | |
1023 | of_node_get(np); | |
1024 | ht = np; | |
1025 | } | |
1026 | } | |
1027 | of_node_put(root); | |
1028 | ||
35499c01 | 1029 | #ifdef CONFIG_PPC64 |
3c3f42d6 PM |
1030 | /* Probe HT last as it relies on the agp resources to be already |
1031 | * setup | |
1032 | */ | |
1033 | if (ht && add_bridge(ht) != 0) | |
1034 | of_node_put(ht); | |
1035 | ||
35499c01 PM |
1036 | /* |
1037 | * We need to call pci_setup_phb_io for the HT bridge first | |
1038 | * so it gets the I/O port numbers starting at 0, and we | |
1039 | * need to call it for the AGP bridge after that so it gets | |
1040 | * small positive I/O port numbers. | |
1041 | */ | |
1042 | if (u3_ht) | |
1043 | pci_setup_phb_io(u3_ht, 1); | |
1044 | if (u3_agp) | |
1045 | pci_setup_phb_io(u3_agp, 0); | |
1beb6a7d BH |
1046 | if (u4_pcie) |
1047 | pci_setup_phb_io(u4_pcie, 0); | |
35499c01 PM |
1048 | |
1049 | /* | |
1050 | * On ppc64, fixup the IO resources on our host bridges as | |
1051 | * the common code does it only for children of the host bridges | |
1052 | */ | |
1053 | pmac_fixup_phb_resources(); | |
1054 | ||
1055 | /* Setup the linkage between OF nodes and PHBs */ | |
1056 | pci_devs_phb_init(); | |
1057 | ||
1058 | /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We | |
1059 | * assume there is no P2P bridge on the AGP bus, which should be a | |
1beb6a7d BH |
1060 | * safe assumptions for now. We should do something better in the |
1061 | * future though | |
35499c01 PM |
1062 | */ |
1063 | if (u3_agp) { | |
1064 | struct device_node *np = u3_agp->arch_data; | |
1065 | PCI_DN(np)->busno = 0xf0; | |
1066 | for (np = np->child; np; np = np->sibling) | |
1067 | PCI_DN(np)->busno = 0xf0; | |
1068 | } | |
35499c01 PM |
1069 | /* pmac_check_ht_link(); */ |
1070 | ||
1071 | /* Tell pci.c to not use the common resource allocation mechanism */ | |
1072 | pci_probe_only = 1; | |
1073 | ||
1074 | /* Allow all IO */ | |
1075 | io_page_mask = -1; | |
1076 | ||
1077 | #else /* CONFIG_PPC64 */ | |
3c3f42d6 PM |
1078 | init_p2pbridge(); |
1079 | fixup_nec_usb2(); | |
35499c01 | 1080 | |
3c3f42d6 PM |
1081 | /* We are still having some issues with the Xserve G4, enabling |
1082 | * some offset between bus number and domains for now when we | |
1083 | * assign all busses should help for now | |
1084 | */ | |
399fe2bd | 1085 | if (pci_assign_all_buses) |
3c3f42d6 | 1086 | pcibios_assign_bus_offset = 0x10; |
35499c01 | 1087 | #endif |
3c3f42d6 PM |
1088 | } |
1089 | ||
14cf11af PM |
1090 | int |
1091 | pmac_pci_enable_device_hook(struct pci_dev *dev, int initial) | |
1092 | { | |
1093 | struct device_node* node; | |
1094 | int updatecfg = 0; | |
1095 | int uninorth_child; | |
1096 | ||
1097 | node = pci_device_to_OF_node(dev); | |
1098 | ||
1099 | /* We don't want to enable USB controllers absent from the OF tree | |
1100 | * (iBook second controller) | |
1101 | */ | |
1102 | if (dev->vendor == PCI_VENDOR_ID_APPLE | |
1103 | && (dev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) | |
1104 | && !node) { | |
1105 | printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", | |
1106 | pci_name(dev)); | |
1107 | return -EINVAL; | |
1108 | } | |
1109 | ||
1110 | if (!node) | |
1111 | return 0; | |
1112 | ||
1113 | uninorth_child = node->parent && | |
1114 | device_is_compatible(node->parent, "uni-north"); | |
35499c01 | 1115 | |
14cf11af PM |
1116 | /* Firewire & GMAC were disabled after PCI probe, the driver is |
1117 | * claiming them, we must re-enable them now. | |
1118 | */ | |
1119 | if (uninorth_child && !strcmp(node->name, "firewire") && | |
1120 | (device_is_compatible(node, "pci106b,18") || | |
1121 | device_is_compatible(node, "pci106b,30") || | |
1122 | device_is_compatible(node, "pci11c1,5811"))) { | |
1123 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); | |
1124 | pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); | |
1125 | updatecfg = 1; | |
1126 | } | |
1127 | if (uninorth_child && !strcmp(node->name, "ethernet") && | |
1128 | device_is_compatible(node, "gmac")) { | |
1129 | pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); | |
1130 | updatecfg = 1; | |
1131 | } | |
1132 | ||
1133 | if (updatecfg) { | |
1134 | u16 cmd; | |
35499c01 | 1135 | |
14cf11af PM |
1136 | /* |
1137 | * Make sure PCI is correctly configured | |
1138 | * | |
1139 | * We use old pci_bios versions of the function since, by | |
1140 | * default, gmac is not powered up, and so will be absent | |
1141 | * from the kernel initial PCI lookup. | |
1142 | * | |
1143 | * Should be replaced by 2.4 new PCI mechanisms and really | |
1144 | * register the device. | |
1145 | */ | |
1146 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
35499c01 PM |
1147 | cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
1148 | | PCI_COMMAND_INVALIDATE; | |
1149 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1150 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); | |
1151 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, | |
1152 | L1_CACHE_BYTES >> 2); | |
14cf11af PM |
1153 | } |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | /* We power down some devices after they have been probed. They'll | |
1159 | * be powered back on later on | |
1160 | */ | |
35499c01 | 1161 | void __init pmac_pcibios_after_init(void) |
14cf11af PM |
1162 | { |
1163 | struct device_node* nd; | |
1164 | ||
1165 | #ifdef CONFIG_BLK_DEV_IDE | |
1166 | struct pci_dev *dev = NULL; | |
1167 | ||
1168 | /* OF fails to initialize IDE controllers on macs | |
1169 | * (and maybe other machines) | |
1170 | * | |
1171 | * Ideally, this should be moved to the IDE layer, but we need | |
1172 | * to check specifically with Andre Hedrick how to do it cleanly | |
1173 | * since the common IDE code seem to care about the fact that the | |
1174 | * BIOS may have disabled a controller. | |
1175 | * | |
1176 | * -- BenH | |
1177 | */ | |
1178 | for_each_pci_dev(dev) { | |
1179 | if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE) | |
1180 | pci_enable_device(dev); | |
1181 | } | |
1182 | #endif /* CONFIG_BLK_DEV_IDE */ | |
1183 | ||
1184 | nd = find_devices("firewire"); | |
1185 | while (nd) { | |
1186 | if (nd->parent && (device_is_compatible(nd, "pci106b,18") || | |
1187 | device_is_compatible(nd, "pci106b,30") || | |
1188 | device_is_compatible(nd, "pci11c1,5811")) | |
1189 | && device_is_compatible(nd->parent, "uni-north")) { | |
1190 | pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); | |
1191 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); | |
1192 | } | |
1193 | nd = nd->next; | |
1194 | } | |
1195 | nd = find_devices("ethernet"); | |
1196 | while (nd) { | |
1197 | if (nd->parent && device_is_compatible(nd, "gmac") | |
1198 | && device_is_compatible(nd->parent, "uni-north")) | |
1199 | pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); | |
1200 | nd = nd->next; | |
1201 | } | |
1202 | } | |
1203 | ||
14cf11af PM |
1204 | #ifdef CONFIG_PPC32 |
1205 | void pmac_pci_fixup_cardbus(struct pci_dev* dev) | |
1206 | { | |
1207 | if (_machine != _MACH_Pmac) | |
1208 | return; | |
1209 | /* | |
1210 | * Fix the interrupt routing on the various cardbus bridges | |
1211 | * used on powerbooks | |
1212 | */ | |
1213 | if (dev->vendor != PCI_VENDOR_ID_TI) | |
1214 | return; | |
1215 | if (dev->device == PCI_DEVICE_ID_TI_1130 || | |
1216 | dev->device == PCI_DEVICE_ID_TI_1131) { | |
1217 | u8 val; | |
35499c01 | 1218 | /* Enable PCI interrupt */ |
14cf11af PM |
1219 | if (pci_read_config_byte(dev, 0x91, &val) == 0) |
1220 | pci_write_config_byte(dev, 0x91, val | 0x30); | |
1221 | /* Disable ISA interrupt mode */ | |
1222 | if (pci_read_config_byte(dev, 0x92, &val) == 0) | |
1223 | pci_write_config_byte(dev, 0x92, val & ~0x06); | |
1224 | } | |
1225 | if (dev->device == PCI_DEVICE_ID_TI_1210 || | |
1226 | dev->device == PCI_DEVICE_ID_TI_1211 || | |
1227 | dev->device == PCI_DEVICE_ID_TI_1410 || | |
1228 | dev->device == PCI_DEVICE_ID_TI_1510) { | |
1229 | u8 val; | |
1230 | /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA | |
1231 | signal out the MFUNC0 pin */ | |
1232 | if (pci_read_config_byte(dev, 0x8c, &val) == 0) | |
1233 | pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); | |
1234 | /* Disable ISA interrupt mode */ | |
1235 | if (pci_read_config_byte(dev, 0x92, &val) == 0) | |
1236 | pci_write_config_byte(dev, 0x92, val & ~0x06); | |
1237 | } | |
1238 | } | |
1239 | ||
1240 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); | |
1241 | ||
1242 | void pmac_pci_fixup_pciata(struct pci_dev* dev) | |
1243 | { | |
1244 | u8 progif = 0; | |
1245 | ||
1246 | /* | |
1247 | * On PowerMacs, we try to switch any PCI ATA controller to | |
1248 | * fully native mode | |
1249 | */ | |
1250 | if (_machine != _MACH_Pmac) | |
1251 | return; | |
1252 | /* Some controllers don't have the class IDE */ | |
1253 | if (dev->vendor == PCI_VENDOR_ID_PROMISE) | |
1254 | switch(dev->device) { | |
1255 | case PCI_DEVICE_ID_PROMISE_20246: | |
1256 | case PCI_DEVICE_ID_PROMISE_20262: | |
1257 | case PCI_DEVICE_ID_PROMISE_20263: | |
1258 | case PCI_DEVICE_ID_PROMISE_20265: | |
1259 | case PCI_DEVICE_ID_PROMISE_20267: | |
1260 | case PCI_DEVICE_ID_PROMISE_20268: | |
1261 | case PCI_DEVICE_ID_PROMISE_20269: | |
1262 | case PCI_DEVICE_ID_PROMISE_20270: | |
1263 | case PCI_DEVICE_ID_PROMISE_20271: | |
1264 | case PCI_DEVICE_ID_PROMISE_20275: | |
1265 | case PCI_DEVICE_ID_PROMISE_20276: | |
1266 | case PCI_DEVICE_ID_PROMISE_20277: | |
1267 | goto good; | |
1268 | } | |
1269 | /* Others, check PCI class */ | |
1270 | if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) | |
1271 | return; | |
1272 | good: | |
1273 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
1274 | if ((progif & 5) != 5) { | |
1beb6a7d BH |
1275 | printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", |
1276 | pci_name(dev)); | |
14cf11af PM |
1277 | (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); |
1278 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
1279 | (progif & 5) != 5) | |
1280 | printk(KERN_ERR "Rewrite of PROGIF failed !\n"); | |
1281 | } | |
1282 | } | |
1283 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); | |
1284 | #endif | |
1285 | ||
1286 | /* | |
1287 | * Disable second function on K2-SATA, it's broken | |
1288 | * and disable IO BARs on first one | |
1289 | */ | |
1290 | static void fixup_k2_sata(struct pci_dev* dev) | |
1291 | { | |
1292 | int i; | |
1293 | u16 cmd; | |
1294 | ||
1295 | if (PCI_FUNC(dev->devfn) > 0) { | |
1296 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1297 | cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); | |
1298 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1299 | for (i = 0; i < 6; i++) { | |
1300 | dev->resource[i].start = dev->resource[i].end = 0; | |
1301 | dev->resource[i].flags = 0; | |
1beb6a7d BH |
1302 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, |
1303 | 0); | |
14cf11af PM |
1304 | } |
1305 | } else { | |
1306 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1307 | cmd &= ~PCI_COMMAND_IO; | |
1308 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1309 | for (i = 0; i < 5; i++) { | |
1310 | dev->resource[i].start = dev->resource[i].end = 0; | |
1311 | dev->resource[i].flags = 0; | |
1beb6a7d BH |
1312 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, |
1313 | 0); | |
14cf11af PM |
1314 | } |
1315 | } | |
1316 | } | |
1317 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata); | |
1318 |