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14cf11af PM |
1 | /* |
2 | * Support for the interrupt controllers found on Power Macintosh, | |
3 | * currently Apple's "Grand Central" interrupt controller in all | |
4 | * it's incarnations. OpenPIC support used on newer machines is | |
5 | * in a separate file | |
6 | * | |
7 | * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) | |
cc5d0189 BH |
8 | * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org) |
9 | * IBM, Corp. | |
14cf11af PM |
10 | * |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | */ | |
17 | ||
14cf11af PM |
18 | #include <linux/stddef.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/signal.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/sysdev.h> | |
25 | #include <linux/adb.h> | |
26 | #include <linux/pmu.h> | |
3c3f42d6 | 27 | #include <linux/module.h> |
14cf11af PM |
28 | |
29 | #include <asm/sections.h> | |
30 | #include <asm/io.h> | |
31 | #include <asm/smp.h> | |
32 | #include <asm/prom.h> | |
33 | #include <asm/pci-bridge.h> | |
34 | #include <asm/time.h> | |
14cf11af PM |
35 | #include <asm/pmac_feature.h> |
36 | #include <asm/mpic.h> | |
37 | ||
3c3f42d6 | 38 | #include "pmac.h" |
14cf11af PM |
39 | |
40 | /* | |
41 | * XXX this should be in xmon.h, but putting it there means xmon.h | |
42 | * has to include <linux/interrupt.h> (to get irqreturn_t), which | |
43 | * causes all sorts of problems. -- paulus | |
44 | */ | |
45 | extern irqreturn_t xmon_irq(int, void *, struct pt_regs *); | |
46 | ||
3c3f42d6 | 47 | #ifdef CONFIG_PPC32 |
14cf11af PM |
48 | struct pmac_irq_hw { |
49 | unsigned int event; | |
50 | unsigned int enable; | |
51 | unsigned int ack; | |
52 | unsigned int level; | |
53 | }; | |
54 | ||
55 | /* Default addresses */ | |
cc5d0189 | 56 | static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4]; |
14cf11af PM |
57 | |
58 | #define GC_LEVEL_MASK 0x3ff00000 | |
59 | #define OHARE_LEVEL_MASK 0x1ff00000 | |
60 | #define HEATHROW_LEVEL_MASK 0x1ff00000 | |
61 | ||
62 | static int max_irqs; | |
63 | static int max_real_irqs; | |
64 | static u32 level_mask[4]; | |
65 | ||
66 | static DEFINE_SPINLOCK(pmac_pic_lock); | |
67 | ||
14cf11af PM |
68 | #define GATWICK_IRQ_POOL_SIZE 10 |
69 | static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE]; | |
70 | ||
756e7104 SR |
71 | #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) |
72 | static unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; | |
73 | ||
14cf11af PM |
74 | /* |
75 | * Mark an irq as "lost". This is only used on the pmac | |
76 | * since it can lose interrupts (see pmac_set_irq_mask). | |
77 | * -- Cort | |
78 | */ | |
cc5d0189 | 79 | void __set_lost(unsigned long irq_nr, int nokick) |
14cf11af PM |
80 | { |
81 | if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) { | |
82 | atomic_inc(&ppc_n_lost_interrupts); | |
83 | if (!nokick) | |
84 | set_dec(1); | |
85 | } | |
86 | } | |
87 | ||
cc5d0189 | 88 | static void pmac_mask_and_ack_irq(unsigned int irq_nr) |
14cf11af PM |
89 | { |
90 | unsigned long bit = 1UL << (irq_nr & 0x1f); | |
91 | int i = irq_nr >> 5; | |
92 | unsigned long flags; | |
93 | ||
94 | if ((unsigned)irq_nr >= max_irqs) | |
95 | return; | |
96 | ||
97 | clear_bit(irq_nr, ppc_cached_irq_mask); | |
98 | if (test_and_clear_bit(irq_nr, ppc_lost_interrupts)) | |
99 | atomic_dec(&ppc_n_lost_interrupts); | |
100 | spin_lock_irqsave(&pmac_pic_lock, flags); | |
101 | out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); | |
102 | out_le32(&pmac_irq_hw[i]->ack, bit); | |
103 | do { | |
104 | /* make sure ack gets to controller before we enable | |
105 | interrupts */ | |
106 | mb(); | |
107 | } while((in_le32(&pmac_irq_hw[i]->enable) & bit) | |
108 | != (ppc_cached_irq_mask[i] & bit)); | |
109 | spin_unlock_irqrestore(&pmac_pic_lock, flags); | |
110 | } | |
111 | ||
112 | static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost) | |
113 | { | |
114 | unsigned long bit = 1UL << (irq_nr & 0x1f); | |
115 | int i = irq_nr >> 5; | |
116 | unsigned long flags; | |
117 | ||
118 | if ((unsigned)irq_nr >= max_irqs) | |
119 | return; | |
120 | ||
121 | spin_lock_irqsave(&pmac_pic_lock, flags); | |
122 | /* enable unmasked interrupts */ | |
123 | out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); | |
124 | ||
125 | do { | |
126 | /* make sure mask gets to controller before we | |
127 | return to user */ | |
128 | mb(); | |
129 | } while((in_le32(&pmac_irq_hw[i]->enable) & bit) | |
130 | != (ppc_cached_irq_mask[i] & bit)); | |
131 | ||
132 | /* | |
133 | * Unfortunately, setting the bit in the enable register | |
134 | * when the device interrupt is already on *doesn't* set | |
135 | * the bit in the flag register or request another interrupt. | |
136 | */ | |
137 | if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level)) | |
138 | __set_lost((ulong)irq_nr, nokicklost); | |
139 | spin_unlock_irqrestore(&pmac_pic_lock, flags); | |
140 | } | |
141 | ||
142 | /* When an irq gets requested for the first client, if it's an | |
143 | * edge interrupt, we clear any previous one on the controller | |
144 | */ | |
145 | static unsigned int pmac_startup_irq(unsigned int irq_nr) | |
146 | { | |
147 | unsigned long bit = 1UL << (irq_nr & 0x1f); | |
148 | int i = irq_nr >> 5; | |
149 | ||
150 | if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0) | |
151 | out_le32(&pmac_irq_hw[i]->ack, bit); | |
152 | set_bit(irq_nr, ppc_cached_irq_mask); | |
153 | pmac_set_irq_mask(irq_nr, 0); | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
158 | static void pmac_mask_irq(unsigned int irq_nr) | |
159 | { | |
160 | clear_bit(irq_nr, ppc_cached_irq_mask); | |
161 | pmac_set_irq_mask(irq_nr, 0); | |
162 | mb(); | |
163 | } | |
164 | ||
165 | static void pmac_unmask_irq(unsigned int irq_nr) | |
166 | { | |
167 | set_bit(irq_nr, ppc_cached_irq_mask); | |
168 | pmac_set_irq_mask(irq_nr, 0); | |
169 | } | |
170 | ||
171 | static void pmac_end_irq(unsigned int irq_nr) | |
172 | { | |
173 | if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)) | |
174 | && irq_desc[irq_nr].action) { | |
175 | set_bit(irq_nr, ppc_cached_irq_mask); | |
176 | pmac_set_irq_mask(irq_nr, 1); | |
177 | } | |
178 | } | |
179 | ||
180 | ||
181 | struct hw_interrupt_type pmac_pic = { | |
182 | .typename = " PMAC-PIC ", | |
183 | .startup = pmac_startup_irq, | |
184 | .enable = pmac_unmask_irq, | |
185 | .disable = pmac_mask_irq, | |
186 | .ack = pmac_mask_and_ack_irq, | |
187 | .end = pmac_end_irq, | |
188 | }; | |
189 | ||
190 | struct hw_interrupt_type gatwick_pic = { | |
191 | .typename = " GATWICK ", | |
192 | .startup = pmac_startup_irq, | |
193 | .enable = pmac_unmask_irq, | |
194 | .disable = pmac_mask_irq, | |
195 | .ack = pmac_mask_and_ack_irq, | |
196 | .end = pmac_end_irq, | |
197 | }; | |
198 | ||
199 | static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs) | |
200 | { | |
201 | int irq, bits; | |
202 | ||
203 | for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) { | |
204 | int i = irq >> 5; | |
205 | bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; | |
206 | /* We must read level interrupts from the level register */ | |
207 | bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); | |
208 | bits &= ppc_cached_irq_mask[i]; | |
209 | if (bits == 0) | |
210 | continue; | |
211 | irq += __ilog2(bits); | |
212 | __do_IRQ(irq, regs); | |
213 | return IRQ_HANDLED; | |
214 | } | |
215 | printk("gatwick irq not from gatwick pic\n"); | |
216 | return IRQ_NONE; | |
217 | } | |
218 | ||
cc5d0189 | 219 | static int pmac_get_irq(struct pt_regs *regs) |
14cf11af PM |
220 | { |
221 | int irq; | |
222 | unsigned long bits = 0; | |
223 | ||
224 | #ifdef CONFIG_SMP | |
225 | void psurge_smp_message_recv(struct pt_regs *); | |
226 | ||
227 | /* IPI's are a hack on the powersurge -- Cort */ | |
228 | if ( smp_processor_id() != 0 ) { | |
229 | psurge_smp_message_recv(regs); | |
230 | return -2; /* ignore, already handled */ | |
231 | } | |
232 | #endif /* CONFIG_SMP */ | |
233 | for (irq = max_real_irqs; (irq -= 32) >= 0; ) { | |
234 | int i = irq >> 5; | |
235 | bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; | |
236 | /* We must read level interrupts from the level register */ | |
237 | bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); | |
238 | bits &= ppc_cached_irq_mask[i]; | |
239 | if (bits == 0) | |
240 | continue; | |
241 | irq += __ilog2(bits); | |
242 | break; | |
243 | } | |
244 | ||
245 | return irq; | |
246 | } | |
247 | ||
248 | /* This routine will fix some missing interrupt values in the device tree | |
249 | * on the gatwick mac-io controller used by some PowerBooks | |
cc5d0189 BH |
250 | * |
251 | * Walking of OF nodes could use a bit more fixing up here, but it's not | |
252 | * very important as this is all boot time code on static portions of the | |
253 | * device-tree. | |
254 | * | |
255 | * However, the modifications done to "intrs" will have to be removed and | |
256 | * replaced with proper updates of the "interrupts" properties or | |
257 | * AAPL,interrupts, yet to be decided, once the dynamic parsing is there. | |
14cf11af | 258 | */ |
cc5d0189 BH |
259 | static void __init pmac_fix_gatwick_interrupts(struct device_node *gw, |
260 | int irq_base) | |
14cf11af PM |
261 | { |
262 | struct device_node *node; | |
263 | int count; | |
264 | ||
265 | memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool)); | |
14cf11af | 266 | count = 0; |
cc5d0189 | 267 | for (node = NULL; (node = of_get_next_child(gw, node)) != NULL;) { |
14cf11af | 268 | /* Fix SCC */ |
cc5d0189 BH |
269 | if ((strcasecmp(node->name, "escc") == 0) && node->child) { |
270 | if (node->child->n_intrs < 3) { | |
271 | node->child->intrs = &gatwick_int_pool[count]; | |
272 | count += 3; | |
14cf11af | 273 | } |
cc5d0189 BH |
274 | node->child->n_intrs = 3; |
275 | node->child->intrs[0].line = 15+irq_base; | |
276 | node->child->intrs[1].line = 4+irq_base; | |
277 | node->child->intrs[2].line = 5+irq_base; | |
278 | printk(KERN_INFO "irq: fixed SCC on gatwick" | |
279 | " (%d,%d,%d)\n", | |
280 | node->child->intrs[0].line, | |
281 | node->child->intrs[1].line, | |
282 | node->child->intrs[2].line); | |
283 | } | |
14cf11af PM |
284 | /* Fix media-bay & left SWIM */ |
285 | if (strcasecmp(node->name, "media-bay") == 0) { | |
286 | struct device_node* ya_node; | |
287 | ||
288 | if (node->n_intrs == 0) | |
289 | node->intrs = &gatwick_int_pool[count++]; | |
290 | node->n_intrs = 1; | |
291 | node->intrs[0].line = 29+irq_base; | |
cc5d0189 BH |
292 | printk(KERN_INFO "irq: fixed media-bay on gatwick" |
293 | " (%d)\n", node->intrs[0].line); | |
14cf11af PM |
294 | |
295 | ya_node = node->child; | |
cc5d0189 | 296 | while(ya_node) { |
14cf11af PM |
297 | if (strcasecmp(ya_node->name, "floppy") == 0) { |
298 | if (ya_node->n_intrs < 2) { | |
299 | ya_node->intrs = &gatwick_int_pool[count]; | |
300 | count += 2; | |
301 | } | |
302 | ya_node->n_intrs = 2; | |
303 | ya_node->intrs[0].line = 19+irq_base; | |
304 | ya_node->intrs[1].line = 1+irq_base; | |
305 | printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n", | |
306 | ya_node->intrs[0].line, ya_node->intrs[1].line); | |
307 | } | |
308 | if (strcasecmp(ya_node->name, "ata4") == 0) { | |
309 | if (ya_node->n_intrs < 2) { | |
310 | ya_node->intrs = &gatwick_int_pool[count]; | |
311 | count += 2; | |
312 | } | |
313 | ya_node->n_intrs = 2; | |
314 | ya_node->intrs[0].line = 14+irq_base; | |
315 | ya_node->intrs[1].line = 3+irq_base; | |
316 | printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n", | |
317 | ya_node->intrs[0].line, ya_node->intrs[1].line); | |
318 | } | |
319 | ya_node = ya_node->sibling; | |
320 | } | |
321 | } | |
14cf11af PM |
322 | } |
323 | if (count > 10) { | |
324 | printk("WARNING !! Gatwick interrupt pool overflow\n"); | |
325 | printk(" GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE); | |
326 | printk(" requested = %d\n", count); | |
327 | } | |
328 | } | |
329 | ||
330 | /* | |
331 | * The PowerBook 3400/2400/3500 can have a combo ethernet/modem | |
332 | * card which includes an ohare chip that acts as a second interrupt | |
333 | * controller. If we find this second ohare, set it up and fix the | |
334 | * interrupt value in the device tree for the ethernet chip. | |
335 | */ | |
cc5d0189 | 336 | static void __init enable_second_ohare(struct device_node *np) |
14cf11af PM |
337 | { |
338 | unsigned char bus, devfn; | |
339 | unsigned short cmd; | |
14cf11af PM |
340 | struct device_node *ether; |
341 | ||
cc5d0189 BH |
342 | /* This code doesn't strictly belong here, it could be part of |
343 | * either the PCI initialisation or the feature code. It's kept | |
344 | * here for historical reasons. | |
345 | */ | |
346 | if (pci_device_from_OF_node(np, &bus, &devfn) == 0) { | |
347 | struct pci_controller* hose = | |
348 | pci_find_hose_for_OF_device(np); | |
349 | if (!hose) { | |
350 | printk(KERN_ERR "Can't find PCI hose for OHare2 !\n"); | |
351 | return; | |
14cf11af | 352 | } |
cc5d0189 BH |
353 | early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); |
354 | cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; | |
355 | cmd &= ~PCI_COMMAND_IO; | |
356 | early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); | |
14cf11af PM |
357 | } |
358 | ||
359 | /* Fix interrupt for the modem/ethernet combo controller. The number | |
cc5d0189 BH |
360 | * in the device tree (27) is bogus (correct for the ethernet-only |
361 | * board but not the combo ethernet/modem board). | |
362 | * The real interrupt is 28 on the second controller -> 28+32 = 60. | |
363 | */ | |
364 | ether = of_find_node_by_name(NULL, "pci1011,14"); | |
14cf11af PM |
365 | if (ether && ether->n_intrs > 0) { |
366 | ether->intrs[0].line = 60; | |
367 | printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n", | |
368 | ether->intrs[0].line); | |
369 | } | |
cc5d0189 | 370 | of_node_put(ether); |
14cf11af PM |
371 | } |
372 | ||
14cf11af PM |
373 | #ifdef CONFIG_XMON |
374 | static struct irqaction xmon_action = { | |
375 | .handler = xmon_irq, | |
376 | .flags = 0, | |
377 | .mask = CPU_MASK_NONE, | |
378 | .name = "NMI - XMON" | |
379 | }; | |
380 | #endif | |
381 | ||
382 | static struct irqaction gatwick_cascade_action = { | |
383 | .handler = gatwick_action, | |
384 | .flags = SA_INTERRUPT, | |
385 | .mask = CPU_MASK_NONE, | |
386 | .name = "cascade", | |
387 | }; | |
3c3f42d6 | 388 | |
cc5d0189 | 389 | static void __init pmac_pic_probe_oldstyle(void) |
3c3f42d6 | 390 | { |
3c3f42d6 | 391 | int i; |
14cf11af | 392 | int irq_cascade = -1; |
cc5d0189 BH |
393 | struct device_node *master = NULL; |
394 | struct device_node *slave = NULL; | |
395 | u8 __iomem *addr; | |
396 | struct resource r; | |
14cf11af | 397 | |
cc5d0189 BH |
398 | /* Set our get_irq function */ |
399 | ppc_md.get_irq = pmac_get_irq; | |
14cf11af | 400 | |
cc5d0189 BH |
401 | /* |
402 | * Find the interrupt controller type & node | |
14cf11af | 403 | */ |
cc5d0189 BH |
404 | |
405 | if ((master = of_find_node_by_name(NULL, "gc")) != NULL) { | |
406 | max_irqs = max_real_irqs = 32; | |
14cf11af | 407 | level_mask[0] = GC_LEVEL_MASK; |
cc5d0189 BH |
408 | } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) { |
409 | max_irqs = max_real_irqs = 32; | |
14cf11af | 410 | level_mask[0] = OHARE_LEVEL_MASK; |
cc5d0189 | 411 | |
14cf11af | 412 | /* We might have a second cascaded ohare */ |
cc5d0189 BH |
413 | slave = of_find_node_by_name(NULL, "pci106b,7"); |
414 | if (slave) { | |
415 | max_irqs = 64; | |
416 | level_mask[1] = OHARE_LEVEL_MASK; | |
417 | enable_second_ohare(slave); | |
418 | } | |
419 | } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) { | |
420 | max_irqs = max_real_irqs = 64; | |
14cf11af PM |
421 | level_mask[0] = HEATHROW_LEVEL_MASK; |
422 | level_mask[1] = 0; | |
cc5d0189 | 423 | |
14cf11af | 424 | /* We might have a second cascaded heathrow */ |
cc5d0189 BH |
425 | slave = of_find_node_by_name(master, "mac-io"); |
426 | ||
427 | /* Check ordering of master & slave */ | |
428 | if (device_is_compatible(master, "gatwick")) { | |
429 | struct device_node *tmp; | |
430 | BUG_ON(slave == NULL); | |
431 | tmp = master; | |
432 | master = slave; | |
433 | slave = tmp; | |
434 | } | |
14cf11af | 435 | |
cc5d0189 BH |
436 | /* We found a slave */ |
437 | if (slave) { | |
14cf11af | 438 | max_irqs = 128; |
cc5d0189 BH |
439 | level_mask[2] = HEATHROW_LEVEL_MASK; |
440 | level_mask[3] = 0; | |
441 | pmac_fix_gatwick_interrupts(slave, max_real_irqs); | |
442 | } | |
14cf11af | 443 | } |
cc5d0189 BH |
444 | BUG_ON(master == NULL); |
445 | ||
446 | /* Set the handler for the main PIC */ | |
14cf11af | 447 | for ( i = 0; i < max_real_irqs ; i++ ) |
d1bef4ed | 448 | irq_desc[i].chip = &pmac_pic; |
14cf11af | 449 | |
cc5d0189 BH |
450 | /* Get addresses of first controller if we have a node for it */ |
451 | BUG_ON(of_address_to_resource(master, 0, &r)); | |
452 | ||
453 | /* Map interrupts of primary controller */ | |
454 | addr = (u8 __iomem *) ioremap(r.start, 0x40); | |
455 | i = 0; | |
456 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
457 | (addr + 0x20); | |
458 | if (max_real_irqs > 32) | |
459 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
460 | (addr + 0x10); | |
461 | of_node_put(master); | |
462 | ||
463 | printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n", | |
464 | master->full_name, max_real_irqs); | |
465 | ||
466 | /* Map interrupts of cascaded controller */ | |
467 | if (slave && !of_address_to_resource(slave, 0, &r)) { | |
468 | addr = (u8 __iomem *)ioremap(r.start, 0x40); | |
469 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
470 | (addr + 0x20); | |
471 | if (max_irqs > 64) | |
472 | pmac_irq_hw[i++] = | |
473 | (volatile struct pmac_irq_hw __iomem *) | |
474 | (addr + 0x10); | |
475 | irq_cascade = slave->intrs[0].line; | |
476 | ||
477 | printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs" | |
478 | " cascade: %d\n", slave->full_name, | |
479 | max_irqs - max_real_irqs, irq_cascade); | |
14cf11af | 480 | } |
cc5d0189 | 481 | of_node_put(slave); |
14cf11af PM |
482 | |
483 | /* disable all interrupts in all controllers */ | |
484 | for (i = 0; i * 32 < max_irqs; ++i) | |
485 | out_le32(&pmac_irq_hw[i]->enable, 0); | |
cc5d0189 | 486 | |
14cf11af PM |
487 | /* mark level interrupts */ |
488 | for (i = 0; i < max_irqs; i++) | |
489 | if (level_mask[i >> 5] & (1UL << (i & 0x1f))) | |
490 | irq_desc[i].status = IRQ_LEVEL; | |
491 | ||
cc5d0189 BH |
492 | /* Setup handlers for secondary controller and hook cascade irq*/ |
493 | if (slave) { | |
14cf11af | 494 | for ( i = max_real_irqs ; i < max_irqs ; i++ ) |
d1bef4ed | 495 | irq_desc[i].chip = &gatwick_pic; |
14cf11af PM |
496 | setup_irq(irq_cascade, &gatwick_cascade_action); |
497 | } | |
cc5d0189 | 498 | printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs); |
14cf11af PM |
499 | #ifdef CONFIG_XMON |
500 | setup_irq(20, &xmon_action); | |
cc5d0189 BH |
501 | #endif |
502 | } | |
503 | #endif /* CONFIG_PPC32 */ | |
504 | ||
505 | static int pmac_u3_cascade(struct pt_regs *regs, void *data) | |
506 | { | |
507 | return mpic_get_one_irq((struct mpic *)data, regs); | |
508 | } | |
509 | ||
510 | static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic) | |
511 | { | |
512 | #if defined(CONFIG_XMON) && defined(CONFIG_PPC32) | |
513 | struct device_node* pswitch; | |
514 | int nmi_irq; | |
515 | ||
516 | pswitch = of_find_node_by_name(NULL, "programmer-switch"); | |
517 | if (pswitch && pswitch->n_intrs) { | |
518 | nmi_irq = pswitch->intrs[0].line; | |
519 | mpic_irq_set_priority(nmi_irq, 9); | |
520 | setup_irq(nmi_irq, &xmon_action); | |
521 | } | |
522 | of_node_put(pswitch); | |
523 | #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */ | |
524 | } | |
525 | ||
1beb6a7d BH |
526 | static struct mpic * __init pmac_setup_one_mpic(struct device_node *np, |
527 | int master) | |
528 | { | |
529 | unsigned char senses[128]; | |
530 | int offset = master ? 0 : 128; | |
531 | int count = master ? 128 : 124; | |
532 | const char *name = master ? " MPIC 1 " : " MPIC 2 "; | |
533 | struct resource r; | |
534 | struct mpic *mpic; | |
535 | unsigned int flags = master ? MPIC_PRIMARY : 0; | |
536 | int rc; | |
537 | ||
538 | rc = of_address_to_resource(np, 0, &r); | |
539 | if (rc) | |
540 | return NULL; | |
541 | ||
542 | pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0); | |
543 | ||
544 | prom_get_irq_senses(senses, offset, offset + count); | |
545 | ||
546 | flags |= MPIC_WANTS_RESET; | |
547 | if (get_property(np, "big-endian", NULL)) | |
548 | flags |= MPIC_BIG_ENDIAN; | |
549 | ||
550 | /* Primary Big Endian means HT interrupts. This is quite dodgy | |
551 | * but works until I find a better way | |
552 | */ | |
553 | if (master && (flags & MPIC_BIG_ENDIAN)) | |
554 | flags |= MPIC_BROKEN_U3; | |
555 | ||
556 | mpic = mpic_alloc(r.start, flags, 0, offset, count, master ? 252 : 0, | |
557 | senses, count, name); | |
558 | if (mpic == NULL) | |
559 | return NULL; | |
560 | ||
561 | mpic_init(mpic); | |
562 | ||
563 | return mpic; | |
564 | } | |
565 | ||
cc5d0189 BH |
566 | static int __init pmac_pic_probe_mpic(void) |
567 | { | |
568 | struct mpic *mpic1, *mpic2; | |
569 | struct device_node *np, *master = NULL, *slave = NULL; | |
cc5d0189 BH |
570 | |
571 | /* We can have up to 2 MPICs cascaded */ | |
572 | for (np = NULL; (np = of_find_node_by_type(np, "open-pic")) | |
573 | != NULL;) { | |
574 | if (master == NULL && | |
1beb6a7d | 575 | get_property(np, "interrupts", NULL) == NULL) |
cc5d0189 BH |
576 | master = of_node_get(np); |
577 | else if (slave == NULL) | |
578 | slave = of_node_get(np); | |
579 | if (master && slave) | |
580 | break; | |
581 | } | |
582 | ||
583 | /* Check for bogus setups */ | |
584 | if (master == NULL && slave != NULL) { | |
585 | master = slave; | |
586 | slave = NULL; | |
587 | } | |
588 | ||
589 | /* Not found, default to good old pmac pic */ | |
590 | if (master == NULL) | |
591 | return -ENODEV; | |
592 | ||
593 | /* Set master handler */ | |
594 | ppc_md.get_irq = mpic_get_irq; | |
595 | ||
596 | /* Setup master */ | |
1beb6a7d | 597 | mpic1 = pmac_setup_one_mpic(master, 1); |
cc5d0189 | 598 | BUG_ON(mpic1 == NULL); |
cc5d0189 BH |
599 | |
600 | /* Install NMI if any */ | |
601 | pmac_pic_setup_mpic_nmi(mpic1); | |
602 | ||
603 | of_node_put(master); | |
604 | ||
605 | /* No slave, let's go out */ | |
606 | if (slave == NULL || slave->n_intrs < 1) | |
607 | return 0; | |
608 | ||
1beb6a7d | 609 | mpic2 = pmac_setup_one_mpic(slave, 0); |
cc5d0189 | 610 | if (mpic2 == NULL) { |
1beb6a7d BH |
611 | printk(KERN_ERR "Failed to setup slave MPIC\n"); |
612 | of_node_put(slave); | |
cc5d0189 BH |
613 | return 0; |
614 | } | |
cc5d0189 BH |
615 | mpic_setup_cascade(slave->intrs[0].line, pmac_u3_cascade, mpic2); |
616 | ||
617 | of_node_put(slave); | |
618 | return 0; | |
619 | } | |
620 | ||
621 | ||
622 | void __init pmac_pic_init(void) | |
623 | { | |
624 | /* We first try to detect Apple's new Core99 chipset, since mac-io | |
625 | * is quite different on those machines and contains an IBM MPIC2. | |
626 | */ | |
627 | if (pmac_pic_probe_mpic() == 0) | |
628 | return; | |
629 | ||
630 | #ifdef CONFIG_PPC32 | |
631 | pmac_pic_probe_oldstyle(); | |
632 | #endif | |
14cf11af PM |
633 | } |
634 | ||
a0005034 | 635 | #if defined(CONFIG_PM) && defined(CONFIG_PPC32) |
14cf11af PM |
636 | /* |
637 | * These procedures are used in implementing sleep on the powerbooks. | |
638 | * sleep_save_intrs() saves the states of all interrupt enables | |
639 | * and disables all interrupts except for the nominated one. | |
640 | * sleep_restore_intrs() restores the states of all interrupt enables. | |
641 | */ | |
642 | unsigned long sleep_save_mask[2]; | |
643 | ||
644 | /* This used to be passed by the PMU driver but that link got | |
645 | * broken with the new driver model. We use this tweak for now... | |
646 | */ | |
647 | static int pmacpic_find_viaint(void) | |
648 | { | |
649 | int viaint = -1; | |
650 | ||
651 | #ifdef CONFIG_ADB_PMU | |
652 | struct device_node *np; | |
653 | ||
654 | if (pmu_get_model() != PMU_OHARE_BASED) | |
655 | goto not_found; | |
656 | np = of_find_node_by_name(NULL, "via-pmu"); | |
657 | if (np == NULL) | |
658 | goto not_found; | |
659 | viaint = np->intrs[0].line; | |
660 | #endif /* CONFIG_ADB_PMU */ | |
661 | ||
662 | not_found: | |
663 | return viaint; | |
664 | } | |
665 | ||
666 | static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state) | |
667 | { | |
668 | int viaint = pmacpic_find_viaint(); | |
669 | ||
670 | sleep_save_mask[0] = ppc_cached_irq_mask[0]; | |
671 | sleep_save_mask[1] = ppc_cached_irq_mask[1]; | |
672 | ppc_cached_irq_mask[0] = 0; | |
673 | ppc_cached_irq_mask[1] = 0; | |
674 | if (viaint > 0) | |
675 | set_bit(viaint, ppc_cached_irq_mask); | |
676 | out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]); | |
677 | if (max_real_irqs > 32) | |
678 | out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]); | |
679 | (void)in_le32(&pmac_irq_hw[0]->event); | |
680 | /* make sure mask gets to controller before we return to caller */ | |
681 | mb(); | |
682 | (void)in_le32(&pmac_irq_hw[0]->enable); | |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
687 | static int pmacpic_resume(struct sys_device *sysdev) | |
688 | { | |
689 | int i; | |
690 | ||
691 | out_le32(&pmac_irq_hw[0]->enable, 0); | |
692 | if (max_real_irqs > 32) | |
693 | out_le32(&pmac_irq_hw[1]->enable, 0); | |
694 | mb(); | |
695 | for (i = 0; i < max_real_irqs; ++i) | |
696 | if (test_bit(i, sleep_save_mask)) | |
697 | pmac_unmask_irq(i); | |
698 | ||
699 | return 0; | |
700 | } | |
701 | ||
a0005034 | 702 | #endif /* CONFIG_PM && CONFIG_PPC32 */ |
14cf11af PM |
703 | |
704 | static struct sysdev_class pmacpic_sysclass = { | |
705 | set_kset_name("pmac_pic"), | |
706 | }; | |
707 | ||
708 | static struct sys_device device_pmacpic = { | |
709 | .id = 0, | |
710 | .cls = &pmacpic_sysclass, | |
711 | }; | |
712 | ||
713 | static struct sysdev_driver driver_pmacpic = { | |
a0005034 | 714 | #if defined(CONFIG_PM) && defined(CONFIG_PPC32) |
14cf11af PM |
715 | .suspend = &pmacpic_suspend, |
716 | .resume = &pmacpic_resume, | |
a0005034 | 717 | #endif /* CONFIG_PM && CONFIG_PPC32 */ |
14cf11af PM |
718 | }; |
719 | ||
720 | static int __init init_pmacpic_sysfs(void) | |
721 | { | |
3c3f42d6 | 722 | #ifdef CONFIG_PPC32 |
14cf11af PM |
723 | if (max_irqs == 0) |
724 | return -ENODEV; | |
3c3f42d6 | 725 | #endif |
14cf11af PM |
726 | printk(KERN_DEBUG "Registering pmac pic with sysfs...\n"); |
727 | sysdev_class_register(&pmacpic_sysclass); | |
728 | sysdev_register(&device_pmacpic); | |
729 | sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic); | |
730 | return 0; | |
731 | } | |
732 | ||
733 | subsys_initcall(init_pmacpic_sysfs); | |
734 |