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[PATCH] powerpc: Experimental support for new G5 Macs (#2)
[deliverable/linux.git] / arch / powerpc / platforms / powermac / smp.c
CommitLineData
14cf11af
PM		 1/*
2 * SMP support for power macintosh.
3 *
4 * We support both the old "powersurge" SMP architecture
5 * and the current Core99 (G4 PowerMac) machines.
6 *
7 * Note that we don't support the very first rev. of
8 * Apple/DayStar 2 CPUs board, the one with the funky
9 * watchdog. Hopefully, none of these should be there except
10 * maybe internally to Apple. I should probably still add some
11 * code to detect this card though and disable SMP. --BenH.
12 *
13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14 * and Ben Herrenschmidt <benh@kernel.crashing.org>.
15 *
16 * Support for DayStar quad CPU cards
17 * Copyright (C) XLR8, Inc. 1994-2000
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 */
24#include <linux/config.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/smp.h>
28#include <linux/smp_lock.h>
29#include <linux/interrupt.h>
30#include <linux/kernel_stat.h>
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/spinlock.h>
34#include <linux/errno.h>
35#include <linux/hardirq.h>
36#include <linux/cpu.h>
54c4e6b5 37#include <linux/compiler.h>
14cf11af
PM		 38
39#include <asm/ptrace.h>
40#include <asm/atomic.h>
41#include <asm/irq.h>
42#include <asm/page.h>
43#include <asm/pgtable.h>
44#include <asm/sections.h>
45#include <asm/io.h>
46#include <asm/prom.h>
47#include <asm/smp.h>
14cf11af
PM		 48#include <asm/machdep.h>
49#include <asm/pmac_feature.h>
50#include <asm/time.h>
c0c0d996 51#include <asm/mpic.h>
14cf11af
PM		 52#include <asm/cacheflush.h>
53#include <asm/keylargo.h>
35499c01
PM		 54#include <asm/pmac_low_i2c.h>
55
56#undef DEBUG
57
58#ifdef DEBUG
59#define DBG(fmt...) udbg_printf(fmt)
60#else
61#define DBG(fmt...)
62#endif
63
64extern void __secondary_start_pmac_0(void);
65
66#ifdef CONFIG_PPC32
67
68/* Sync flag for HW tb sync */
69static volatile int sec_tb_reset = 0;
14cf11af
PM		 70
71/*
72 * Powersurge (old powermac SMP) support.
73 */
74
14cf11af
PM		 75/* Addresses for powersurge registers */
76#define HAMMERHEAD_BASE 0xf8000000
77#define HHEAD_CONFIG 0x90
78#define HHEAD_SEC_INTR 0xc0
79
80/* register for interrupting the primary processor on the powersurge */
81/* N.B. this is actually the ethernet ROM! */
82#define PSURGE_PRI_INTR 0xf3019000
83
84/* register for storing the start address for the secondary processor */
85/* N.B. this is the PCI config space address register for the 1st bridge */
86#define PSURGE_START 0xf2800000
87
88/* Daystar/XLR8 4-CPU card */
89#define PSURGE_QUAD_REG_ADDR 0xf8800000
90
91#define PSURGE_QUAD_IRQ_SET 0
92#define PSURGE_QUAD_IRQ_CLR 1
93#define PSURGE_QUAD_IRQ_PRIMARY 2
94#define PSURGE_QUAD_CKSTOP_CTL 3
95#define PSURGE_QUAD_PRIMARY_ARB 4
96#define PSURGE_QUAD_BOARD_ID 6
97#define PSURGE_QUAD_WHICH_CPU 7
98#define PSURGE_QUAD_CKSTOP_RDBK 8
99#define PSURGE_QUAD_RESET_CTL 11
100
101#define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
102#define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
103#define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
104#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
105
106/* virtual addresses for the above */
107static volatile u8 __iomem *hhead_base;
108static volatile u8 __iomem *quad_base;
109static volatile u32 __iomem *psurge_pri_intr;
110static volatile u8 __iomem *psurge_sec_intr;
111static volatile u32 __iomem *psurge_start;
112
113/* values for psurge_type */
114#define PSURGE_NONE -1
115#define PSURGE_DUAL 0
116#define PSURGE_QUAD_OKEE 1
117#define PSURGE_QUAD_COTTON 2
118#define PSURGE_QUAD_ICEGRASS 3
119
120/* what sort of powersurge board we have */
121static int psurge_type = PSURGE_NONE;
122
14cf11af
PM		 123/*
124 * Set and clear IPIs for powersurge.
125 */
126static inline void psurge_set_ipi(int cpu)
127{
128 if (psurge_type == PSURGE_NONE)
129 return;
130 if (cpu == 0)
131 in_be32(psurge_pri_intr);
132 else if (psurge_type == PSURGE_DUAL)
133 out_8(psurge_sec_intr, 0);
134 else
135 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
136}
137
138static inline void psurge_clr_ipi(int cpu)
139{
140 if (cpu > 0) {
141 switch(psurge_type) {
142 case PSURGE_DUAL:
143 out_8(psurge_sec_intr, ~0);
144 case PSURGE_NONE:
145 break;
146 default:
147 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
148 }
149 }
150}
151
152/*
153 * On powersurge (old SMP powermac architecture) we don't have
154 * separate IPIs for separate messages like openpic does. Instead
155 * we have a bitmap for each processor, where a 1 bit means that
156 * the corresponding message is pending for that processor.
157 * Ideally each cpu's entry would be in a different cache line.
158 * -- paulus.
159 */
160static unsigned long psurge_smp_message[NR_CPUS];
161
162void psurge_smp_message_recv(struct pt_regs *regs)
163{
164 int cpu = smp_processor_id();
165 int msg;
166
167 /* clear interrupt */
168 psurge_clr_ipi(cpu);
169
170 if (num_online_cpus() < 2)
171 return;
172
173 /* make sure there is a message there */
174 for (msg = 0; msg < 4; msg++)
175 if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
176 smp_message_recv(msg, regs);
177}
178
179irqreturn_t psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
180{
181 psurge_smp_message_recv(regs);
182 return IRQ_HANDLED;
183}
184
7ed476d1 185static void smp_psurge_message_pass(int target, int msg)
14cf11af
PM		 186{
187 int i;
188
189 if (num_online_cpus() < 2)
190 return;
191
192 for (i = 0; i < NR_CPUS; i++) {
193 if (!cpu_online(i))
194 continue;
195 if (target == MSG_ALL
196 || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
197 || target == i) {
198 set_bit(msg, &psurge_smp_message[i]);
199 psurge_set_ipi(i);
200 }
201 }
202}
203
204/*
205 * Determine a quad card presence. We read the board ID register, we
206 * force the data bus to change to something else, and we read it again.
207 * It it's stable, then the register probably exist (ugh !)
208 */
209static int __init psurge_quad_probe(void)
210{
211 int type;
212 unsigned int i;
213
214 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
215 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
216 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
217 return PSURGE_DUAL;
218
219 /* looks OK, try a slightly more rigorous test */
220 /* bogus is not necessarily cacheline-aligned,
221 though I don't suppose that really matters. -- paulus */
222 for (i = 0; i < 100; i++) {
223 volatile u32 bogus[8];
224 bogus[(0+i)%8] = 0x00000000;
225 bogus[(1+i)%8] = 0x55555555;
226 bogus[(2+i)%8] = 0xFFFFFFFF;
227 bogus[(3+i)%8] = 0xAAAAAAAA;
228 bogus[(4+i)%8] = 0x33333333;
229 bogus[(5+i)%8] = 0xCCCCCCCC;
230 bogus[(6+i)%8] = 0xCCCCCCCC;
231 bogus[(7+i)%8] = 0x33333333;
232 wmb();
233 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
234 mb();
235 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
236 return PSURGE_DUAL;
237 }
238 return type;
239}
240
241static void __init psurge_quad_init(void)
242{
243 int procbits;
244
245 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
246 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
247 if (psurge_type == PSURGE_QUAD_ICEGRASS)
248 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
249 else
250 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
251 mdelay(33);
252 out_8(psurge_sec_intr, ~0);
253 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
254 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
255 if (psurge_type != PSURGE_QUAD_ICEGRASS)
256 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
257 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
258 mdelay(33);
259 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
260 mdelay(33);
261 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
262 mdelay(33);
263}
264
265static int __init smp_psurge_probe(void)
266{
267 int i, ncpus;
268
269 /* We don't do SMP on the PPC601 -- paulus */
270 if (PVR_VER(mfspr(SPRN_PVR)) == 1)
271 return 1;
272
273 /*
274 * The powersurge cpu board can be used in the generation
275 * of powermacs that have a socket for an upgradeable cpu card,
276 * including the 7500, 8500, 9500, 9600.
277 * The device tree doesn't tell you if you have 2 cpus because
278 * OF doesn't know anything about the 2nd processor.
279 * Instead we look for magic bits in magic registers,
280 * in the hammerhead memory controller in the case of the
281 * dual-cpu powersurge board. -- paulus.
282 */
283 if (find_devices("hammerhead") == NULL)
284 return 1;
285
286 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
287 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
288 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
289
290 psurge_type = psurge_quad_probe();
291 if (psurge_type != PSURGE_DUAL) {
292 psurge_quad_init();
293 /* All released cards using this HW design have 4 CPUs */
294 ncpus = 4;
295 } else {
296 iounmap(quad_base);
297 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
298 /* not a dual-cpu card */
299 iounmap(hhead_base);
300 psurge_type = PSURGE_NONE;
301 return 1;
302 }
303 ncpus = 2;
304 }
305
306 psurge_start = ioremap(PSURGE_START, 4);
307 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
308
094fe2e7
PM		 309 /*
310 * This is necessary because OF doesn't know about the
311 * secondary cpu(s), and thus there aren't nodes in the
312 * device tree for them, and smp_setup_cpu_maps hasn't
313 * set their bits in cpu_possible_map and cpu_present_map.
314 */
315 if (ncpus > NR_CPUS)
316 ncpus = NR_CPUS;
317 for (i = 1; i < ncpus ; ++i) {
318 cpu_set(i, cpu_present_map);
319 cpu_set(i, cpu_possible_map);
320 set_hard_smp_processor_id(i, i);
321 }
14cf11af
PM		 322
323 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
324
325 return ncpus;
326}
327
328static void __init smp_psurge_kick_cpu(int nr)
329{
330 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
331 unsigned long a;
332
333 /* may need to flush here if secondary bats aren't setup */
334 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
335 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
336 asm volatile("sync");
337
338 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
339
340 out_be32(psurge_start, start);
341 mb();
342
343 psurge_set_ipi(nr);
344 udelay(10);
345 psurge_clr_ipi(nr);
346
347 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
348}
349
350/*
351 * With the dual-cpu powersurge board, the decrementers and timebases
352 * of both cpus are frozen after the secondary cpu is started up,
353 * until we give the secondary cpu another interrupt. This routine
354 * uses this to get the timebases synchronized.
355 * -- paulus.
356 */
357static void __init psurge_dual_sync_tb(int cpu_nr)
358{
359 int t;
360
361 set_dec(tb_ticks_per_jiffy);
094fe2e7 362 /* XXX fixme */
14cf11af 363 set_tb(0, 0);
14cf11af
PM		 364
365 if (cpu_nr > 0) {
366 mb();
367 sec_tb_reset = 1;
368 return;
369 }
370
371 /* wait for the secondary to have reset its TB before proceeding */
372 for (t = 10000000; t > 0 && !sec_tb_reset; --t)
373 ;
374
375 /* now interrupt the secondary, starting both TBs */
376 psurge_set_ipi(1);
14cf11af
PM		 377}
378
379static struct irqaction psurge_irqaction = {
380 .handler = psurge_primary_intr,
381 .flags = SA_INTERRUPT,
382 .mask = CPU_MASK_NONE,
383 .name = "primary IPI",
384};
385
386static void __init smp_psurge_setup_cpu(int cpu_nr)
387{
388
389 if (cpu_nr == 0) {
390 /* If we failed to start the second CPU, we should still
391 * send it an IPI to start the timebase & DEC or we might
392 * have them stuck.
393 */
394 if (num_online_cpus() < 2) {
395 if (psurge_type == PSURGE_DUAL)
396 psurge_set_ipi(1);
397 return;
398 }
399 /* reset the entry point so if we get another intr we won't
400 * try to startup again */
401 out_be32(psurge_start, 0x100);
402 if (setup_irq(30, &psurge_irqaction))
403 printk(KERN_ERR "Couldn't get primary IPI interrupt");
404 }
405
406 if (psurge_type == PSURGE_DUAL)
407 psurge_dual_sync_tb(cpu_nr);
408}
409
410void __init smp_psurge_take_timebase(void)
411{
412 /* Dummy implementation */
413}
414
415void __init smp_psurge_give_timebase(void)
416{
417 /* Dummy implementation */
418}
419
35499c01
PM		 420/* PowerSurge-style Macs */
421struct smp_ops_t psurge_smp_ops = {
422 .message_pass = smp_psurge_message_pass,
423 .probe = smp_psurge_probe,
424 .kick_cpu = smp_psurge_kick_cpu,
425 .setup_cpu = smp_psurge_setup_cpu,
426 .give_timebase = smp_psurge_give_timebase,
427 .take_timebase = smp_psurge_take_timebase,
428};
429#endif /* CONFIG_PPC32 - actually powersurge support */
14cf11af 430
1beb6a7d
BH		 431/*
432 * Core 99 and later support
433 */
434
435static void (*pmac_tb_freeze)(int freeze);
436static unsigned long timebase;
437static int tb_req;
438
439static void smp_core99_give_timebase(void)
440{
441 unsigned long flags;
442
443 local_irq_save(flags);
444
445 while(!tb_req)
446 barrier();
447 tb_req = 0;
448 (*pmac_tb_freeze)(1);
449 mb();
450 timebase = get_tb();
451 mb();
452 while (timebase)
453 barrier();
454 mb();
455 (*pmac_tb_freeze)(0);
456 mb();
457
458 local_irq_restore(flags);
459}
460
461
462static void __devinit smp_core99_take_timebase(void)
463{
464 unsigned long flags;
465
466 local_irq_save(flags);
467
468 tb_req = 1;
469 mb();
470 while (!timebase)
471 barrier();
472 mb();
473 set_tb(timebase >> 32, timebase & 0xffffffff);
474 timebase = 0;
475 mb();
476 set_dec(tb_ticks_per_jiffy/2);
477
478 local_irq_restore(flags);
479}
480
35499c01
PM		 481#ifdef CONFIG_PPC64
482/*
483 * G5s enable/disable the timebase via an i2c-connected clock chip.
484 */
485static struct device_node *pmac_tb_clock_chip_host;
486static u8 pmac_tb_pulsar_addr;
14cf11af 487
35499c01
PM		 488static void smp_core99_cypress_tb_freeze(int freeze)
489{
490 u8 data;
491 int rc;
14cf11af 492
35499c01
PM		 493 /* Strangely, the device-tree says address is 0xd2, but darwin
494 * accesses 0xd0 ...
495 */
1beb6a7d
BH		 496 pmac_low_i2c_setmode(pmac_tb_clock_chip_host,
497 pmac_low_i2c_mode_combined);
35499c01
PM		 498 rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
499 0xd0 | pmac_low_i2c_read,
500 0x81, &data, 1);
501 if (rc != 0)
502 goto bail;
503
504 data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
505
506 pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
507 rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
508 0xd0 | pmac_low_i2c_write,
509 0x81, &data, 1);
510
511 bail:
512 if (rc != 0) {
513 printk("Cypress Timebase %s rc: %d\n",
514 freeze ? "freeze" : "unfreeze", rc);
515 panic("Timebase freeze failed !\n");
14cf11af 516 }
14cf11af
PM		 517}
518
14cf11af 519
35499c01
PM		 520static void smp_core99_pulsar_tb_freeze(int freeze)
521{
522 u8 data;
523 int rc;
524
1beb6a7d
BH		 525 pmac_low_i2c_setmode(pmac_tb_clock_chip_host,
526 pmac_low_i2c_mode_combined);
35499c01
PM		 527 rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
528 pmac_tb_pulsar_addr | pmac_low_i2c_read,
529 0x2e, &data, 1);
530 if (rc != 0)
531 goto bail;
532
533 data = (data & 0x88) | (freeze ? 0x11 : 0x22);
534
535 pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
536 rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
537 pmac_tb_pulsar_addr | pmac_low_i2c_write,
538 0x2e, &data, 1);
539 bail:
540 if (rc != 0) {
541 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
542 freeze ? "freeze" : "unfreeze", rc);
543 panic("Timebase freeze failed !\n");
544 }
545}
14cf11af 546
1beb6a7d 547static void __init smp_core99_setup_i2c_hwsync(int ncpus)
14cf11af 548{
35499c01
PM		 549 struct device_node *cc = NULL;
550 struct device_node *p;
1beb6a7d 551 const char *name = NULL;
35499c01
PM		 552 u32 *reg;
553 int ok;
554
35499c01
PM		 555 /* Look for the clock chip */
556 while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) {
557 p = of_get_parent(cc);
558 ok = p && device_is_compatible(p, "uni-n-i2c");
559 of_node_put(p);
560 if (!ok)
561 continue;
14cf11af 562
35499c01
PM		 563 reg = (u32 *)get_property(cc, "reg", NULL);
564 if (reg == NULL)
565 continue;
14cf11af 566
35499c01
PM		 567 switch (*reg) {
568 case 0xd2:
569 if (device_is_compatible(cc, "pulsar-legacy-slewing")) {
570 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
571 pmac_tb_pulsar_addr = 0xd2;
1beb6a7d 572 name = "Pulsar";
35499c01
PM		 573 } else if (device_is_compatible(cc, "cy28508")) {
574 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
1beb6a7d 575 name = "Cypress";
35499c01
PM		 576 }
577 break;
578 case 0xd4:
579 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
580 pmac_tb_pulsar_addr = 0xd4;
1beb6a7d 581 name = "Pulsar";
35499c01
PM		 582 break;
583 }
1beb6a7d 584 if (pmac_tb_freeze != NULL)
35499c01 585 break;
35499c01 586 }
1beb6a7d
BH		 587 if (pmac_tb_freeze != NULL) {
588 struct device_node *p = of_get_parent(cc);
589 of_node_put(cc);
590 while(p && strcmp(p->type, "i2c")) {
591 cc = of_get_parent(p);
592 of_node_put(p);
593 p = cc;
594 }
595 if (p == NULL)
596 goto no_i2c_sync;
597 /* Open i2c bus for synchronous access */
598 if (pmac_low_i2c_open(p, 0)) {
599 printk(KERN_ERR "Failed top open i2c bus %s for clock"
600 " sync, fallback to software sync !\n",
601 p->full_name);
602 of_node_put(p);
603 goto no_i2c_sync;
604 }
605 pmac_tb_clock_chip_host = p;
606 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n",
607 name);
608 return;
14cf11af 609 }
1beb6a7d
BH		 610 no_i2c_sync:
611 pmac_tb_freeze = NULL;
14cf11af
PM		 612}
613
1beb6a7d 614#endif /* CONFIG_PPC64 */
14cf11af 615
14cf11af 616
35499c01 617/*
1beb6a7d 618 * SMP G4 and newer G5 use a GPIO to enable/disable the timebase.
35499c01 619 */
14cf11af 620
35499c01 621static unsigned int core99_tb_gpio; /* Timebase freeze GPIO */
14cf11af 622
1beb6a7d 623static void smp_core99_gpio_tb_freeze(int freeze)
14cf11af 624{
1beb6a7d
BH		 625 if (freeze)
626 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
627 else
628 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
14cf11af 629 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
35499c01
PM		 630}
631
632/* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
633volatile static long int core99_l2_cache;
634volatile static long int core99_l3_cache;
635
636static void __devinit core99_init_caches(int cpu)
14cf11af 637{
1beb6a7d 638#ifndef CONFIG_PPC64
35499c01 639 if (!cpu_has_feature(CPU_FTR_L2CR))
14cf11af 640 return;
35499c01
PM		 641
642 if (cpu == 0) {
643 core99_l2_cache = _get_L2CR();
644 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
645 } else {
646 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
647 _set_L2CR(0);
648 _set_L2CR(core99_l2_cache);
649 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
14cf11af 650 }
35499c01
PM		 651
652 if (!cpu_has_feature(CPU_FTR_L3CR))
653 return;
654
655 if (cpu == 0){
656 core99_l3_cache = _get_L3CR();
657 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
658 } else {
659 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
660 _set_L3CR(0);
661 _set_L3CR(core99_l3_cache);
662 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
14cf11af 663 }
1beb6a7d 664#endif /* !CONFIG_PPC64 */
14cf11af
PM		 665}
666
35499c01
PM		 667static void __init smp_core99_setup(int ncpus)
668{
1beb6a7d 669#ifdef CONFIG_PPC64
35499c01 670
1beb6a7d
BH		 671 /* i2c based HW sync on some G5s */
672 if (machine_is_compatible("PowerMac7,2") ||
673 machine_is_compatible("PowerMac7,3") ||
674 machine_is_compatible("RackMac3,1"))
675 smp_core99_setup_i2c_hwsync(ncpus);
676
677 /* GPIO based HW sync on recent G5s */
678 if (pmac_tb_freeze == NULL) {
679 struct device_node *np =
680 of_find_node_by_name(NULL, "timebase-enable");
681 u32 *reg = (u32 *)get_property(np, "reg", NULL);
682
683 if (np && reg && !strcmp(np->type, "gpio")) {
684 core99_tb_gpio = *reg;
685 if (core99_tb_gpio < 0x50)
686 core99_tb_gpio += 0x50;
687 pmac_tb_freeze = smp_core99_gpio_tb_freeze;
688 printk(KERN_INFO "Processor timebase sync using"
689 " GPIO 0x%02x\n", core99_tb_gpio);
690 }
35499c01
PM		 691 }
692
1beb6a7d
BH		 693#else /* CONFIG_PPC64 */
694
695 /* GPIO based HW sync on ppc32 Core99 */
696 if (pmac_tb_freeze == NULL && !machine_is_compatible("MacRISC4")) {
697 struct device_node *cpu;
698 u32 *tbprop = NULL;
699
700 core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */
701 cpu = of_find_node_by_type(NULL, "cpu");
702 if (cpu != NULL) {
703 tbprop = (u32 *)get_property(cpu, "timebase-enable",
704 NULL);
705 if (tbprop)
706 core99_tb_gpio = *tbprop;
707 of_node_put(cpu);
708 }
709 pmac_tb_freeze = smp_core99_gpio_tb_freeze;
710 printk(KERN_INFO "Processor timebase sync using"
711 " GPIO 0x%02x\n", core99_tb_gpio);
712 }
713
714#endif /* CONFIG_PPC64 */
715
716 /* No timebase sync, fallback to software */
717 if (pmac_tb_freeze == NULL) {
718 smp_ops->give_timebase = smp_generic_give_timebase;
719 smp_ops->take_timebase = smp_generic_take_timebase;
720 printk(KERN_INFO "Processor timebase sync using software\n");
721 }
722
723#ifndef CONFIG_PPC64
724 {
725 int i;
726
727 /* XXX should get this from reg properties */
728 for (i = 1; i < ncpus; ++i)
729 smp_hw_index[i] = i;
730 }
35499c01
PM		 731#endif
732
1beb6a7d
BH		 733 /* 32 bits SMP can't NAP */
734 if (!machine_is_compatible("MacRISC4"))
735 powersave_nap = 0;
736}
737
35499c01
PM		 738static int __init smp_core99_probe(void)
739{
740 struct device_node *cpus;
741 int ncpus = 0;
742
743 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
744
745 /* Count CPUs in the device-tree */
746 for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
747 ++ncpus;
748
749 printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
750
751 /* Nothing more to do if less than 2 of them */
752 if (ncpus <= 1)
753 return 1;
754
755 smp_core99_setup(ncpus);
756 mpic_request_ipis();
757 core99_init_caches(0);
758
759 return ncpus;
760}
761
762static void __devinit smp_core99_kick_cpu(int nr)
763{
764 unsigned int save_vector;
758438a7 765 unsigned long target, flags;
35499c01
PM		 766 volatile unsigned int *vector
767 = ((volatile unsigned int *)(KERNELBASE+0x100));
768
769 if (nr < 0 || nr > 3)
770 return;
758438a7
ME		 771
772 if (ppc_md.progress)
773 ppc_md.progress("smp_core99_kick_cpu", 0x346);
35499c01
PM		 774
775 local_irq_save(flags);
776 local_irq_disable();
777
778 /* Save reset vector */
779 save_vector = *vector;
780
758438a7 781 /* Setup fake reset vector that does
35499c01
PM		 782 * b __secondary_start_pmac_0 + nr*8 - KERNELBASE
783 */
758438a7
ME		 784 target = (unsigned long) __secondary_start_pmac_0 + nr * 8;
785 create_branch((unsigned long)vector, target, BRANCH_SET_LINK);
35499c01
PM		 786
787 /* Put some life in our friend */
788 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
789
790 /* FIXME: We wait a bit for the CPU to take the exception, I should
791 * instead wait for the entry code to set something for me. Well,
792 * ideally, all that crap will be done in prom.c and the CPU left
793 * in a RAM-based wait loop like CHRP.
794 */
795 mdelay(1);
796
797 /* Restore our exception vector */
798 *vector = save_vector;
799 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
800
801 local_irq_restore(flags);
802 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
803}
804
805static void __devinit smp_core99_setup_cpu(int cpu_nr)
806{
807 /* Setup L2/L3 */
808 if (cpu_nr != 0)
809 core99_init_caches(cpu_nr);
810
811 /* Setup openpic */
812 mpic_setup_this_cpu();
813
814 if (cpu_nr == 0) {
1beb6a7d 815#ifdef CONFIG_PPC64
35499c01
PM		 816 extern void g5_phy_disable_cpu1(void);
817
1beb6a7d
BH		 818 /* Close i2c bus if it was used for tb sync */
819 if (pmac_tb_clock_chip_host) {
820 pmac_low_i2c_close(pmac_tb_clock_chip_host);
821 pmac_tb_clock_chip_host = NULL;
822 }
823
35499c01
PM		 824 /* If we didn't start the second CPU, we must take
825 * it off the bus
826 */
827 if (machine_is_compatible("MacRISC4") &&
828 num_online_cpus() < 2)
829 g5_phy_disable_cpu1();
1beb6a7d
BH		 830#endif /* CONFIG_PPC64 */
831
832 if (ppc_md.progress)
833 ppc_md.progress("core99_setup_cpu 0 done", 0x349);
35499c01
PM		 834 }
835}
14cf11af 836
14cf11af 837
35499c01 838#if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32)
14cf11af 839
094fe2e7 840int smp_core99_cpu_disable(void)
14cf11af
PM		 841{
842 cpu_clear(smp_processor_id(), cpu_online_map);
843
844 /* XXX reset cpu affinity here */
c0c0d996 845 mpic_cpu_set_priority(0xf);
14cf11af
PM		 846 asm volatile("mtdec %0" : : "r" (0x7fffffff));
847 mb();
848 udelay(20);
849 asm volatile("mtdec %0" : : "r" (0x7fffffff));
850 return 0;
851}
852
35499c01 853extern void low_cpu_die(void) __attribute__((noreturn)); /* in sleep.S */
14cf11af
PM		 854static int cpu_dead[NR_CPUS];
855
856void cpu_die(void)
857{
858 local_irq_disable();
859 cpu_dead[smp_processor_id()] = 1;
860 mb();
861 low_cpu_die();
862}
863
094fe2e7 864void smp_core99_cpu_die(unsigned int cpu)
14cf11af
PM		 865{
866 int timeout;
867
868 timeout = 1000;
869 while (!cpu_dead[cpu]) {
870 if (--timeout == 0) {
871 printk("CPU %u refused to die!\n", cpu);
872 break;
873 }
874 msleep(1);
875 }
14cf11af
PM		 876 cpu_dead[cpu] = 0;
877}
878
879#endif
094fe2e7
PM		 880
881/* Core99 Macs (dual G4s and G5s) */
882struct smp_ops_t core99_smp_ops = {
883 .message_pass = smp_mpic_message_pass,
884 .probe = smp_core99_probe,
885 .kick_cpu = smp_core99_kick_cpu,
886 .setup_cpu = smp_core99_setup_cpu,
887 .give_timebase = smp_core99_give_timebase,
888 .take_timebase = smp_core99_take_timebase,
889#if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32)
890 .cpu_disable = smp_core99_cpu_disable,
891 .cpu_die = smp_core99_cpu_die,
892#endif
893};
Linux kernel - Deliverables
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