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powerpc/powernv: don't enable SRIOV when VF BAR has non 64bit-prefetchable BAR
[deliverable/linux.git] / arch / powerpc / platforms / powernv / pci-ioda.c
CommitLineData
184cd4a3
BH		 1/*
2 * Support PCI/PCIe on PowerNV platforms
3 *
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
cee72d5b 12#undef DEBUG
184cd4a3
BH		 13
14#include <linux/kernel.h>
15#include <linux/pci.h>
361f2a2a 16#include <linux/crash_dump.h>
37c367f2 17#include <linux/debugfs.h>
184cd4a3
BH		 18#include <linux/delay.h>
19#include <linux/string.h>
20#include <linux/init.h>
21#include <linux/bootmem.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/msi.h>
cd15b048 25#include <linux/memblock.h>
ac9a5889 26#include <linux/iommu.h>
e57080f1 27#include <linux/rculist.h>
4793d65d 28#include <linux/sizes.h>
184cd4a3
BH		 29
30#include <asm/sections.h>
31#include <asm/io.h>
32#include <asm/prom.h>
33#include <asm/pci-bridge.h>
34#include <asm/machdep.h>
fb1b55d6 35#include <asm/msi_bitmap.h>
184cd4a3
BH		 36#include <asm/ppc-pci.h>
37#include <asm/opal.h>
38#include <asm/iommu.h>
39#include <asm/tce.h>
137436c9 40#include <asm/xics.h>
37c367f2 41#include <asm/debug.h>
262af557 42#include <asm/firmware.h>
80c49c7e 43#include <asm/pnv-pci.h>
aca6913f 44#include <asm/mmzone.h>
80c49c7e 45
ec249dd8 46#include <misc/cxl-base.h>
184cd4a3
BH		 47
48#include "powernv.h"
49#include "pci.h"
50
781a868f
WY		 51/* 256M DMA window, 4K TCE pages, 8 bytes TCE */
52#define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8)
53
bbb845c4
AK		 54#define POWERNV_IOMMU_DEFAULT_LEVELS 1
55#define POWERNV_IOMMU_MAX_LEVELS 5
56
aca6913f
AK		 57static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
58
6d31c2fa
JP		 59static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
60 const char *fmt, ...)
61{
62 struct va_format vaf;
63 va_list args;
64 char pfix[32];
65
66 va_start(args, fmt);
67
68 vaf.fmt = fmt;
69 vaf.va = &args;
70
781a868f 71 if (pe->flags & PNV_IODA_PE_DEV)
6d31c2fa 72 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
781a868f 73 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
6d31c2fa
JP		 74 sprintf(pfix, "%04x:%02x ",
75 pci_domain_nr(pe->pbus), pe->pbus->number);
781a868f
WY		 76#ifdef CONFIG_PCI_IOV
77 else if (pe->flags & PNV_IODA_PE_VF)
78 sprintf(pfix, "%04x:%02x:%2x.%d",
79 pci_domain_nr(pe->parent_dev->bus),
80 (pe->rid & 0xff00) >> 8,
81 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
82#endif /* CONFIG_PCI_IOV*/
6d31c2fa
JP		 83
84 printk("%spci %s: [PE# %.3d] %pV",
85 level, pfix, pe->pe_number, &vaf);
86
87 va_end(args);
88}
184cd4a3 89
6d31c2fa
JP		 90#define pe_err(pe, fmt, ...) \
91 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
92#define pe_warn(pe, fmt, ...) \
93 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
94#define pe_info(pe, fmt, ...) \
95 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
184cd4a3 96
4e287840
TLSC		 97static bool pnv_iommu_bypass_disabled __read_mostly;
98
99static int __init iommu_setup(char *str)
100{
101 if (!str)
102 return -EINVAL;
103
104 while (*str) {
105 if (!strncmp(str, "nobypass", 8)) {
106 pnv_iommu_bypass_disabled = true;
107 pr_info("PowerNV: IOMMU bypass window disabled.\n");
108 break;
109 }
110 str += strcspn(str, ",");
111 if (*str == ',')
112 str++;
113 }
114
115 return 0;
116}
117early_param("iommu", iommu_setup);
118
262af557
GC		 119static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
120{
121 return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
122 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
123}
124
4b82ab18
GS		 125static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
126{
127 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) {
128 pr_warn("%s: Invalid PE %d on PHB#%x\n",
129 __func__, pe_no, phb->hose->global_number);
130 return;
131 }
132
e9dc4d7f
GS		 133 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
134 pr_debug("%s: PE %d was reserved on PHB#%x\n",
135 __func__, pe_no, phb->hose->global_number);
4b82ab18
GS		 136
137 phb->ioda.pe_array[pe_no].phb = phb;
138 phb->ioda.pe_array[pe_no].pe_number = pe_no;
139}
140
cad5cef6 141static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
184cd4a3
BH		 142{
143 unsigned long pe;
144
145 do {
146 pe = find_next_zero_bit(phb->ioda.pe_alloc,
147 phb->ioda.total_pe, 0);
148 if (pe >= phb->ioda.total_pe)
149 return IODA_INVALID_PE;
150 } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
151
4cce9550 152 phb->ioda.pe_array[pe].phb = phb;
184cd4a3
BH		 153 phb->ioda.pe_array[pe].pe_number = pe;
154 return pe;
155}
156
cad5cef6 157static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
184cd4a3
BH		 158{
159 WARN_ON(phb->ioda.pe_array[pe].pdev);
160
161 memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
162 clear_bit(pe, phb->ioda.pe_alloc);
163}
164
262af557
GC		 165/* The default M64 BAR is shared by all PEs */
166static int pnv_ioda2_init_m64(struct pnv_phb *phb)
167{
168 const char *desc;
169 struct resource *r;
170 s64 rc;
171
172 /* Configure the default M64 BAR */
173 rc = opal_pci_set_phb_mem_window(phb->opal_id,
174 OPAL_M64_WINDOW_TYPE,
175 phb->ioda.m64_bar_idx,
176 phb->ioda.m64_base,
177 0, /* unused */
178 phb->ioda.m64_size);
179 if (rc != OPAL_SUCCESS) {
180 desc = "configuring";
181 goto fail;
182 }
183
184 /* Enable the default M64 BAR */
185 rc = opal_pci_phb_mmio_enable(phb->opal_id,
186 OPAL_M64_WINDOW_TYPE,
187 phb->ioda.m64_bar_idx,
188 OPAL_ENABLE_M64_SPLIT);
189 if (rc != OPAL_SUCCESS) {
190 desc = "enabling";
191 goto fail;
192 }
193
194 /* Mark the M64 BAR assigned */
195 set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
196
197 /*
198 * Strip off the segment used by the reserved PE, which is
199 * expected to be 0 or last one of PE capabicity.
200 */
201 r = &phb->hose->mem_resources[1];
202 if (phb->ioda.reserved_pe == 0)
203 r->start += phb->ioda.m64_segsize;
204 else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1))
205 r->end -= phb->ioda.m64_segsize;
206 else
207 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n",
208 phb->ioda.reserved_pe);
209
210 return 0;
211
212fail:
213 pr_warn(" Failure %lld %s M64 BAR#%d\n",
214 rc, desc, phb->ioda.m64_bar_idx);
215 opal_pci_phb_mmio_enable(phb->opal_id,
216 OPAL_M64_WINDOW_TYPE,
217 phb->ioda.m64_bar_idx,
218 OPAL_DISABLE_M64);
219 return -EIO;
220}
221
96a2f92b
GS		 222static void pnv_ioda2_reserve_dev_m64_pe(struct pci_dev *pdev,
223 unsigned long *pe_bitmap)
262af557 224{
96a2f92b
GS		 225 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
226 struct pnv_phb *phb = hose->private_data;
262af557 227 struct resource *r;
96a2f92b
GS		 228 resource_size_t base, sgsz, start, end;
229 int segno, i;
230
231 base = phb->ioda.m64_base;
232 sgsz = phb->ioda.m64_segsize;
233 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
234 r = &pdev->resource[i];
235 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags))
236 continue;
262af557 237
96a2f92b
GS		 238 start = _ALIGN_DOWN(r->start - base, sgsz);
239 end = _ALIGN_UP(r->end - base, sgsz);
240 for (segno = start / sgsz; segno < end / sgsz; segno++) {
241 if (pe_bitmap)
242 set_bit(segno, pe_bitmap);
243 else
244 pnv_ioda_reserve_pe(phb, segno);
262af557
GC		 245 }
246 }
247}
248
96a2f92b
GS		 249static void pnv_ioda2_reserve_m64_pe(struct pci_bus *bus,
250 unsigned long *pe_bitmap,
251 bool all)
262af557 252{
262af557 253 struct pci_dev *pdev;
96a2f92b
GS		 254
255 list_for_each_entry(pdev, &bus->devices, bus_list) {
256 pnv_ioda2_reserve_dev_m64_pe(pdev, pe_bitmap);
257
258 if (all && pdev->subordinate)
259 pnv_ioda2_reserve_m64_pe(pdev->subordinate,
260 pe_bitmap, all);
261 }
262}
263
26ba248d 264static int pnv_ioda2_pick_m64_pe(struct pci_bus *bus, bool all)
262af557 265{
26ba248d
GS		 266 struct pci_controller *hose = pci_bus_to_host(bus);
267 struct pnv_phb *phb = hose->private_data;
262af557
GC		 268 struct pnv_ioda_pe *master_pe, *pe;
269 unsigned long size, *pe_alloc;
26ba248d 270 int i;
262af557
GC		 271
272 /* Root bus shouldn't use M64 */
273 if (pci_is_root_bus(bus))
274 return IODA_INVALID_PE;
275
262af557
GC		 276 /* Allocate bitmap */
277 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
278 pe_alloc = kzalloc(size, GFP_KERNEL);
279 if (!pe_alloc) {
280 pr_warn("%s: Out of memory !\n",
281 __func__);
282 return IODA_INVALID_PE;
283 }
284
26ba248d
GS		 285 /* Figure out reserved PE numbers by the PE */
286 pnv_ioda2_reserve_m64_pe(bus, pe_alloc, all);
262af557
GC		 287
288 /*
289 * the current bus might not own M64 window and that's all
290 * contributed by its child buses. For the case, we needn't
291 * pick M64 dependent PE#.
292 */
293 if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) {
294 kfree(pe_alloc);
295 return IODA_INVALID_PE;
296 }
297
298 /*
299 * Figure out the master PE and put all slave PEs to master
300 * PE's list to form compound PE.
301 */
262af557
GC		 302 master_pe = NULL;
303 i = -1;
304 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) <
305 phb->ioda.total_pe) {
306 pe = &phb->ioda.pe_array[i];
262af557
GC		 307
308 if (!master_pe) {
309 pe->flags |= PNV_IODA_PE_MASTER;
310 INIT_LIST_HEAD(&pe->slaves);
311 master_pe = pe;
312 } else {
313 pe->flags |= PNV_IODA_PE_SLAVE;
314 pe->master = master_pe;
315 list_add_tail(&pe->list, &master_pe->slaves);
316 }
317 }
318
319 kfree(pe_alloc);
320 return master_pe->pe_number;
321}
322
323static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
324{
325 struct pci_controller *hose = phb->hose;
326 struct device_node *dn = hose->dn;
327 struct resource *res;
328 const u32 *r;
329 u64 pci_addr;
330
1665c4a8
GS		 331 /* FIXME: Support M64 for P7IOC */
332 if (phb->type != PNV_PHB_IODA2) {
333 pr_info(" Not support M64 window\n");
334 return;
335 }
336
e4d54f71 337 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
262af557
GC		 338 pr_info(" Firmware too old to support M64 window\n");
339 return;
340 }
341
342 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
343 if (!r) {
344 pr_info(" No <ibm,opal-m64-window> on %s\n",
345 dn->full_name);
346 return;
347 }
348
262af557 349 res = &hose->mem_resources[1];
e80c4e7c 350 res->name = dn->full_name;
262af557
GC		 351 res->start = of_translate_address(dn, r + 2);
352 res->end = res->start + of_read_number(r + 4, 2) - 1;
353 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
354 pci_addr = of_read_number(r, 2);
355 hose->mem_offset[1] = res->start - pci_addr;
356
357 phb->ioda.m64_size = resource_size(res);
358 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe;
359 phb->ioda.m64_base = pci_addr;
360
e9863e68
WY		 361 pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
362 res->start, res->end, pci_addr);
363
262af557
GC		 364 /* Use last M64 BAR to cover M64 window */
365 phb->ioda.m64_bar_idx = 15;
366 phb->init_m64 = pnv_ioda2_init_m64;
5ef73567 367 phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe;
262af557
GC		 368 phb->pick_m64_pe = pnv_ioda2_pick_m64_pe;
369}
370
49dec922
GS		 371static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
372{
373 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
374 struct pnv_ioda_pe *slave;
375 s64 rc;
376
377 /* Fetch master PE */
378 if (pe->flags & PNV_IODA_PE_SLAVE) {
379 pe = pe->master;
ec8e4e9d
GS		 380 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
381 return;
382
49dec922
GS		 383 pe_no = pe->pe_number;
384 }
385
386 /* Freeze master PE */
387 rc = opal_pci_eeh_freeze_set(phb->opal_id,
388 pe_no,
389 OPAL_EEH_ACTION_SET_FREEZE_ALL);
390 if (rc != OPAL_SUCCESS) {
391 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
392 __func__, rc, phb->hose->global_number, pe_no);
393 return;
394 }
395
396 /* Freeze slave PEs */
397 if (!(pe->flags & PNV_IODA_PE_MASTER))
398 return;
399
400 list_for_each_entry(slave, &pe->slaves, list) {
401 rc = opal_pci_eeh_freeze_set(phb->opal_id,
402 slave->pe_number,
403 OPAL_EEH_ACTION_SET_FREEZE_ALL);
404 if (rc != OPAL_SUCCESS)
405 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
406 __func__, rc, phb->hose->global_number,
407 slave->pe_number);
408 }
409}
410
e51df2c1 411static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
49dec922
GS		 412{
413 struct pnv_ioda_pe *pe, *slave;
414 s64 rc;
415
416 /* Find master PE */
417 pe = &phb->ioda.pe_array[pe_no];
418 if (pe->flags & PNV_IODA_PE_SLAVE) {
419 pe = pe->master;
420 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
421 pe_no = pe->pe_number;
422 }
423
424 /* Clear frozen state for master PE */
425 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
426 if (rc != OPAL_SUCCESS) {
427 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
428 __func__, rc, opt, phb->hose->global_number, pe_no);
429 return -EIO;
430 }
431
432 if (!(pe->flags & PNV_IODA_PE_MASTER))
433 return 0;
434
435 /* Clear frozen state for slave PEs */
436 list_for_each_entry(slave, &pe->slaves, list) {
437 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
438 slave->pe_number,
439 opt);
440 if (rc != OPAL_SUCCESS) {
441 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
442 __func__, rc, opt, phb->hose->global_number,
443 slave->pe_number);
444 return -EIO;
445 }
446 }
447
448 return 0;
449}
450
451static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
452{
453 struct pnv_ioda_pe *slave, *pe;
454 u8 fstate, state;
455 __be16 pcierr;
456 s64 rc;
457
458 /* Sanity check on PE number */
459 if (pe_no < 0 || pe_no >= phb->ioda.total_pe)
460 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
461
462 /*
463 * Fetch the master PE and the PE instance might be
464 * not initialized yet.
465 */
466 pe = &phb->ioda.pe_array[pe_no];
467 if (pe->flags & PNV_IODA_PE_SLAVE) {
468 pe = pe->master;
469 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
470 pe_no = pe->pe_number;
471 }
472
473 /* Check the master PE */
474 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
475 &state, &pcierr, NULL);
476 if (rc != OPAL_SUCCESS) {
477 pr_warn("%s: Failure %lld getting "
478 "PHB#%x-PE#%x state\n",
479 __func__, rc,
480 phb->hose->global_number, pe_no);
481 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
482 }
483
484 /* Check the slave PE */
485 if (!(pe->flags & PNV_IODA_PE_MASTER))
486 return state;
487
488 list_for_each_entry(slave, &pe->slaves, list) {
489 rc = opal_pci_eeh_freeze_status(phb->opal_id,
490 slave->pe_number,
491 &fstate,
492 &pcierr,
493 NULL);
494 if (rc != OPAL_SUCCESS) {
495 pr_warn("%s: Failure %lld getting "
496 "PHB#%x-PE#%x state\n",
497 __func__, rc,
498 phb->hose->global_number, slave->pe_number);
499 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
500 }
501
502 /*
503 * Override the result based on the ascending
504 * priority.
505 */
506 if (fstate > state)
507 state = fstate;
508 }
509
510 return state;
511}
512
184cd4a3
BH		 513/* Currently those 2 are only used when MSIs are enabled, this will change
514 * but in the meantime, we need to protect them to avoid warnings
515 */
516#ifdef CONFIG_PCI_MSI
cad5cef6 517static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
184cd4a3
BH		 518{
519 struct pci_controller *hose = pci_bus_to_host(dev->bus);
520 struct pnv_phb *phb = hose->private_data;
b72c1f65 521 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3
BH		 522
523 if (!pdn)
524 return NULL;
525 if (pdn->pe_number == IODA_INVALID_PE)
526 return NULL;
527 return &phb->ioda.pe_array[pdn->pe_number];
528}
184cd4a3
BH		 529#endif /* CONFIG_PCI_MSI */
530
b131a842
GS		 531static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
532 struct pnv_ioda_pe *parent,
533 struct pnv_ioda_pe *child,
534 bool is_add)
535{
536 const char *desc = is_add ? "adding" : "removing";
537 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
538 OPAL_REMOVE_PE_FROM_DOMAIN;
539 struct pnv_ioda_pe *slave;
540 long rc;
541
542 /* Parent PE affects child PE */
543 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
544 child->pe_number, op);
545 if (rc != OPAL_SUCCESS) {
546 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
547 rc, desc);
548 return -ENXIO;
549 }
550
551 if (!(child->flags & PNV_IODA_PE_MASTER))
552 return 0;
553
554 /* Compound case: parent PE affects slave PEs */
555 list_for_each_entry(slave, &child->slaves, list) {
556 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
557 slave->pe_number, op);
558 if (rc != OPAL_SUCCESS) {
559 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
560 rc, desc);
561 return -ENXIO;
562 }
563 }
564
565 return 0;
566}
567
568static int pnv_ioda_set_peltv(struct pnv_phb *phb,
569 struct pnv_ioda_pe *pe,
570 bool is_add)
571{
572 struct pnv_ioda_pe *slave;
781a868f 573 struct pci_dev *pdev = NULL;
b131a842
GS		 574 int ret;
575
576 /*
577 * Clear PE frozen state. If it's master PE, we need
578 * clear slave PE frozen state as well.
579 */
580 if (is_add) {
581 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
582 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
583 if (pe->flags & PNV_IODA_PE_MASTER) {
584 list_for_each_entry(slave, &pe->slaves, list)
585 opal_pci_eeh_freeze_clear(phb->opal_id,
586 slave->pe_number,
587 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
588 }
589 }
590
591 /*
592 * Associate PE in PELT. We need add the PE into the
593 * corresponding PELT-V as well. Otherwise, the error
594 * originated from the PE might contribute to other
595 * PEs.
596 */
597 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
598 if (ret)
599 return ret;
600
601 /* For compound PEs, any one affects all of them */
602 if (pe->flags & PNV_IODA_PE_MASTER) {
603 list_for_each_entry(slave, &pe->slaves, list) {
604 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
605 if (ret)
606 return ret;
607 }
608 }
609
610 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
611 pdev = pe->pbus->self;
781a868f 612 else if (pe->flags & PNV_IODA_PE_DEV)
b131a842 613 pdev = pe->pdev->bus->self;
781a868f
WY		 614#ifdef CONFIG_PCI_IOV
615 else if (pe->flags & PNV_IODA_PE_VF)
283e2d8a 616 pdev = pe->parent_dev;
781a868f 617#endif /* CONFIG_PCI_IOV */
b131a842
GS		 618 while (pdev) {
619 struct pci_dn *pdn = pci_get_pdn(pdev);
620 struct pnv_ioda_pe *parent;
621
622 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
623 parent = &phb->ioda.pe_array[pdn->pe_number];
624 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
625 if (ret)
626 return ret;
627 }
628
629 pdev = pdev->bus->self;
630 }
631
632 return 0;
633}
634
781a868f
WY		 635#ifdef CONFIG_PCI_IOV
636static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
637{
638 struct pci_dev *parent;
639 uint8_t bcomp, dcomp, fcomp;
640 int64_t rc;
641 long rid_end, rid;
642
643 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
644 if (pe->pbus) {
645 int count;
646
647 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
648 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
649 parent = pe->pbus->self;
650 if (pe->flags & PNV_IODA_PE_BUS_ALL)
651 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
652 else
653 count = 1;
654
655 switch(count) {
656 case 1: bcomp = OpalPciBusAll; break;
657 case 2: bcomp = OpalPciBus7Bits; break;
658 case 4: bcomp = OpalPciBus6Bits; break;
659 case 8: bcomp = OpalPciBus5Bits; break;
660 case 16: bcomp = OpalPciBus4Bits; break;
661 case 32: bcomp = OpalPciBus3Bits; break;
662 default:
663 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
664 count);
665 /* Do an exact match only */
666 bcomp = OpalPciBusAll;
667 }
668 rid_end = pe->rid + (count << 8);
669 } else {
670 if (pe->flags & PNV_IODA_PE_VF)
671 parent = pe->parent_dev;
672 else
673 parent = pe->pdev->bus->self;
674 bcomp = OpalPciBusAll;
675 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
676 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
677 rid_end = pe->rid + 1;
678 }
679
680 /* Clear the reverse map */
681 for (rid = pe->rid; rid < rid_end; rid++)
682 phb->ioda.pe_rmap[rid] = 0;
683
684 /* Release from all parents PELT-V */
685 while (parent) {
686 struct pci_dn *pdn = pci_get_pdn(parent);
687 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
688 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
689 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
690 /* XXX What to do in case of error ? */
691 }
692 parent = parent->bus->self;
693 }
694
f951e510 695 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
781a868f
WY		 696 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
697
698 /* Disassociate PE in PELT */
699 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
700 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
701 if (rc)
702 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
703 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
704 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
705 if (rc)
706 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
707
708 pe->pbus = NULL;
709 pe->pdev = NULL;
710 pe->parent_dev = NULL;
711
712 return 0;
713}
714#endif /* CONFIG_PCI_IOV */
715
cad5cef6 716static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
184cd4a3
BH		 717{
718 struct pci_dev *parent;
719 uint8_t bcomp, dcomp, fcomp;
720 long rc, rid_end, rid;
721
722 /* Bus validation ? */
723 if (pe->pbus) {
724 int count;
725
726 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
727 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
728 parent = pe->pbus->self;
fb446ad0
GS		 729 if (pe->flags & PNV_IODA_PE_BUS_ALL)
730 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
731 else
732 count = 1;
733
184cd4a3
BH		 734 switch(count) {
735 case 1: bcomp = OpalPciBusAll; break;
736 case 2: bcomp = OpalPciBus7Bits; break;
737 case 4: bcomp = OpalPciBus6Bits; break;
738 case 8: bcomp = OpalPciBus5Bits; break;
739 case 16: bcomp = OpalPciBus4Bits; break;
740 case 32: bcomp = OpalPciBus3Bits; break;
741 default:
781a868f
WY		 742 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
743 count);
184cd4a3
BH		 744 /* Do an exact match only */
745 bcomp = OpalPciBusAll;
746 }
747 rid_end = pe->rid + (count << 8);
748 } else {
781a868f
WY		 749#ifdef CONFIG_PCI_IOV
750 if (pe->flags & PNV_IODA_PE_VF)
751 parent = pe->parent_dev;
752 else
753#endif /* CONFIG_PCI_IOV */
754 parent = pe->pdev->bus->self;
184cd4a3
BH		 755 bcomp = OpalPciBusAll;
756 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
757 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
758 rid_end = pe->rid + 1;
759 }
760
631ad691
GS		 761 /*
762 * Associate PE in PELT. We need add the PE into the
763 * corresponding PELT-V as well. Otherwise, the error
764 * originated from the PE might contribute to other
765 * PEs.
766 */
184cd4a3
BH		 767 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
768 bcomp, dcomp, fcomp, OPAL_MAP_PE);
769 if (rc) {
770 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
771 return -ENXIO;
772 }
631ad691 773
5d2aa710
AP		 774 /*
775 * Configure PELTV. NPUs don't have a PELTV table so skip
776 * configuration on them.
777 */
778 if (phb->type != PNV_PHB_NPU)
779 pnv_ioda_set_peltv(phb, pe, true);
184cd4a3 780
184cd4a3
BH		 781 /* Setup reverse map */
782 for (rid = pe->rid; rid < rid_end; rid++)
783 phb->ioda.pe_rmap[rid] = pe->pe_number;
784
785 /* Setup one MVTs on IODA1 */
4773f76b
GS		 786 if (phb->type != PNV_PHB_IODA1) {
787 pe->mve_number = 0;
788 goto out;
789 }
790
791 pe->mve_number = pe->pe_number;
792 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
793 if (rc != OPAL_SUCCESS) {
794 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
795 rc, pe->mve_number);
796 pe->mve_number = -1;
797 } else {
798 rc = opal_pci_set_mve_enable(phb->opal_id,
799 pe->mve_number, OPAL_ENABLE_MVE);
184cd4a3 800 if (rc) {
4773f76b 801 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
184cd4a3
BH		 802 rc, pe->mve_number);
803 pe->mve_number = -1;
184cd4a3 804 }
4773f76b 805 }
184cd4a3 806
4773f76b 807out:
184cd4a3
BH		 808 return 0;
809}
810
cad5cef6
GKH		 811static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
812 struct pnv_ioda_pe *pe)
184cd4a3
BH		 813{
814 struct pnv_ioda_pe *lpe;
815
7ebdf956 816 list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
184cd4a3 817 if (lpe->dma_weight < pe->dma_weight) {
7ebdf956 818 list_add_tail(&pe->dma_link, &lpe->dma_link);
184cd4a3
BH		 819 return;
820 }
821 }
7ebdf956 822 list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
184cd4a3
BH		 823}
824
825static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
826{
827 /* This is quite simplistic. The "base" weight of a device
828 * is 10. 0 means no DMA is to be accounted for it.
829 */
830
831 /* If it's a bridge, no DMA */
832 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
833 return 0;
834
835 /* Reduce the weight of slow USB controllers */
836 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
837 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
838 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
839 return 3;
840
841 /* Increase the weight of RAID (includes Obsidian) */
842 if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
843 return 15;
844
845 /* Default */
846 return 10;
847}
848
781a868f
WY		 849#ifdef CONFIG_PCI_IOV
850static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
851{
852 struct pci_dn *pdn = pci_get_pdn(dev);
853 int i;
854 struct resource *res, res2;
855 resource_size_t size;
856 u16 num_vfs;
857
858 if (!dev->is_physfn)
859 return -EINVAL;
860
861 /*
862 * "offset" is in VFs. The M64 windows are sized so that when they
863 * are segmented, each segment is the same size as the IOV BAR.
864 * Each segment is in a separate PE, and the high order bits of the
865 * address are the PE number. Therefore, each VF's BAR is in a
866 * separate PE, and changing the IOV BAR start address changes the
867 * range of PEs the VFs are in.
868 */
869 num_vfs = pdn->num_vfs;
870 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
871 res = &dev->resource[i + PCI_IOV_RESOURCES];
872 if (!res->flags || !res->parent)
873 continue;
874
781a868f
WY		 875 /*
876 * The actual IOV BAR range is determined by the start address
877 * and the actual size for num_vfs VFs BAR. This check is to
878 * make sure that after shifting, the range will not overlap
879 * with another device.
880 */
881 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
882 res2.flags = res->flags;
883 res2.start = res->start + (size * offset);
884 res2.end = res2.start + (size * num_vfs) - 1;
885
886 if (res2.end > res->end) {
887 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
888 i, &res2, res, num_vfs, offset);
889 return -EBUSY;
890 }
891 }
892
893 /*
894 * After doing so, there would be a "hole" in the /proc/iomem when
895 * offset is a positive value. It looks like the device return some
896 * mmio back to the system, which actually no one could use it.
897 */
898 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
899 res = &dev->resource[i + PCI_IOV_RESOURCES];
900 if (!res->flags || !res->parent)
901 continue;
902
781a868f
WY		 903 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
904 res2 = *res;
905 res->start += size * offset;
906
74703cc4
WY		 907 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
908 i, &res2, res, (offset > 0) ? "En" : "Dis",
909 num_vfs, offset);
781a868f
WY		 910 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
911 }
912 return 0;
913}
914#endif /* CONFIG_PCI_IOV */
915
cad5cef6 916static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
184cd4a3
BH		 917{
918 struct pci_controller *hose = pci_bus_to_host(dev->bus);
919 struct pnv_phb *phb = hose->private_data;
b72c1f65 920 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3
BH		 921 struct pnv_ioda_pe *pe;
922 int pe_num;
923
924 if (!pdn) {
925 pr_err("%s: Device tree node not associated properly\n",
926 pci_name(dev));
927 return NULL;
928 }
929 if (pdn->pe_number != IODA_INVALID_PE)
930 return NULL;
931
5d2aa710 932 pe_num = pnv_ioda_alloc_pe(phb);
184cd4a3
BH		 933 if (pe_num == IODA_INVALID_PE) {
934 pr_warning("%s: Not enough PE# available, disabling device\n",
935 pci_name(dev));
936 return NULL;
937 }
938
939 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
940 * pointer in the PE data structure, both should be destroyed at the
941 * same time. However, this needs to be looked at more closely again
942 * once we actually start removing things (Hotplug, SR-IOV, ...)
943 *
944 * At some point we want to remove the PDN completely anyways
945 */
946 pe = &phb->ioda.pe_array[pe_num];
947 pci_dev_get(dev);
948 pdn->pcidev = dev;
949 pdn->pe_number = pe_num;
5d2aa710 950 pe->flags = PNV_IODA_PE_DEV;
184cd4a3
BH		 951 pe->pdev = dev;
952 pe->pbus = NULL;
953 pe->tce32_seg = -1;
954 pe->mve_number = -1;
955 pe->rid = dev->bus->number << 8 | pdn->devfn;
956
957 pe_info(pe, "Associated device to PE\n");
958
959 if (pnv_ioda_configure_pe(phb, pe)) {
960 /* XXX What do we do here ? */
961 if (pe_num)
962 pnv_ioda_free_pe(phb, pe_num);
963 pdn->pe_number = IODA_INVALID_PE;
964 pe->pdev = NULL;
965 pci_dev_put(dev);
966 return NULL;
967 }
968
969 /* Assign a DMA weight to the device */
970 pe->dma_weight = pnv_ioda_dma_weight(dev);
971 if (pe->dma_weight != 0) {
972 phb->ioda.dma_weight += pe->dma_weight;
973 phb->ioda.dma_pe_count++;
974 }
975
976 /* Link the PE */
977 pnv_ioda_link_pe_by_weight(phb, pe);
978
979 return pe;
980}
981
982static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
983{
984 struct pci_dev *dev;
985
986 list_for_each_entry(dev, &bus->devices, bus_list) {
b72c1f65 987 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3
BH		 988
989 if (pdn == NULL) {
990 pr_warn("%s: No device node associated with device !\n",
991 pci_name(dev));
992 continue;
993 }
94973b24 994 pdn->pcidev = dev;
184cd4a3
BH		 995 pdn->pe_number = pe->pe_number;
996 pe->dma_weight += pnv_ioda_dma_weight(dev);
fb446ad0 997 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
184cd4a3
BH		 998 pnv_ioda_setup_same_PE(dev->subordinate, pe);
999 }
1000}
1001
fb446ad0
GS		 1002/*
1003 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1004 * single PCI bus. Another one that contains the primary PCI bus and its
1005 * subordinate PCI devices and buses. The second type of PE is normally
1006 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1007 */
d1203852 1008static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
184cd4a3 1009{
fb446ad0 1010 struct pci_controller *hose = pci_bus_to_host(bus);
184cd4a3 1011 struct pnv_phb *phb = hose->private_data;
184cd4a3 1012 struct pnv_ioda_pe *pe;
262af557
GC		 1013 int pe_num = IODA_INVALID_PE;
1014
1015 /* Check if PE is determined by M64 */
1016 if (phb->pick_m64_pe)
26ba248d 1017 pe_num = phb->pick_m64_pe(bus, all);
262af557
GC		 1018
1019 /* The PE number isn't pinned by M64 */
1020 if (pe_num == IODA_INVALID_PE)
1021 pe_num = pnv_ioda_alloc_pe(phb);
184cd4a3 1022
184cd4a3 1023 if (pe_num == IODA_INVALID_PE) {
fb446ad0
GS		 1024 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1025 __func__, pci_domain_nr(bus), bus->number);
184cd4a3
BH		 1026 return;
1027 }
1028
1029 pe = &phb->ioda.pe_array[pe_num];
262af557 1030 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
184cd4a3
BH		 1031 pe->pbus = bus;
1032 pe->pdev = NULL;
1033 pe->tce32_seg = -1;
1034 pe->mve_number = -1;
b918c62e 1035 pe->rid = bus->busn_res.start << 8;
184cd4a3
BH		 1036 pe->dma_weight = 0;
1037
fb446ad0
GS		 1038 if (all)
1039 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1040 bus->busn_res.start, bus->busn_res.end, pe_num);
1041 else
1042 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1043 bus->busn_res.start, pe_num);
184cd4a3
BH		 1044
1045 if (pnv_ioda_configure_pe(phb, pe)) {
1046 /* XXX What do we do here ? */
1047 if (pe_num)
1048 pnv_ioda_free_pe(phb, pe_num);
1049 pe->pbus = NULL;
1050 return;
1051 }
1052
1053 /* Associate it with all child devices */
1054 pnv_ioda_setup_same_PE(bus, pe);
1055
7ebdf956
GS		 1056 /* Put PE to the list */
1057 list_add_tail(&pe->list, &phb->ioda.pe_list);
1058
184cd4a3
BH		 1059 /* Account for one DMA PE if at least one DMA capable device exist
1060 * below the bridge
1061 */
1062 if (pe->dma_weight != 0) {
1063 phb->ioda.dma_weight += pe->dma_weight;
1064 phb->ioda.dma_pe_count++;
1065 }
1066
1067 /* Link the PE */
1068 pnv_ioda_link_pe_by_weight(phb, pe);
1069}
1070
b521549a
AP		 1071static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1072{
1073 int pe_num, found_pe = false, rc;
1074 long rid;
1075 struct pnv_ioda_pe *pe;
1076 struct pci_dev *gpu_pdev;
1077 struct pci_dn *npu_pdn;
1078 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1079 struct pnv_phb *phb = hose->private_data;
1080
1081 /*
1082 * Due to a hardware errata PE#0 on the NPU is reserved for
1083 * error handling. This means we only have three PEs remaining
1084 * which need to be assigned to four links, implying some
1085 * links must share PEs.
1086 *
1087 * To achieve this we assign PEs such that NPUs linking the
1088 * same GPU get assigned the same PE.
1089 */
1090 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1091 for (pe_num = 0; pe_num < phb->ioda.total_pe; pe_num++) {
1092 pe = &phb->ioda.pe_array[pe_num];
1093 if (!pe->pdev)
1094 continue;
1095
1096 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1097 /*
1098 * This device has the same peer GPU so should
1099 * be assigned the same PE as the existing
1100 * peer NPU.
1101 */
1102 dev_info(&npu_pdev->dev,
1103 "Associating to existing PE %d\n", pe_num);
1104 pci_dev_get(npu_pdev);
1105 npu_pdn = pci_get_pdn(npu_pdev);
1106 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1107 npu_pdn->pcidev = npu_pdev;
1108 npu_pdn->pe_number = pe_num;
1109 pe->dma_weight += pnv_ioda_dma_weight(npu_pdev);
1110 phb->ioda.pe_rmap[rid] = pe->pe_number;
1111
1112 /* Map the PE to this link */
1113 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1114 OpalPciBusAll,
1115 OPAL_COMPARE_RID_DEVICE_NUMBER,
1116 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1117 OPAL_MAP_PE);
1118 WARN_ON(rc != OPAL_SUCCESS);
1119 found_pe = true;
1120 break;
1121 }
1122 }
1123
1124 if (!found_pe)
1125 /*
1126 * Could not find an existing PE so allocate a new
1127 * one.
1128 */
1129 return pnv_ioda_setup_dev_PE(npu_pdev);
1130 else
1131 return pe;
1132}
1133
1134static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
5d2aa710 1135{
5d2aa710
AP		 1136 struct pci_dev *pdev;
1137
1138 list_for_each_entry(pdev, &bus->devices, bus_list)
b521549a 1139 pnv_ioda_setup_npu_PE(pdev);
5d2aa710
AP		 1140}
1141
cad5cef6 1142static void pnv_ioda_setup_PEs(struct pci_bus *bus)
184cd4a3
BH		 1143{
1144 struct pci_dev *dev;
fb446ad0 1145
d1203852 1146 pnv_ioda_setup_bus_PE(bus, false);
184cd4a3
BH		 1147
1148 list_for_each_entry(dev, &bus->devices, bus_list) {
fb446ad0
GS		 1149 if (dev->subordinate) {
1150 if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
d1203852 1151 pnv_ioda_setup_bus_PE(dev->subordinate, true);
fb446ad0
GS		 1152 else
1153 pnv_ioda_setup_PEs(dev->subordinate);
1154 }
1155 }
1156}
1157
1158/*
1159 * Configure PEs so that the downstream PCI buses and devices
1160 * could have their associated PE#. Unfortunately, we didn't
1161 * figure out the way to identify the PLX bridge yet. So we
1162 * simply put the PCI bus and the subordinate behind the root
1163 * port to PE# here. The game rule here is expected to be changed
1164 * as soon as we can detected PLX bridge correctly.
1165 */
cad5cef6 1166static void pnv_pci_ioda_setup_PEs(void)
fb446ad0
GS		 1167{
1168 struct pci_controller *hose, *tmp;
262af557 1169 struct pnv_phb *phb;
fb446ad0
GS		 1170
1171 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
262af557
GC		 1172 phb = hose->private_data;
1173
1174 /* M64 layout might affect PE allocation */
5ef73567 1175 if (phb->reserve_m64_pe)
96a2f92b 1176 phb->reserve_m64_pe(hose->bus, NULL, true);
262af557 1177
5d2aa710
AP		 1178 /*
1179 * On NPU PHB, we expect separate PEs for individual PCI
1180 * functions. PCI bus dependent PEs are required for the
1181 * remaining types of PHBs.
1182 */
08f48f32
AP		 1183 if (phb->type == PNV_PHB_NPU) {
1184 /* PE#0 is needed for error reporting */
1185 pnv_ioda_reserve_pe(phb, 0);
b521549a 1186 pnv_ioda_setup_npu_PEs(hose->bus);
08f48f32 1187 } else
5d2aa710 1188 pnv_ioda_setup_PEs(hose->bus);
184cd4a3
BH		 1189 }
1190}
1191
a8b2f828 1192#ifdef CONFIG_PCI_IOV
781a868f
WY		 1193static int pnv_pci_vf_release_m64(struct pci_dev *pdev)
1194{
1195 struct pci_bus *bus;
1196 struct pci_controller *hose;
1197 struct pnv_phb *phb;
1198 struct pci_dn *pdn;
02639b0e 1199 int i, j;
781a868f
WY		 1200
1201 bus = pdev->bus;
1202 hose = pci_bus_to_host(bus);
1203 phb = hose->private_data;
1204 pdn = pci_get_pdn(pdev);
1205
02639b0e
WY		 1206 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1207 for (j = 0; j < M64_PER_IOV; j++) {
1208 if (pdn->m64_wins[i][j] == IODA_INVALID_M64)
1209 continue;
1210 opal_pci_phb_mmio_enable(phb->opal_id,
1211 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0);
1212 clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc);
1213 pdn->m64_wins[i][j] = IODA_INVALID_M64;
1214 }
781a868f
WY		 1215
1216 return 0;
1217}
1218
02639b0e 1219static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
781a868f
WY		 1220{
1221 struct pci_bus *bus;
1222 struct pci_controller *hose;
1223 struct pnv_phb *phb;
1224 struct pci_dn *pdn;
1225 unsigned int win;
1226 struct resource *res;
02639b0e 1227 int i, j;
781a868f 1228 int64_t rc;
02639b0e
WY		 1229 int total_vfs;
1230 resource_size_t size, start;
1231 int pe_num;
1232 int vf_groups;
1233 int vf_per_group;
781a868f
WY		 1234
1235 bus = pdev->bus;
1236 hose = pci_bus_to_host(bus);
1237 phb = hose->private_data;
1238 pdn = pci_get_pdn(pdev);
02639b0e 1239 total_vfs = pci_sriov_get_totalvfs(pdev);
781a868f
WY		 1240
1241 /* Initialize the m64_wins to IODA_INVALID_M64 */
1242 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
02639b0e
WY		 1243 for (j = 0; j < M64_PER_IOV; j++)
1244 pdn->m64_wins[i][j] = IODA_INVALID_M64;
1245
1246 if (pdn->m64_per_iov == M64_PER_IOV) {
1247 vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV;
1248 vf_per_group = (num_vfs <= M64_PER_IOV)? 1:
1249 roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1250 } else {
1251 vf_groups = 1;
1252 vf_per_group = 1;
1253 }
781a868f
WY		 1254
1255 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1256 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1257 if (!res->flags || !res->parent)
1258 continue;
1259
02639b0e
WY		 1260 for (j = 0; j < vf_groups; j++) {
1261 do {
1262 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1263 phb->ioda.m64_bar_idx + 1, 0);
1264
1265 if (win >= phb->ioda.m64_bar_idx + 1)
1266 goto m64_failed;
1267 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1268
1269 pdn->m64_wins[i][j] = win;
1270
1271 if (pdn->m64_per_iov == M64_PER_IOV) {
1272 size = pci_iov_resource_size(pdev,
1273 PCI_IOV_RESOURCES + i);
1274 size = size * vf_per_group;
1275 start = res->start + size * j;
1276 } else {
1277 size = resource_size(res);
1278 start = res->start;
1279 }
1280
1281 /* Map the M64 here */
1282 if (pdn->m64_per_iov == M64_PER_IOV) {
1283 pe_num = pdn->offset + j;
1284 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1285 pe_num, OPAL_M64_WINDOW_TYPE,
1286 pdn->m64_wins[i][j], 0);
1287 }
1288
1289 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1290 OPAL_M64_WINDOW_TYPE,
1291 pdn->m64_wins[i][j],
1292 start,
1293 0, /* unused */
1294 size);
781a868f 1295
781a868f 1296
02639b0e
WY		 1297 if (rc != OPAL_SUCCESS) {
1298 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1299 win, rc);
1300 goto m64_failed;
1301 }
781a868f 1302
02639b0e
WY		 1303 if (pdn->m64_per_iov == M64_PER_IOV)
1304 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1305 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2);
1306 else
1307 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1308 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1);
781a868f 1309
02639b0e
WY		 1310 if (rc != OPAL_SUCCESS) {
1311 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1312 win, rc);
1313 goto m64_failed;
1314 }
781a868f
WY		 1315 }
1316 }
1317 return 0;
1318
1319m64_failed:
1320 pnv_pci_vf_release_m64(pdev);
1321 return -EBUSY;
1322}
1323
c035e37b
AK		 1324static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1325 int num);
1326static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1327
781a868f
WY		 1328static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1329{
781a868f 1330 struct iommu_table *tbl;
781a868f
WY		 1331 int64_t rc;
1332
b348aa65 1333 tbl = pe->table_group.tables[0];
c035e37b 1334 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
781a868f
WY		 1335 if (rc)
1336 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1337
c035e37b 1338 pnv_pci_ioda2_set_bypass(pe, false);
0eaf4def
AK		 1339 if (pe->table_group.group) {
1340 iommu_group_put(pe->table_group.group);
1341 BUG_ON(pe->table_group.group);
ac9a5889 1342 }
aca6913f 1343 pnv_pci_ioda2_table_free_pages(tbl);
781a868f 1344 iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
781a868f
WY		 1345}
1346
02639b0e 1347static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs)
781a868f
WY		 1348{
1349 struct pci_bus *bus;
1350 struct pci_controller *hose;
1351 struct pnv_phb *phb;
1352 struct pnv_ioda_pe *pe, *pe_n;
1353 struct pci_dn *pdn;
02639b0e
WY		 1354 u16 vf_index;
1355 int64_t rc;
781a868f
WY		 1356
1357 bus = pdev->bus;
1358 hose = pci_bus_to_host(bus);
1359 phb = hose->private_data;
02639b0e 1360 pdn = pci_get_pdn(pdev);
781a868f
WY		 1361
1362 if (!pdev->is_physfn)
1363 return;
1364
02639b0e
WY		 1365 if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1366 int vf_group;
1367 int vf_per_group;
1368 int vf_index1;
1369
1370 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1371
1372 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++)
1373 for (vf_index = vf_group * vf_per_group;
1374 vf_index < (vf_group + 1) * vf_per_group &&
1375 vf_index < num_vfs;
1376 vf_index++)
1377 for (vf_index1 = vf_group * vf_per_group;
1378 vf_index1 < (vf_group + 1) * vf_per_group &&
1379 vf_index1 < num_vfs;
1380 vf_index1++){
1381
1382 rc = opal_pci_set_peltv(phb->opal_id,
1383 pdn->offset + vf_index,
1384 pdn->offset + vf_index1,
1385 OPAL_REMOVE_PE_FROM_DOMAIN);
1386
1387 if (rc)
1388 dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n",
1389 __func__,
1390 pdn->offset + vf_index1, rc);
1391 }
1392 }
1393
781a868f
WY		 1394 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1395 if (pe->parent_dev != pdev)
1396 continue;
1397
1398 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1399
1400 /* Remove from list */
1401 mutex_lock(&phb->ioda.pe_list_mutex);
1402 list_del(&pe->list);
1403 mutex_unlock(&phb->ioda.pe_list_mutex);
1404
1405 pnv_ioda_deconfigure_pe(phb, pe);
1406
1407 pnv_ioda_free_pe(phb, pe->pe_number);
1408 }
1409}
1410
1411void pnv_pci_sriov_disable(struct pci_dev *pdev)
1412{
1413 struct pci_bus *bus;
1414 struct pci_controller *hose;
1415 struct pnv_phb *phb;
1416 struct pci_dn *pdn;
1417 struct pci_sriov *iov;
1418 u16 num_vfs;
1419
1420 bus = pdev->bus;
1421 hose = pci_bus_to_host(bus);
1422 phb = hose->private_data;
1423 pdn = pci_get_pdn(pdev);
1424 iov = pdev->sriov;
1425 num_vfs = pdn->num_vfs;
1426
1427 /* Release VF PEs */
02639b0e 1428 pnv_ioda_release_vf_PE(pdev, num_vfs);
781a868f
WY		 1429
1430 if (phb->type == PNV_PHB_IODA2) {
02639b0e
WY		 1431 if (pdn->m64_per_iov == 1)
1432 pnv_pci_vf_resource_shift(pdev, -pdn->offset);
781a868f
WY		 1433
1434 /* Release M64 windows */
1435 pnv_pci_vf_release_m64(pdev);
1436
1437 /* Release PE numbers */
1438 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1439 pdn->offset = 0;
1440 }
1441}
1442
1443static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1444 struct pnv_ioda_pe *pe);
1445static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1446{
1447 struct pci_bus *bus;
1448 struct pci_controller *hose;
1449 struct pnv_phb *phb;
1450 struct pnv_ioda_pe *pe;
1451 int pe_num;
1452 u16 vf_index;
1453 struct pci_dn *pdn;
02639b0e 1454 int64_t rc;
781a868f
WY		 1455
1456 bus = pdev->bus;
1457 hose = pci_bus_to_host(bus);
1458 phb = hose->private_data;
1459 pdn = pci_get_pdn(pdev);
1460
1461 if (!pdev->is_physfn)
1462 return;
1463
1464 /* Reserve PE for each VF */
1465 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1466 pe_num = pdn->offset + vf_index;
1467
1468 pe = &phb->ioda.pe_array[pe_num];
1469 pe->pe_number = pe_num;
1470 pe->phb = phb;
1471 pe->flags = PNV_IODA_PE_VF;
1472 pe->pbus = NULL;
1473 pe->parent_dev = pdev;
1474 pe->tce32_seg = -1;
1475 pe->mve_number = -1;
1476 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1477 pci_iov_virtfn_devfn(pdev, vf_index);
1478
1479 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1480 hose->global_number, pdev->bus->number,
1481 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1482 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1483
1484 if (pnv_ioda_configure_pe(phb, pe)) {
1485 /* XXX What do we do here ? */
1486 if (pe_num)
1487 pnv_ioda_free_pe(phb, pe_num);
1488 pe->pdev = NULL;
1489 continue;
1490 }
1491
781a868f
WY		 1492 /* Put PE to the list */
1493 mutex_lock(&phb->ioda.pe_list_mutex);
1494 list_add_tail(&pe->list, &phb->ioda.pe_list);
1495 mutex_unlock(&phb->ioda.pe_list_mutex);
1496
1497 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1498 }
02639b0e
WY		 1499
1500 if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1501 int vf_group;
1502 int vf_per_group;
1503 int vf_index1;
1504
1505 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1506
1507 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) {
1508 for (vf_index = vf_group * vf_per_group;
1509 vf_index < (vf_group + 1) * vf_per_group &&
1510 vf_index < num_vfs;
1511 vf_index++) {
1512 for (vf_index1 = vf_group * vf_per_group;
1513 vf_index1 < (vf_group + 1) * vf_per_group &&
1514 vf_index1 < num_vfs;
1515 vf_index1++) {
1516
1517 rc = opal_pci_set_peltv(phb->opal_id,
1518 pdn->offset + vf_index,
1519 pdn->offset + vf_index1,
1520 OPAL_ADD_PE_TO_DOMAIN);
1521
1522 if (rc)
1523 dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n",
1524 __func__,
1525 pdn->offset + vf_index1, rc);
1526 }
1527 }
1528 }
1529 }
781a868f
WY		 1530}
1531
1532int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1533{
1534 struct pci_bus *bus;
1535 struct pci_controller *hose;
1536 struct pnv_phb *phb;
1537 struct pci_dn *pdn;
1538 int ret;
1539
1540 bus = pdev->bus;
1541 hose = pci_bus_to_host(bus);
1542 phb = hose->private_data;
1543 pdn = pci_get_pdn(pdev);
1544
1545 if (phb->type == PNV_PHB_IODA2) {
b0331854
WY		 1546 if (!pdn->vfs_expanded) {
1547 dev_info(&pdev->dev, "don't support this SRIOV device"
1548 " with non 64bit-prefetchable IOV BAR\n");
1549 return -ENOSPC;
1550 }
1551
781a868f
WY		 1552 /* Calculate available PE for required VFs */
1553 mutex_lock(&phb->ioda.pe_alloc_mutex);
1554 pdn->offset = bitmap_find_next_zero_area(
1555 phb->ioda.pe_alloc, phb->ioda.total_pe,
1556 0, num_vfs, 0);
1557 if (pdn->offset >= phb->ioda.total_pe) {
1558 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1559 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1560 pdn->offset = 0;
1561 return -EBUSY;
1562 }
1563 bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1564 pdn->num_vfs = num_vfs;
1565 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1566
1567 /* Assign M64 window accordingly */
02639b0e 1568 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
781a868f
WY		 1569 if (ret) {
1570 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1571 goto m64_failed;
1572 }
1573
1574 /*
1575 * When using one M64 BAR to map one IOV BAR, we need to shift
1576 * the IOV BAR according to the PE# allocated to the VFs.
1577 * Otherwise, the PE# for the VF will conflict with others.
1578 */
02639b0e
WY		 1579 if (pdn->m64_per_iov == 1) {
1580 ret = pnv_pci_vf_resource_shift(pdev, pdn->offset);
1581 if (ret)
1582 goto m64_failed;
1583 }
781a868f
WY		 1584 }
1585
1586 /* Setup VF PEs */
1587 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1588
1589 return 0;
1590
1591m64_failed:
1592 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1593 pdn->offset = 0;
1594
1595 return ret;
1596}
1597
a8b2f828
GS		 1598int pcibios_sriov_disable(struct pci_dev *pdev)
1599{
781a868f
WY		 1600 pnv_pci_sriov_disable(pdev);
1601
a8b2f828
GS		 1602 /* Release PCI data */
1603 remove_dev_pci_data(pdev);
1604 return 0;
1605}
1606
1607int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1608{
1609 /* Allocate PCI data */
1610 add_dev_pci_data(pdev);
781a868f
WY		 1611
1612 pnv_pci_sriov_enable(pdev, num_vfs);
a8b2f828
GS		 1613 return 0;
1614}
1615#endif /* CONFIG_PCI_IOV */
1616
959c9bdd 1617static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
184cd4a3 1618{
b72c1f65 1619 struct pci_dn *pdn = pci_get_pdn(pdev);
959c9bdd 1620 struct pnv_ioda_pe *pe;
184cd4a3 1621
959c9bdd
GS		 1622 /*
1623 * The function can be called while the PE#
1624 * hasn't been assigned. Do nothing for the
1625 * case.
1626 */
1627 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1628 return;
184cd4a3 1629
959c9bdd 1630 pe = &phb->ioda.pe_array[pdn->pe_number];
cd15b048 1631 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
0e1ffef0 1632 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
b348aa65 1633 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
4617082e
AK		 1634 /*
1635 * Note: iommu_add_device() will fail here as
1636 * for physical PE: the device is already added by now;
1637 * for virtual PE: sysfs entries are not ready yet and
1638 * tce_iommu_bus_notifier will add the device to a group later.
1639 */
184cd4a3
BH		 1640}
1641
763d2d8d 1642static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
cd15b048 1643{
763d2d8d
DA		 1644 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1645 struct pnv_phb *phb = hose->private_data;
cd15b048
BH		 1646 struct pci_dn *pdn = pci_get_pdn(pdev);
1647 struct pnv_ioda_pe *pe;
1648 uint64_t top;
1649 bool bypass = false;
5d2aa710
AP		 1650 struct pci_dev *linked_npu_dev;
1651 int i;
cd15b048
BH		 1652
1653 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1654 return -ENODEV;;
1655
1656 pe = &phb->ioda.pe_array[pdn->pe_number];
1657 if (pe->tce_bypass_enabled) {
1658 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1659 bypass = (dma_mask >= top);
1660 }
1661
1662 if (bypass) {
1663 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1664 set_dma_ops(&pdev->dev, &dma_direct_ops);
cd15b048
BH		 1665 } else {
1666 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1667 set_dma_ops(&pdev->dev, &dma_iommu_ops);
cd15b048 1668 }
a32305bf 1669 *pdev->dev.dma_mask = dma_mask;
5d2aa710
AP		 1670
1671 /* Update peer npu devices */
1672 if (pe->flags & PNV_IODA_PE_PEER)
419dbd5e
AP		 1673 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
1674 if (!pe->peers[i])
1675 continue;
1676
5d2aa710
AP		 1677 linked_npu_dev = pe->peers[i]->pdev;
1678 if (dma_get_mask(&linked_npu_dev->dev) != dma_mask)
1679 dma_set_mask(&linked_npu_dev->dev, dma_mask);
1680 }
1681
cd15b048
BH		 1682 return 0;
1683}
1684
53522982 1685static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
fe7e85c6 1686{
53522982
AD		 1687 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1688 struct pnv_phb *phb = hose->private_data;
fe7e85c6
GS		 1689 struct pci_dn *pdn = pci_get_pdn(pdev);
1690 struct pnv_ioda_pe *pe;
1691 u64 end, mask;
1692
1693 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1694 return 0;
1695
1696 pe = &phb->ioda.pe_array[pdn->pe_number];
1697 if (!pe->tce_bypass_enabled)
1698 return __dma_get_required_mask(&pdev->dev);
1699
1700
1701 end = pe->tce_bypass_base + memblock_end_of_DRAM();
1702 mask = 1ULL << (fls64(end) - 1);
1703 mask += mask - 1;
1704
1705 return mask;
1706}
1707
dff4a39e 1708static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
ea30e99e 1709 struct pci_bus *bus)
74251fe2
BH		 1710{
1711 struct pci_dev *dev;
1712
1713 list_for_each_entry(dev, &bus->devices, bus_list) {
b348aa65 1714 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
e91c2511 1715 set_dma_offset(&dev->dev, pe->tce_bypass_base);
4617082e 1716 iommu_add_device(&dev->dev);
dff4a39e 1717
5c89a87d 1718 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
ea30e99e 1719 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
74251fe2
BH		 1720 }
1721}
1722
decbda25
AK		 1723static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
1724 unsigned long index, unsigned long npages, bool rm)
4cce9550 1725{
0eaf4def
AK		 1726 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1727 &tbl->it_group_list, struct iommu_table_group_link,
1728 next);
1729 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
b348aa65 1730 struct pnv_ioda_pe, table_group);
3ad26e5c 1731 __be64 __iomem *invalidate = rm ?
5780fb04
AK		 1732 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1733 pe->phb->ioda.tce_inval_reg;
4cce9550 1734 unsigned long start, end, inc;
b0376c9b 1735 const unsigned shift = tbl->it_page_shift;
4cce9550 1736
decbda25
AK		 1737 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1738 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1739 npages - 1);
4cce9550
GS		 1740
1741 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
1742 if (tbl->it_busno) {
b0376c9b
AK		 1743 start <<= shift;
1744 end <<= shift;
1745 inc = 128ull << shift;
4cce9550
GS		 1746 start |= tbl->it_busno;
1747 end |= tbl->it_busno;
1748 } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
1749 /* p7ioc-style invalidation, 2 TCEs per write */
1750 start |= (1ull << 63);
1751 end |= (1ull << 63);
1752 inc = 16;
1753 } else {
1754 /* Default (older HW) */
1755 inc = 128;
1756 }
1757
1758 end |= inc - 1; /* round up end to be different than start */
1759
1760 mb(); /* Ensure above stores are visible */
1761 while (start <= end) {
8e0a1611 1762 if (rm)
3ad26e5c 1763 __raw_rm_writeq(cpu_to_be64(start), invalidate);
8e0a1611 1764 else
3ad26e5c 1765 __raw_writeq(cpu_to_be64(start), invalidate);
4cce9550
GS		 1766 start += inc;
1767 }
1768
1769 /*
1770 * The iommu layer will do another mb() for us on build()
1771 * and we don't care on free()
1772 */
1773}
1774
decbda25
AK		 1775static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1776 long npages, unsigned long uaddr,
1777 enum dma_data_direction direction,
1778 struct dma_attrs *attrs)
1779{
1780 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1781 attrs);
1782
1783 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1784 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1785
1786 return ret;
1787}
1788
05c6cfb9
AK		 1789#ifdef CONFIG_IOMMU_API
1790static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1791 unsigned long *hpa, enum dma_data_direction *direction)
1792{
1793 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1794
1795 if (!ret && (tbl->it_type &
1796 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1797 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false);
1798
1799 return ret;
1800}
1801#endif
1802
decbda25
AK		 1803static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1804 long npages)
1805{
1806 pnv_tce_free(tbl, index, npages);
1807
1808 if (tbl->it_type & TCE_PCI_SWINV_FREE)
1809 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1810}
1811
da004c36 1812static struct iommu_table_ops pnv_ioda1_iommu_ops = {
decbda25 1813 .set = pnv_ioda1_tce_build,
05c6cfb9
AK		 1814#ifdef CONFIG_IOMMU_API
1815 .exchange = pnv_ioda1_tce_xchg,
1816#endif
decbda25 1817 .clear = pnv_ioda1_tce_free,
da004c36
AK		 1818 .get = pnv_tce_get,
1819};
1820
5780fb04
AK		 1821static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe)
1822{
1823 /* 01xb - invalidate TCEs that match the specified PE# */
1824 unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF);
1825 struct pnv_phb *phb = pe->phb;
5d2aa710
AP		 1826 struct pnv_ioda_pe *npe;
1827 int i;
5780fb04
AK		 1828
1829 if (!phb->ioda.tce_inval_reg)
1830 return;
1831
1832 mb(); /* Ensure above stores are visible */
1833 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
5d2aa710
AP		 1834
1835 if (pe->flags & PNV_IODA_PE_PEER)
1836 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
1837 npe = pe->peers[i];
1838 if (!npe || npe->phb->type != PNV_PHB_NPU)
1839 continue;
1840
1841 pnv_npu_tce_invalidate_entire(npe);
1842 }
5780fb04
AK		 1843}
1844
e57080f1
AK		 1845static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm,
1846 __be64 __iomem *invalidate, unsigned shift,
1847 unsigned long index, unsigned long npages)
4cce9550
GS		 1848{
1849 unsigned long start, end, inc;
4cce9550
GS		 1850
1851 /* We'll invalidate DMA address in PE scope */
b0376c9b 1852 start = 0x2ull << 60;
e57080f1 1853 start |= (pe_number & 0xFF);
4cce9550
GS		 1854 end = start;
1855
1856 /* Figure out the start, end and step */
decbda25
AK		 1857 start |= (index << shift);
1858 end |= ((index + npages - 1) << shift);
b0376c9b 1859 inc = (0x1ull << shift);
4cce9550
GS		 1860 mb();
1861
1862 while (start <= end) {
8e0a1611 1863 if (rm)
3ad26e5c 1864 __raw_rm_writeq(cpu_to_be64(start), invalidate);
8e0a1611 1865 else
3ad26e5c 1866 __raw_writeq(cpu_to_be64(start), invalidate);
4cce9550
GS		 1867 start += inc;
1868 }
1869}
1870
e57080f1
AK		 1871static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1872 unsigned long index, unsigned long npages, bool rm)
1873{
1874 struct iommu_table_group_link *tgl;
1875
1876 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
5d2aa710 1877 struct pnv_ioda_pe *npe;
e57080f1
AK		 1878 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1879 struct pnv_ioda_pe, table_group);
1880 __be64 __iomem *invalidate = rm ?
1881 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1882 pe->phb->ioda.tce_inval_reg;
5d2aa710 1883 int i;
e57080f1
AK		 1884
1885 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm,
1886 invalidate, tbl->it_page_shift,
1887 index, npages);
5d2aa710
AP		 1888
1889 if (pe->flags & PNV_IODA_PE_PEER)
1890 /* Invalidate PEs using the same TCE table */
1891 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
1892 npe = pe->peers[i];
1893 if (!npe || npe->phb->type != PNV_PHB_NPU)
1894 continue;
1895
1896 pnv_npu_tce_invalidate(npe, tbl, index,
1897 npages, rm);
1898 }
e57080f1
AK		 1899 }
1900}
1901
decbda25
AK		 1902static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1903 long npages, unsigned long uaddr,
1904 enum dma_data_direction direction,
1905 struct dma_attrs *attrs)
4cce9550 1906{
decbda25
AK		 1907 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1908 attrs);
4cce9550 1909
decbda25
AK		 1910 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1911 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1912
1913 return ret;
1914}
1915
05c6cfb9
AK		 1916#ifdef CONFIG_IOMMU_API
1917static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1918 unsigned long *hpa, enum dma_data_direction *direction)
1919{
1920 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1921
1922 if (!ret && (tbl->it_type &
1923 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1924 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1925
1926 return ret;
1927}
1928#endif
1929
decbda25
AK		 1930static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1931 long npages)
1932{
1933 pnv_tce_free(tbl, index, npages);
1934
1935 if (tbl->it_type & TCE_PCI_SWINV_FREE)
1936 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
4cce9550
GS		 1937}
1938
4793d65d
AK		 1939static void pnv_ioda2_table_free(struct iommu_table *tbl)
1940{
1941 pnv_pci_ioda2_table_free_pages(tbl);
1942 iommu_free_table(tbl, "pnv");
1943}
1944
da004c36 1945static struct iommu_table_ops pnv_ioda2_iommu_ops = {
decbda25 1946 .set = pnv_ioda2_tce_build,
05c6cfb9
AK		 1947#ifdef CONFIG_IOMMU_API
1948 .exchange = pnv_ioda2_tce_xchg,
1949#endif
decbda25 1950 .clear = pnv_ioda2_tce_free,
da004c36 1951 .get = pnv_tce_get,
4793d65d 1952 .free = pnv_ioda2_table_free,
da004c36
AK		 1953};
1954
cad5cef6
GKH		 1955static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
1956 struct pnv_ioda_pe *pe, unsigned int base,
1957 unsigned int segs)
184cd4a3
BH		 1958{
1959
1960 struct page *tce_mem = NULL;
184cd4a3
BH		 1961 struct iommu_table *tbl;
1962 unsigned int i;
1963 int64_t rc;
1964 void *addr;
1965
184cd4a3
BH		 1966 /* XXX FIXME: Handle 64-bit only DMA devices */
1967 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1968 /* XXX FIXME: Allocate multi-level tables on PHB3 */
1969
1970 /* We shouldn't already have a 32-bit DMA associated */
1971 if (WARN_ON(pe->tce32_seg >= 0))
1972 return;
1973
0eaf4def 1974 tbl = pnv_pci_table_alloc(phb->hose->node);
b348aa65
AK		 1975 iommu_register_group(&pe->table_group, phb->hose->global_number,
1976 pe->pe_number);
0eaf4def 1977 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
c5773822 1978
184cd4a3
BH		 1979 /* Grab a 32-bit TCE table */
1980 pe->tce32_seg = base;
1981 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
1982 (base << 28), ((base + segs) << 28) - 1);
1983
1984 /* XXX Currently, we allocate one big contiguous table for the
1985 * TCEs. We only really need one chunk per 256M of TCE space
1986 * (ie per segment) but that's an optimization for later, it
1987 * requires some added smarts with our get/put_tce implementation
1988 */
1989 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
1990 get_order(TCE32_TABLE_SIZE * segs));
1991 if (!tce_mem) {
1992 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
1993 goto fail;
1994 }
1995 addr = page_address(tce_mem);
1996 memset(addr, 0, TCE32_TABLE_SIZE * segs);
1997
1998 /* Configure HW */
1999 for (i = 0; i < segs; i++) {
2000 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2001 pe->pe_number,
2002 base + i, 1,
2003 __pa(addr) + TCE32_TABLE_SIZE * i,
2004 TCE32_TABLE_SIZE, 0x1000);
2005 if (rc) {
2006 pe_err(pe, " Failed to configure 32-bit TCE table,"
2007 " err %ld\n", rc);
2008 goto fail;
2009 }
2010 }
2011
2012 /* Setup linux iommu table */
184cd4a3 2013 pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
8fa5d454 2014 base << 28, IOMMU_PAGE_SHIFT_4K);
184cd4a3
BH		 2015
2016 /* OPAL variant of P7IOC SW invalidated TCEs */
5780fb04 2017 if (phb->ioda.tce_inval_reg)
65fd766b
GS		 2018 tbl->it_type |= (TCE_PCI_SWINV_CREATE |
2019 TCE_PCI_SWINV_FREE |
2020 TCE_PCI_SWINV_PAIR);
5780fb04 2021
da004c36 2022 tbl->it_ops = &pnv_ioda1_iommu_ops;
4793d65d
AK		 2023 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2024 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
184cd4a3
BH		 2025 iommu_init_table(tbl, phb->hose->node);
2026
781a868f 2027 if (pe->flags & PNV_IODA_PE_DEV) {
4617082e
AK		 2028 /*
2029 * Setting table base here only for carrying iommu_group
2030 * further down to let iommu_add_device() do the job.
2031 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2032 */
2033 set_iommu_table_base(&pe->pdev->dev, tbl);
2034 iommu_add_device(&pe->pdev->dev);
c5773822 2035 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
ea30e99e 2036 pnv_ioda_setup_bus_dma(pe, pe->pbus);
74251fe2 2037
184cd4a3
BH		 2038 return;
2039 fail:
2040 /* XXX Failure: Try to fallback to 64-bit only ? */
2041 if (pe->tce32_seg >= 0)
2042 pe->tce32_seg = -1;
2043 if (tce_mem)
2044 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
0eaf4def
AK		 2045 if (tbl) {
2046 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2047 iommu_free_table(tbl, "pnv");
2048 }
184cd4a3
BH		 2049}
2050
43cb60ab
AK		 2051static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2052 int num, struct iommu_table *tbl)
2053{
2054 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2055 table_group);
2056 struct pnv_phb *phb = pe->phb;
2057 int64_t rc;
bbb845c4
AK		 2058 const unsigned long size = tbl->it_indirect_levels ?
2059 tbl->it_level_size : tbl->it_size;
43cb60ab
AK		 2060 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2061 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2062
4793d65d 2063 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
43cb60ab
AK		 2064 start_addr, start_addr + win_size - 1,
2065 IOMMU_PAGE_SIZE(tbl));
2066
2067 /*
2068 * Map TCE table through TVT. The TVE index is the PE number
2069 * shifted by 1 bit for 32-bits DMA space.
2070 */
2071 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2072 pe->pe_number,
4793d65d 2073 (pe->pe_number << 1) + num,
bbb845c4 2074 tbl->it_indirect_levels + 1,
43cb60ab 2075 __pa(tbl->it_base),
bbb845c4 2076 size << 3,
43cb60ab
AK		 2077 IOMMU_PAGE_SIZE(tbl));
2078 if (rc) {
2079 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2080 return rc;
2081 }
2082
2083 pnv_pci_link_table_and_group(phb->hose->node, num,
2084 tbl, &pe->table_group);
2085 pnv_pci_ioda2_tce_invalidate_entire(pe);
2086
2087 return 0;
2088}
2089
f87a8864 2090static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
cd15b048 2091{
cd15b048
BH		 2092 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2093 int64_t rc;
2094
2095 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2096 if (enable) {
2097 phys_addr_t top = memblock_end_of_DRAM();
2098
2099 top = roundup_pow_of_two(top);
2100 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2101 pe->pe_number,
2102 window_id,
2103 pe->tce_bypass_base,
2104 top);
2105 } else {
2106 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2107 pe->pe_number,
2108 window_id,
2109 pe->tce_bypass_base,
2110 0);
cd15b048
BH		 2111 }
2112 if (rc)
2113 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2114 else
2115 pe->tce_bypass_enabled = enable;
2116}
2117
4793d65d
AK		 2118static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2119 __u32 page_shift, __u64 window_size, __u32 levels,
2120 struct iommu_table *tbl);
2121
2122static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2123 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2124 struct iommu_table **ptbl)
2125{
2126 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2127 table_group);
2128 int nid = pe->phb->hose->node;
2129 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2130 long ret;
2131 struct iommu_table *tbl;
2132
2133 tbl = pnv_pci_table_alloc(nid);
2134 if (!tbl)
2135 return -ENOMEM;
2136
2137 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2138 bus_offset, page_shift, window_size,
2139 levels, tbl);
2140 if (ret) {
2141 iommu_free_table(tbl, "pnv");
2142 return ret;
2143 }
2144
2145 tbl->it_ops = &pnv_ioda2_iommu_ops;
2146 if (pe->phb->ioda.tce_inval_reg)
2147 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2148
2149 *ptbl = tbl;
2150
2151 return 0;
2152}
2153
46d3e1e1
AK		 2154static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2155{
2156 struct iommu_table *tbl = NULL;
2157 long rc;
2158
fa144869
NA		 2159 /*
2160 * crashkernel= specifies the kdump kernel's maximum memory at
2161 * some offset and there is no guaranteed the result is a power
2162 * of 2, which will cause errors later.
2163 */
2164 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2165
bb005455
NA		 2166 /*
2167 * In memory constrained environments, e.g. kdump kernel, the
2168 * DMA window can be larger than available memory, which will
2169 * cause errors later.
2170 */
fa144869 2171 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
bb005455 2172
46d3e1e1
AK		 2173 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2174 IOMMU_PAGE_SHIFT_4K,
bb005455 2175 window_size,
46d3e1e1
AK		 2176 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2177 if (rc) {
2178 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2179 rc);
2180 return rc;
2181 }
2182
2183 iommu_init_table(tbl, pe->phb->hose->node);
2184
2185 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2186 if (rc) {
2187 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2188 rc);
2189 pnv_ioda2_table_free(tbl);
2190 return rc;
2191 }
2192
2193 if (!pnv_iommu_bypass_disabled)
2194 pnv_pci_ioda2_set_bypass(pe, true);
2195
2196 /* OPAL variant of PHB3 invalidated TCEs */
2197 if (pe->phb->ioda.tce_inval_reg)
2198 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2199
2200 /*
2201 * Setting table base here only for carrying iommu_group
2202 * further down to let iommu_add_device() do the job.
2203 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2204 */
2205 if (pe->flags & PNV_IODA_PE_DEV)
2206 set_iommu_table_base(&pe->pdev->dev, tbl);
2207
2208 return 0;
2209}
2210
b5926430
AK		 2211#if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2212static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2213 int num)
2214{
2215 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2216 table_group);
2217 struct pnv_phb *phb = pe->phb;
2218 long ret;
2219
2220 pe_info(pe, "Removing DMA window #%d\n", num);
2221
2222 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2223 (pe->pe_number << 1) + num,
2224 0/* levels */, 0/* table address */,
2225 0/* table size */, 0/* page size */);
2226 if (ret)
2227 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2228 else
2229 pnv_pci_ioda2_tce_invalidate_entire(pe);
2230
2231 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2232
2233 return ret;
2234}
2235#endif
2236
f87a8864 2237#ifdef CONFIG_IOMMU_API
00547193
AK		 2238static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2239 __u64 window_size, __u32 levels)
2240{
2241 unsigned long bytes = 0;
2242 const unsigned window_shift = ilog2(window_size);
2243 unsigned entries_shift = window_shift - page_shift;
2244 unsigned table_shift = entries_shift + 3;
2245 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2246 unsigned long direct_table_size;
2247
2248 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2249 (window_size > memory_hotplug_max()) ||
2250 !is_power_of_2(window_size))
2251 return 0;
2252
2253 /* Calculate a direct table size from window_size and levels */
2254 entries_shift = (entries_shift + levels - 1) / levels;
2255 table_shift = entries_shift + 3;
2256 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2257 direct_table_size = 1UL << table_shift;
2258
2259 for ( ; levels; --levels) {
2260 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2261
2262 tce_table_size /= direct_table_size;
2263 tce_table_size <<= 3;
2264 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2265 }
2266
2267 return bytes;
2268}
2269
f87a8864 2270static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
cd15b048 2271{
f87a8864
AK		 2272 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2273 table_group);
46d3e1e1
AK		 2274 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2275 struct iommu_table *tbl = pe->table_group.tables[0];
cd15b048 2276
f87a8864 2277 pnv_pci_ioda2_set_bypass(pe, false);
46d3e1e1
AK		 2278 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2279 pnv_ioda2_table_free(tbl);
f87a8864 2280}
cd15b048 2281
f87a8864
AK		 2282static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2283{
2284 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2285 table_group);
2286
46d3e1e1 2287 pnv_pci_ioda2_setup_default_config(pe);
cd15b048
BH		 2288}
2289
f87a8864 2290static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
00547193 2291 .get_table_size = pnv_pci_ioda2_get_table_size,
4793d65d
AK		 2292 .create_table = pnv_pci_ioda2_create_table,
2293 .set_window = pnv_pci_ioda2_set_window,
2294 .unset_window = pnv_pci_ioda2_unset_window,
f87a8864
AK		 2295 .take_ownership = pnv_ioda2_take_ownership,
2296 .release_ownership = pnv_ioda2_release_ownership,
2297};
2298#endif
2299
5780fb04
AK		 2300static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb)
2301{
2302 const __be64 *swinvp;
2303
2304 /* OPAL variant of PHB3 invalidated TCEs */
2305 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
2306 if (!swinvp)
2307 return;
2308
2309 phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp);
2310 phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8);
2311}
2312
bbb845c4
AK		 2313static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2314 unsigned levels, unsigned long limit,
3ba3a73e 2315 unsigned long *current_offset, unsigned long *total_allocated)
373f5657
GS		 2316{
2317 struct page *tce_mem = NULL;
bbb845c4 2318 __be64 *addr, *tmp;
aca6913f 2319 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
bbb845c4
AK		 2320 unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2321 unsigned entries = 1UL << (shift - 3);
2322 long i;
aca6913f
AK		 2323
2324 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2325 if (!tce_mem) {
2326 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2327 return NULL;
2328 }
2329 addr = page_address(tce_mem);
bbb845c4 2330 memset(addr, 0, allocated);
3ba3a73e 2331 *total_allocated += allocated;
bbb845c4
AK		 2332
2333 --levels;
2334 if (!levels) {
2335 *current_offset += allocated;
2336 return addr;
2337 }
2338
2339 for (i = 0; i < entries; ++i) {
2340 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
3ba3a73e 2341 levels, limit, current_offset, total_allocated);
bbb845c4
AK		 2342 if (!tmp)
2343 break;
2344
2345 addr[i] = cpu_to_be64(__pa(tmp) |
2346 TCE_PCI_READ | TCE_PCI_WRITE);
2347
2348 if (*current_offset >= limit)
2349 break;
2350 }
aca6913f
AK		 2351
2352 return addr;
2353}
2354
bbb845c4
AK		 2355static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2356 unsigned long size, unsigned level);
2357
aca6913f 2358static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
bbb845c4
AK		 2359 __u32 page_shift, __u64 window_size, __u32 levels,
2360 struct iommu_table *tbl)
aca6913f 2361{
373f5657 2362 void *addr;
3ba3a73e 2363 unsigned long offset = 0, level_shift, total_allocated = 0;
aca6913f
AK		 2364 const unsigned window_shift = ilog2(window_size);
2365 unsigned entries_shift = window_shift - page_shift;
2366 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2367 const unsigned long tce_table_size = 1UL << table_shift;
2368
bbb845c4
AK		 2369 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2370 return -EINVAL;
2371
aca6913f
AK		 2372 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2373 return -EINVAL;
2374
bbb845c4
AK		 2375 /* Adjust direct table size from window_size and levels */
2376 entries_shift = (entries_shift + levels - 1) / levels;
2377 level_shift = entries_shift + 3;
2378 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2379
aca6913f 2380 /* Allocate TCE table */
bbb845c4 2381 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
3ba3a73e 2382 levels, tce_table_size, &offset, &total_allocated);
bbb845c4
AK		 2383
2384 /* addr==NULL means that the first level allocation failed */
aca6913f
AK		 2385 if (!addr)
2386 return -ENOMEM;
2387
bbb845c4
AK		 2388 /*
2389 * First level was allocated but some lower level failed as
2390 * we did not allocate as much as we wanted,
2391 * release partially allocated table.
2392 */
2393 if (offset < tce_table_size) {
2394 pnv_pci_ioda2_table_do_free_pages(addr,
2395 1ULL << (level_shift - 3), levels - 1);
2396 return -ENOMEM;
2397 }
2398
aca6913f
AK		 2399 /* Setup linux iommu table */
2400 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2401 page_shift);
bbb845c4
AK		 2402 tbl->it_level_size = 1ULL << (level_shift - 3);
2403 tbl->it_indirect_levels = levels - 1;
3ba3a73e 2404 tbl->it_allocated_size = total_allocated;
aca6913f
AK		 2405
2406 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2407 window_size, tce_table_size, bus_offset);
2408
2409 return 0;
2410}
2411
bbb845c4
AK		 2412static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2413 unsigned long size, unsigned level)
2414{
2415 const unsigned long addr_ul = (unsigned long) addr &
2416 ~(TCE_PCI_READ | TCE_PCI_WRITE);
2417
2418 if (level) {
2419 long i;
2420 u64 *tmp = (u64 *) addr_ul;
2421
2422 for (i = 0; i < size; ++i) {
2423 unsigned long hpa = be64_to_cpu(tmp[i]);
2424
2425 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2426 continue;
2427
2428 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2429 level - 1);
2430 }
2431 }
2432
2433 free_pages(addr_ul, get_order(size << 3));
2434}
2435
aca6913f
AK		 2436static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2437{
bbb845c4
AK		 2438 const unsigned long size = tbl->it_indirect_levels ?
2439 tbl->it_level_size : tbl->it_size;
2440
aca6913f
AK		 2441 if (!tbl->it_size)
2442 return;
2443
bbb845c4
AK		 2444 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2445 tbl->it_indirect_levels);
aca6913f
AK		 2446}
2447
2448static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2449 struct pnv_ioda_pe *pe)
2450{
373f5657
GS		 2451 int64_t rc;
2452
2453 /* We shouldn't already have a 32-bit DMA associated */
2454 if (WARN_ON(pe->tce32_seg >= 0))
2455 return;
2456
f87a8864
AK		 2457 /* TVE #1 is selected by PCI address bit 59 */
2458 pe->tce_bypass_base = 1ull << 59;
2459
b348aa65
AK		 2460 iommu_register_group(&pe->table_group, phb->hose->global_number,
2461 pe->pe_number);
c5773822 2462
373f5657
GS		 2463 /* The PE will reserve all possible 32-bits space */
2464 pe->tce32_seg = 0;
373f5657 2465 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
aca6913f 2466 phb->ioda.m32_pci_base);
373f5657 2467
aca6913f 2468 /* Setup linux iommu table */
4793d65d
AK		 2469 pe->table_group.tce32_start = 0;
2470 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2471 pe->table_group.max_dynamic_windows_supported =
2472 IOMMU_TABLE_GROUP_MAX_TABLES;
2473 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2474 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
e5aad1e6
AK		 2475#ifdef CONFIG_IOMMU_API
2476 pe->table_group.ops = &pnv_pci_ioda2_ops;
2477#endif
2478
46d3e1e1 2479 rc = pnv_pci_ioda2_setup_default_config(pe);
373f5657 2480 if (rc) {
46d3e1e1
AK		 2481 if (pe->tce32_seg >= 0)
2482 pe->tce32_seg = -1;
2483 return;
373f5657
GS		 2484 }
2485
46d3e1e1 2486 if (pe->flags & PNV_IODA_PE_DEV)
4617082e 2487 iommu_add_device(&pe->pdev->dev);
46d3e1e1 2488 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
ea30e99e 2489 pnv_ioda_setup_bus_dma(pe, pe->pbus);
373f5657
GS		 2490}
2491
cad5cef6 2492static void pnv_ioda_setup_dma(struct pnv_phb *phb)
184cd4a3
BH		 2493{
2494 struct pci_controller *hose = phb->hose;
2495 unsigned int residual, remaining, segs, tw, base;
2496 struct pnv_ioda_pe *pe;
2497
2498 /* If we have more PE# than segments available, hand out one
2499 * per PE until we run out and let the rest fail. If not,
2500 * then we assign at least one segment per PE, plus more based
2501 * on the amount of devices under that PE
2502 */
2503 if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
2504 residual = 0;
2505 else
2506 residual = phb->ioda.tce32_count -
2507 phb->ioda.dma_pe_count;
2508
2509 pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
2510 hose->global_number, phb->ioda.tce32_count);
2511 pr_info("PCI: %d PE# for a total weight of %d\n",
2512 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
2513
5780fb04
AK		 2514 pnv_pci_ioda_setup_opal_tce_kill(phb);
2515
184cd4a3
BH		 2516 /* Walk our PE list and configure their DMA segments, hand them
2517 * out one base segment plus any residual segments based on
2518 * weight
2519 */
2520 remaining = phb->ioda.tce32_count;
2521 tw = phb->ioda.dma_weight;
2522 base = 0;
7ebdf956 2523 list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
184cd4a3
BH		 2524 if (!pe->dma_weight)
2525 continue;
2526 if (!remaining) {
2527 pe_warn(pe, "No DMA32 resources available\n");
2528 continue;
2529 }
2530 segs = 1;
2531 if (residual) {
2532 segs += ((pe->dma_weight * residual) + (tw / 2)) / tw;
2533 if (segs > remaining)
2534 segs = remaining;
2535 }
373f5657
GS		 2536
2537 /*
2538 * For IODA2 compliant PHB3, we needn't care about the weight.
2539 * The all available 32-bits DMA space will be assigned to
2540 * the specific PE.
2541 */
2542 if (phb->type == PNV_PHB_IODA1) {
2543 pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
2544 pe->dma_weight, segs);
2545 pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
5d2aa710 2546 } else if (phb->type == PNV_PHB_IODA2) {
373f5657
GS		 2547 pe_info(pe, "Assign DMA32 space\n");
2548 segs = 0;
2549 pnv_pci_ioda2_setup_dma_pe(phb, pe);
5d2aa710
AP		 2550 } else if (phb->type == PNV_PHB_NPU) {
2551 /*
2552 * We initialise the DMA space for an NPU PHB
2553 * after setup of the PHB is complete as we
2554 * point the NPU TVT to the the same location
2555 * as the PHB3 TVT.
2556 */
373f5657
GS		 2557 }
2558
184cd4a3
BH		 2559 remaining -= segs;
2560 base += segs;
2561 }
2562}
2563
2564#ifdef CONFIG_PCI_MSI
137436c9
GS		 2565static void pnv_ioda2_msi_eoi(struct irq_data *d)
2566{
2567 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2568 struct irq_chip *chip = irq_data_get_irq_chip(d);
2569 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2570 ioda.irq_chip);
2571 int64_t rc;
2572
2573 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2574 WARN_ON_ONCE(rc);
2575
2576 icp_native_eoi(d);
2577}
2578
fd9a1c26
IM		 2579
2580static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2581{
2582 struct irq_data *idata;
2583 struct irq_chip *ichip;
2584
2585 if (phb->type != PNV_PHB_IODA2)
2586 return;
2587
2588 if (!phb->ioda.irq_chip_init) {
2589 /*
2590 * First time we setup an MSI IRQ, we need to setup the
2591 * corresponding IRQ chip to route correctly.
2592 */
2593 idata = irq_get_irq_data(virq);
2594 ichip = irq_data_get_irq_chip(idata);
2595 phb->ioda.irq_chip_init = 1;
2596 phb->ioda.irq_chip = *ichip;
2597 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2598 }
2599 irq_set_chip(virq, &phb->ioda.irq_chip);
2600}
2601
80c49c7e
IM		 2602#ifdef CONFIG_CXL_BASE
2603
6f963ec2 2604struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
80c49c7e
IM		 2605{
2606 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2607
6f963ec2 2608 return of_node_get(hose->dn);
80c49c7e 2609}
6f963ec2 2610EXPORT_SYMBOL(pnv_pci_get_phb_node);
80c49c7e 2611
1212aa1c 2612int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
80c49c7e
IM		 2613{
2614 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2615 struct pnv_phb *phb = hose->private_data;
2616 struct pnv_ioda_pe *pe;
2617 int rc;
2618
2619 pe = pnv_ioda_get_pe(dev);
2620 if (!pe)
2621 return -ENODEV;
2622
2623 pe_info(pe, "Switching PHB to CXL\n");
2624
1212aa1c 2625 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
80c49c7e
IM		 2626 if (rc)
2627 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
2628
2629 return rc;
2630}
1212aa1c 2631EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
80c49c7e
IM		 2632
2633/* Find PHB for cxl dev and allocate MSI hwirqs?
2634 * Returns the absolute hardware IRQ number
2635 */
2636int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
2637{
2638 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2639 struct pnv_phb *phb = hose->private_data;
2640 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
2641
2642 if (hwirq < 0) {
2643 dev_warn(&dev->dev, "Failed to find a free MSI\n");
2644 return -ENOSPC;
2645 }
2646
2647 return phb->msi_base + hwirq;
2648}
2649EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
2650
2651void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
2652{
2653 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2654 struct pnv_phb *phb = hose->private_data;
2655
2656 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
2657}
2658EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
2659
2660void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
2661 struct pci_dev *dev)
2662{
2663 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2664 struct pnv_phb *phb = hose->private_data;
2665 int i, hwirq;
2666
2667 for (i = 1; i < CXL_IRQ_RANGES; i++) {
2668 if (!irqs->range[i])
2669 continue;
2670 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n",
2671 i, irqs->offset[i],
2672 irqs->range[i]);
2673 hwirq = irqs->offset[i] - phb->msi_base;
2674 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
2675 irqs->range[i]);
2676 }
2677}
2678EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
2679
2680int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
2681 struct pci_dev *dev, int num)
2682{
2683 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2684 struct pnv_phb *phb = hose->private_data;
2685 int i, hwirq, try;
2686
2687 memset(irqs, 0, sizeof(struct cxl_irq_ranges));
2688
2689 /* 0 is reserved for the multiplexed PSL DSI interrupt */
2690 for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
2691 try = num;
2692 while (try) {
2693 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
2694 if (hwirq >= 0)
2695 break;
2696 try /= 2;
2697 }
2698 if (!try)
2699 goto fail;
2700
2701 irqs->offset[i] = phb->msi_base + hwirq;
2702 irqs->range[i] = try;
2703 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n",
2704 i, irqs->offset[i], irqs->range[i]);
2705 num -= try;
2706 }
2707 if (num)
2708 goto fail;
2709
2710 return 0;
2711fail:
2712 pnv_cxl_release_hwirq_ranges(irqs, dev);
2713 return -ENOSPC;
2714}
2715EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
2716
2717int pnv_cxl_get_irq_count(struct pci_dev *dev)
2718{
2719 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2720 struct pnv_phb *phb = hose->private_data;
2721
2722 return phb->msi_bmp.irq_count;
2723}
2724EXPORT_SYMBOL(pnv_cxl_get_irq_count);
2725
2726int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
2727 unsigned int virq)
2728{
2729 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2730 struct pnv_phb *phb = hose->private_data;
2731 unsigned int xive_num = hwirq - phb->msi_base;
2732 struct pnv_ioda_pe *pe;
2733 int rc;
2734
2735 if (!(pe = pnv_ioda_get_pe(dev)))
2736 return -ENODEV;
2737
2738 /* Assign XIVE to PE */
2739 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2740 if (rc) {
2741 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
2742 "hwirq 0x%x XIVE 0x%x PE\n",
2743 pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
2744 return -EIO;
2745 }
2746 set_msi_irq_chip(phb, virq);
2747
2748 return 0;
2749}
2750EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
2751#endif
2752
184cd4a3 2753static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
137436c9
GS		 2754 unsigned int hwirq, unsigned int virq,
2755 unsigned int is_64, struct msi_msg *msg)
184cd4a3
BH		 2756{
2757 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2758 unsigned int xive_num = hwirq - phb->msi_base;
3a1a4661 2759 __be32 data;
184cd4a3
BH		 2760 int rc;
2761
2762 /* No PE assigned ? bail out ... no MSI for you ! */
2763 if (pe == NULL)
2764 return -ENXIO;
2765
2766 /* Check if we have an MVE */
2767 if (pe->mve_number < 0)
2768 return -ENXIO;
2769
b72c1f65 2770 /* Force 32-bit MSI on some broken devices */
36074381 2771 if (dev->no_64bit_msi)
b72c1f65
BH		 2772 is_64 = 0;
2773
184cd4a3
BH		 2774 /* Assign XIVE to PE */
2775 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2776 if (rc) {
2777 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2778 pci_name(dev), rc, xive_num);
2779 return -EIO;
2780 }
2781
2782 if (is_64) {
3a1a4661
BH		 2783 __be64 addr64;
2784
184cd4a3
BH		 2785 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2786 &addr64, &data);
2787 if (rc) {
2788 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2789 pci_name(dev), rc);
2790 return -EIO;
2791 }
3a1a4661
BH		 2792 msg->address_hi = be64_to_cpu(addr64) >> 32;
2793 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
184cd4a3 2794 } else {
3a1a4661
BH		 2795 __be32 addr32;
2796
184cd4a3
BH		 2797 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2798 &addr32, &data);
2799 if (rc) {
2800 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2801 pci_name(dev), rc);
2802 return -EIO;
2803 }
2804 msg->address_hi = 0;
3a1a4661 2805 msg->address_lo = be32_to_cpu(addr32);
184cd4a3 2806 }
3a1a4661 2807 msg->data = be32_to_cpu(data);
184cd4a3 2808
fd9a1c26 2809 set_msi_irq_chip(phb, virq);
137436c9 2810
184cd4a3
BH		 2811 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2812 " address=%x_%08x data=%x PE# %d\n",
2813 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2814 msg->address_hi, msg->address_lo, data, pe->pe_number);
2815
2816 return 0;
2817}
2818
2819static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2820{
fb1b55d6 2821 unsigned int count;
184cd4a3
BH		 2822 const __be32 *prop = of_get_property(phb->hose->dn,
2823 "ibm,opal-msi-ranges", NULL);
2824 if (!prop) {
2825 /* BML Fallback */
2826 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2827 }
2828 if (!prop)
2829 return;
2830
2831 phb->msi_base = be32_to_cpup(prop);
fb1b55d6
GS		 2832 count = be32_to_cpup(prop + 1);
2833 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
184cd4a3
BH		 2834 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2835 phb->hose->global_number);
2836 return;
2837 }
fb1b55d6 2838
184cd4a3
BH		 2839 phb->msi_setup = pnv_pci_ioda_msi_setup;
2840 phb->msi32_support = 1;
2841 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
fb1b55d6 2842 count, phb->msi_base);
184cd4a3
BH		 2843}
2844#else
2845static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2846#endif /* CONFIG_PCI_MSI */
2847
6e628c7d
WY		 2848#ifdef CONFIG_PCI_IOV
2849static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2850{
2851 struct pci_controller *hose;
2852 struct pnv_phb *phb;
2853 struct resource *res;
2854 int i;
2855 resource_size_t size;
2856 struct pci_dn *pdn;
5b88ec22 2857 int mul, total_vfs;
6e628c7d
WY		 2858
2859 if (!pdev->is_physfn || pdev->is_added)
2860 return;
2861
2862 hose = pci_bus_to_host(pdev->bus);
2863 phb = hose->private_data;
2864
2865 pdn = pci_get_pdn(pdev);
2866 pdn->vfs_expanded = 0;
2867
5b88ec22
WY		 2868 total_vfs = pci_sriov_get_totalvfs(pdev);
2869 pdn->m64_per_iov = 1;
2870 mul = phb->ioda.total_pe;
2871
2872 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2873 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2874 if (!res->flags || res->parent)
2875 continue;
2876 if (!pnv_pci_is_mem_pref_64(res->flags)) {
b0331854
WY		 2877 dev_warn(&pdev->dev, "Don't support SR-IOV with"
2878 " non M64 VF BAR%d: %pR. \n",
5b88ec22 2879 i, res);
b0331854 2880 goto truncate_iov;
5b88ec22
WY		 2881 }
2882
2883 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2884
2885 /* bigger than 64M */
2886 if (size > (1 << 26)) {
2887 dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n",
2888 i, res);
2889 pdn->m64_per_iov = M64_PER_IOV;
2890 mul = roundup_pow_of_two(total_vfs);
2891 break;
2892 }
2893 }
2894
6e628c7d
WY		 2895 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2896 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2897 if (!res->flags || res->parent)
2898 continue;
6e628c7d
WY		 2899
2900 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2901 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
5b88ec22 2902 res->end = res->start + size * mul - 1;
6e628c7d
WY		 2903 dev_dbg(&pdev->dev, " %pR\n", res);
2904 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
5b88ec22 2905 i, res, mul);
6e628c7d 2906 }
5b88ec22 2907 pdn->vfs_expanded = mul;
b0331854
WY		 2908
2909 return;
2910
2911truncate_iov:
2912 /* To save MMIO space, IOV BAR is truncated. */
2913 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2914 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2915 res->flags = 0;
2916 res->end = res->start - 1;
2917 }
6e628c7d
WY		 2918}
2919#endif /* CONFIG_PCI_IOV */
2920
11685bec
GS		 2921/*
2922 * This function is supposed to be called on basis of PE from top
2923 * to bottom style. So the the I/O or MMIO segment assigned to
2924 * parent PE could be overrided by its child PEs if necessary.
2925 */
cad5cef6
GKH		 2926static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
2927 struct pnv_ioda_pe *pe)
11685bec
GS		 2928{
2929 struct pnv_phb *phb = hose->private_data;
2930 struct pci_bus_region region;
2931 struct resource *res;
2932 int i, index;
2933 int rc;
2934
2935 /*
2936 * NOTE: We only care PCI bus based PE for now. For PCI
2937 * device based PE, for example SRIOV sensitive VF should
2938 * be figured out later.
2939 */
2940 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
2941
2942 pci_bus_for_each_resource(pe->pbus, res, i) {
2943 if (!res || !res->flags ||
2944 res->start > res->end)
2945 continue;
2946
2947 if (res->flags & IORESOURCE_IO) {
2948 region.start = res->start - phb->ioda.io_pci_base;
2949 region.end = res->end - phb->ioda.io_pci_base;
2950 index = region.start / phb->ioda.io_segsize;
2951
2952 while (index < phb->ioda.total_pe &&
2953 region.start <= region.end) {
2954 phb->ioda.io_segmap[index] = pe->pe_number;
2955 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2956 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2957 if (rc != OPAL_SUCCESS) {
2958 pr_err("%s: OPAL error %d when mapping IO "
2959 "segment #%d to PE#%d\n",
2960 __func__, rc, index, pe->pe_number);
2961 break;
2962 }
2963
2964 region.start += phb->ioda.io_segsize;
2965 index++;
2966 }
027fa02f
GS		 2967 } else if ((res->flags & IORESOURCE_MEM) &&
2968 !pnv_pci_is_mem_pref_64(res->flags)) {
11685bec 2969 region.start = res->start -
3fd47f06 2970 hose->mem_offset[0] -
11685bec
GS		 2971 phb->ioda.m32_pci_base;
2972 region.end = res->end -
3fd47f06 2973 hose->mem_offset[0] -
11685bec
GS		 2974 phb->ioda.m32_pci_base;
2975 index = region.start / phb->ioda.m32_segsize;
2976
2977 while (index < phb->ioda.total_pe &&
2978 region.start <= region.end) {
2979 phb->ioda.m32_segmap[index] = pe->pe_number;
2980 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2981 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2982 if (rc != OPAL_SUCCESS) {
2983 pr_err("%s: OPAL error %d when mapping M32 "
2984 "segment#%d to PE#%d",
2985 __func__, rc, index, pe->pe_number);
2986 break;
2987 }
2988
2989 region.start += phb->ioda.m32_segsize;
2990 index++;
2991 }
2992 }
2993 }
2994}
2995
cad5cef6 2996static void pnv_pci_ioda_setup_seg(void)
11685bec
GS		 2997{
2998 struct pci_controller *tmp, *hose;
2999 struct pnv_phb *phb;
3000 struct pnv_ioda_pe *pe;
3001
3002 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3003 phb = hose->private_data;
5d2aa710
AP		 3004
3005 /* NPU PHB does not support IO or MMIO segmentation */
3006 if (phb->type == PNV_PHB_NPU)
3007 continue;
3008
11685bec
GS		 3009 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
3010 pnv_ioda_setup_pe_seg(hose, pe);
3011 }
3012 }
3013}
3014
cad5cef6 3015static void pnv_pci_ioda_setup_DMA(void)
13395c48
GS		 3016{
3017 struct pci_controller *hose, *tmp;
db1266c8 3018 struct pnv_phb *phb;
13395c48
GS		 3019
3020 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3021 pnv_ioda_setup_dma(hose->private_data);
db1266c8
GS		 3022
3023 /* Mark the PHB initialization done */
3024 phb = hose->private_data;
3025 phb->initialized = 1;
13395c48
GS		 3026 }
3027}
3028
37c367f2
GS		 3029static void pnv_pci_ioda_create_dbgfs(void)
3030{
3031#ifdef CONFIG_DEBUG_FS
3032 struct pci_controller *hose, *tmp;
3033 struct pnv_phb *phb;
3034 char name[16];
3035
3036 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3037 phb = hose->private_data;
3038
3039 sprintf(name, "PCI%04x", hose->global_number);
3040 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3041 if (!phb->dbgfs)
3042 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3043 __func__, hose->global_number);
3044 }
3045#endif /* CONFIG_DEBUG_FS */
3046}
3047
5d2aa710
AP		 3048static void pnv_npu_ioda_fixup(void)
3049{
3050 bool enable_bypass;
3051 struct pci_controller *hose, *tmp;
3052 struct pnv_phb *phb;
3053 struct pnv_ioda_pe *pe;
3054
3055 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3056 phb = hose->private_data;
3057 if (phb->type != PNV_PHB_NPU)
3058 continue;
3059
3060 list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
3061 enable_bypass = dma_get_mask(&pe->pdev->dev) ==
3062 DMA_BIT_MASK(64);
3063 pnv_npu_init_dma_pe(pe);
3064 pnv_npu_dma_set_bypass(pe, enable_bypass);
3065 }
3066 }
3067}
3068
cad5cef6 3069static void pnv_pci_ioda_fixup(void)
fb446ad0
GS		 3070{
3071 pnv_pci_ioda_setup_PEs();
11685bec 3072 pnv_pci_ioda_setup_seg();
13395c48 3073 pnv_pci_ioda_setup_DMA();
e9cc17d4 3074
37c367f2
GS		 3075 pnv_pci_ioda_create_dbgfs();
3076
e9cc17d4 3077#ifdef CONFIG_EEH
e9cc17d4 3078 eeh_init();
dadcd6d6 3079 eeh_addr_cache_build();
e9cc17d4 3080#endif
5d2aa710
AP		 3081
3082 /* Link NPU IODA tables to their PCI devices. */
3083 pnv_npu_ioda_fixup();
fb446ad0
GS		 3084}
3085
271fd03a
GS		 3086/*
3087 * Returns the alignment for I/O or memory windows for P2P
3088 * bridges. That actually depends on how PEs are segmented.
3089 * For now, we return I/O or M32 segment size for PE sensitive
3090 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3091 * 1MiB for memory) will be returned.
3092 *
3093 * The current PCI bus might be put into one PE, which was
3094 * create against the parent PCI bridge. For that case, we
3095 * needn't enlarge the alignment so that we can save some
3096 * resources.
3097 */
3098static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3099 unsigned long type)
3100{
3101 struct pci_dev *bridge;
3102 struct pci_controller *hose = pci_bus_to_host(bus);
3103 struct pnv_phb *phb = hose->private_data;
3104 int num_pci_bridges = 0;
3105
3106 bridge = bus->self;
3107 while (bridge) {
3108 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3109 num_pci_bridges++;
3110 if (num_pci_bridges >= 2)
3111 return 1;
3112 }
3113
3114 bridge = bridge->bus->self;
3115 }
3116
262af557
GC		 3117 /* We fail back to M32 if M64 isn't supported */
3118 if (phb->ioda.m64_segsize &&
3119 pnv_pci_is_mem_pref_64(type))
3120 return phb->ioda.m64_segsize;
271fd03a
GS		 3121 if (type & IORESOURCE_MEM)
3122 return phb->ioda.m32_segsize;
3123
3124 return phb->ioda.io_segsize;
3125}
3126
5350ab3f
WY		 3127#ifdef CONFIG_PCI_IOV
3128static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3129 int resno)
3130{
3131 struct pci_dn *pdn = pci_get_pdn(pdev);
3132 resource_size_t align, iov_align;
3133
3134 iov_align = resource_size(&pdev->resource[resno]);
3135 if (iov_align)
3136 return iov_align;
3137
3138 align = pci_iov_resource_size(pdev, resno);
3139 if (pdn->vfs_expanded)
3140 return pdn->vfs_expanded * align;
3141
3142 return align;
3143}
3144#endif /* CONFIG_PCI_IOV */
3145
184cd4a3
BH		 3146/* Prevent enabling devices for which we couldn't properly
3147 * assign a PE
3148 */
c88c2a18 3149static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
184cd4a3 3150{
db1266c8
GS		 3151 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3152 struct pnv_phb *phb = hose->private_data;
3153 struct pci_dn *pdn;
184cd4a3 3154
db1266c8
GS		 3155 /* The function is probably called while the PEs have
3156 * not be created yet. For example, resource reassignment
3157 * during PCI probe period. We just skip the check if
3158 * PEs isn't ready.
3159 */
3160 if (!phb->initialized)
c88c2a18 3161 return true;
db1266c8 3162
b72c1f65 3163 pdn = pci_get_pdn(dev);
184cd4a3 3164 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
c88c2a18 3165 return false;
db1266c8 3166
c88c2a18 3167 return true;
184cd4a3
BH		 3168}
3169
3170static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
3171 u32 devfn)
3172{
3173 return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
3174}
3175
7a8e6bbf 3176static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
73ed148a 3177{
7a8e6bbf
MN		 3178 struct pnv_phb *phb = hose->private_data;
3179
d1a85eee 3180 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
73ed148a
BH		 3181 OPAL_ASSERT_RESET);
3182}
3183
92ae0353
DA		 3184static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3185 .dma_dev_setup = pnv_pci_dma_dev_setup,
3186#ifdef CONFIG_PCI_MSI
3187 .setup_msi_irqs = pnv_setup_msi_irqs,
3188 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3189#endif
3190 .enable_device_hook = pnv_pci_enable_device_hook,
3191 .window_alignment = pnv_pci_window_alignment,
3192 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
763d2d8d 3193 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
53522982 3194 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
7a8e6bbf 3195 .shutdown = pnv_pci_ioda_shutdown,
92ae0353
DA		 3196};
3197
5d2aa710
AP		 3198static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3199 .dma_dev_setup = pnv_pci_dma_dev_setup,
3200#ifdef CONFIG_PCI_MSI
3201 .setup_msi_irqs = pnv_setup_msi_irqs,
3202 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3203#endif
3204 .enable_device_hook = pnv_pci_enable_device_hook,
3205 .window_alignment = pnv_pci_window_alignment,
3206 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3207 .dma_set_mask = pnv_npu_dma_set_mask,
3208 .shutdown = pnv_pci_ioda_shutdown,
3209};
3210
e51df2c1
AB		 3211static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3212 u64 hub_id, int ioda_type)
184cd4a3
BH		 3213{
3214 struct pci_controller *hose;
184cd4a3 3215 struct pnv_phb *phb;
8184616f 3216 unsigned long size, m32map_off, pemap_off, iomap_off = 0;
c681b93c 3217 const __be64 *prop64;
3a1a4661 3218 const __be32 *prop32;
f1b7cc3e 3219 int len;
184cd4a3
BH		 3220 u64 phb_id;
3221 void *aux;
3222 long rc;
3223
58d714ec 3224 pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
184cd4a3
BH		 3225
3226 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3227 if (!prop64) {
3228 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3229 return;
3230 }
3231 phb_id = be64_to_cpup(prop64);
3232 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3233
e39f223f 3234 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
58d714ec
GS		 3235
3236 /* Allocate PCI controller */
58d714ec
GS		 3237 phb->hose = hose = pcibios_alloc_controller(np);
3238 if (!phb->hose) {
3239 pr_err(" Can't allocate PCI controller for %s\n",
184cd4a3 3240 np->full_name);
e39f223f 3241 memblock_free(__pa(phb), sizeof(struct pnv_phb));
184cd4a3
BH		 3242 return;
3243 }
3244
3245 spin_lock_init(&phb->lock);
f1b7cc3e
GS		 3246 prop32 = of_get_property(np, "bus-range", &len);
3247 if (prop32 && len == 8) {
3a1a4661
BH		 3248 hose->first_busno = be32_to_cpu(prop32[0]);
3249 hose->last_busno = be32_to_cpu(prop32[1]);
f1b7cc3e
GS		 3250 } else {
3251 pr_warn(" Broken <bus-range> on %s\n", np->full_name);
3252 hose->first_busno = 0;
3253 hose->last_busno = 0xff;
3254 }
184cd4a3 3255 hose->private_data = phb;
e9cc17d4 3256 phb->hub_id = hub_id;
184cd4a3 3257 phb->opal_id = phb_id;
aa0c033f 3258 phb->type = ioda_type;
781a868f 3259 mutex_init(&phb->ioda.pe_alloc_mutex);
184cd4a3 3260
cee72d5b
BH		 3261 /* Detect specific models for error handling */
3262 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3263 phb->model = PNV_PHB_MODEL_P7IOC;
f3d40c25 3264 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
aa0c033f 3265 phb->model = PNV_PHB_MODEL_PHB3;
5d2aa710
AP		 3266 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3267 phb->model = PNV_PHB_MODEL_NPU;
cee72d5b
BH		 3268 else
3269 phb->model = PNV_PHB_MODEL_UNKNOWN;
3270
aa0c033f 3271 /* Parse 32-bit and IO ranges (if any) */
2f1ec02e 3272 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
184cd4a3 3273
aa0c033f 3274 /* Get registers */
184cd4a3
BH		 3275 phb->regs = of_iomap(np, 0);
3276 if (phb->regs == NULL)
3277 pr_err(" Failed to map registers !\n");
3278
184cd4a3 3279 /* Initialize more IODA stuff */
36954dc7 3280 phb->ioda.total_pe = 1;
aa0c033f 3281 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
36954dc7 3282 if (prop32)
3a1a4661 3283 phb->ioda.total_pe = be32_to_cpup(prop32);
36954dc7
GS		 3284 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3285 if (prop32)
3286 phb->ioda.reserved_pe = be32_to_cpup(prop32);
262af557
GC		 3287
3288 /* Parse 64-bit MMIO range */
3289 pnv_ioda_parse_m64_window(phb);
3290
184cd4a3 3291 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
aa0c033f 3292 /* FW Has already off top 64k of M32 space (MSI space) */
184cd4a3
BH		 3293 phb->ioda.m32_size += 0x10000;
3294
3295 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
3fd47f06 3296 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
184cd4a3
BH		 3297 phb->ioda.io_size = hose->pci_io_size;
3298 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
3299 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3300
c35d2a8c 3301 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
184cd4a3
BH		 3302 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
3303 m32map_off = size;
e47747f4 3304 size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
c35d2a8c
GS		 3305 if (phb->type == PNV_PHB_IODA1) {
3306 iomap_off = size;
3307 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
3308 }
184cd4a3
BH		 3309 pemap_off = size;
3310 size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
e39f223f 3311 aux = memblock_virt_alloc(size, 0);
184cd4a3
BH		 3312 phb->ioda.pe_alloc = aux;
3313 phb->ioda.m32_segmap = aux + m32map_off;
c35d2a8c
GS		 3314 if (phb->type == PNV_PHB_IODA1)
3315 phb->ioda.io_segmap = aux + iomap_off;
184cd4a3 3316 phb->ioda.pe_array = aux + pemap_off;
36954dc7 3317 set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc);
184cd4a3 3318
7ebdf956 3319 INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
184cd4a3 3320 INIT_LIST_HEAD(&phb->ioda.pe_list);
781a868f 3321 mutex_init(&phb->ioda.pe_list_mutex);
184cd4a3
BH		 3322
3323 /* Calculate how many 32-bit TCE segments we have */
3324 phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
3325
aa0c033f 3326#if 0 /* We should really do that ... */
184cd4a3
BH		 3327 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3328 window_type,
3329 window_num,
3330 starting_real_address,
3331 starting_pci_address,
3332 segment_size);
3333#endif
3334
262af557
GC		 3335 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3336 phb->ioda.total_pe, phb->ioda.reserved_pe,
3337 phb->ioda.m32_size, phb->ioda.m32_segsize);
3338 if (phb->ioda.m64_size)
3339 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3340 phb->ioda.m64_size, phb->ioda.m64_segsize);
3341 if (phb->ioda.io_size)
3342 pr_info(" IO: 0x%x [segment=0x%x]\n",
3343 phb->ioda.io_size, phb->ioda.io_segsize);
3344
184cd4a3 3345
184cd4a3 3346 phb->hose->ops = &pnv_pci_ops;
49dec922
GS		 3347 phb->get_pe_state = pnv_ioda_get_pe_state;
3348 phb->freeze_pe = pnv_ioda_freeze_pe;
3349 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
184cd4a3
BH		 3350
3351 /* Setup RID -> PE mapping function */
3352 phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
3353
3354 /* Setup TCEs */
3355 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3356
3357 /* Setup MSI support */
3358 pnv_pci_init_ioda_msis(phb);
3359
c40a4210
GS		 3360 /*
3361 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3362 * to let the PCI core do resource assignment. It's supposed
3363 * that the PCI core will do correct I/O and MMIO alignment
3364 * for the P2P bridge bars so that each PCI bus (excluding
3365 * the child P2P bridges) can form individual PE.
184cd4a3 3366 */
fb446ad0 3367 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
5d2aa710
AP		 3368
3369 if (phb->type == PNV_PHB_NPU)
3370 hose->controller_ops = pnv_npu_ioda_controller_ops;
3371 else
3372 hose->controller_ops = pnv_pci_ioda_controller_ops;
ad30cb99 3373
6e628c7d
WY		 3374#ifdef CONFIG_PCI_IOV
3375 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
5350ab3f 3376 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
ad30cb99
ME		 3377#endif
3378
c40a4210 3379 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
184cd4a3
BH		 3380
3381 /* Reset IODA tables to a clean state */
d1a85eee 3382 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
184cd4a3 3383 if (rc)
f11fe552 3384 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
361f2a2a
GS		 3385
3386 /* If we're running in kdump kerenl, the previous kerenl never
3387 * shutdown PCI devices correctly. We already got IODA table
3388 * cleaned out. So we have to issue PHB reset to stop all PCI
3389 * transactions from previous kerenl.
3390 */
3391 if (is_kdump_kernel()) {
3392 pr_info(" Issue PHB reset ...\n");
cadf364d
GS		 3393 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3394 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
361f2a2a 3395 }
262af557 3396
9e9e8935
GS		 3397 /* Remove M64 resource if we can't configure it successfully */
3398 if (!phb->init_m64 || phb->init_m64(phb))
262af557 3399 hose->mem_resources[1].flags = 0;
aa0c033f
GS		 3400}
3401
67975005 3402void __init pnv_pci_init_ioda2_phb(struct device_node *np)
aa0c033f 3403{
e9cc17d4 3404 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
184cd4a3
BH		 3405}
3406
5d2aa710
AP		 3407void __init pnv_pci_init_npu_phb(struct device_node *np)
3408{
3409 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3410}
3411
184cd4a3
BH		 3412void __init pnv_pci_init_ioda_hub(struct device_node *np)
3413{
3414 struct device_node *phbn;
c681b93c 3415 const __be64 *prop64;
184cd4a3
BH		 3416 u64 hub_id;
3417
3418 pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3419
3420 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3421 if (!prop64) {
3422 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3423 return;
3424 }
3425 hub_id = be64_to_cpup(prop64);
3426 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3427
3428 /* Count child PHBs */
3429 for_each_child_of_node(np, phbn) {
3430 /* Look for IODA1 PHBs */
3431 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
e9cc17d4 3432 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
184cd4a3
BH		 3433 }
3434}
Linux kernel - Deliverables
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