[deliverable/linux.git] / arch / powerpc / platforms / powernv / pci.h

#ifndef __POWERNV_PCI_H
#define __POWERNV_PCI_H

struct pci_dn;

enum pnv_phb_type {
	PNV_PHB_IODA1	= 0,
	PNV_PHB_IODA2	= 1,
	PNV_PHB_NPU	= 2,
};

/* Precise PHB model for error management */
enum pnv_phb_model {
	PNV_PHB_MODEL_UNKNOWN,
	PNV_PHB_MODEL_P7IOC,
	PNV_PHB_MODEL_PHB3,
	PNV_PHB_MODEL_NPU,
};

#define PNV_PCI_DIAG_BUF_SIZE	8192
#define PNV_IODA_PE_DEV		(1 << 0)	/* PE has single PCI device	*/
#define PNV_IODA_PE_BUS		(1 << 1)	/* PE has primary PCI bus	*/
#define PNV_IODA_PE_BUS_ALL	(1 << 2)	/* PE has subordinate buses	*/
#define PNV_IODA_PE_MASTER	(1 << 3)	/* Master PE in compound case	*/
#define PNV_IODA_PE_SLAVE	(1 << 4)	/* Slave PE in compound case	*/
#define PNV_IODA_PE_VF		(1 << 5)	/* PE for one VF 		*/

/* Data associated with a PE, including IOMMU tracking etc.. */
struct pnv_phb;
struct pnv_ioda_pe {
	unsigned long		flags;
	struct pnv_phb		*phb;

	/* A PE can be associated with a single device or an
	 * entire bus (& children). In the former case, pdev
	 * is populated, in the later case, pbus is.
	 */
#ifdef CONFIG_PCI_IOV
	struct pci_dev          *parent_dev;
#endif
	struct pci_dev		*pdev;
	struct pci_bus		*pbus;

	/* Effective RID (device RID for a device PE and base bus
	 * RID with devfn 0 for a bus PE)
	 */
	unsigned int		rid;

	/* PE number */
	unsigned int		pe_number;

	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
	struct iommu_table_group table_group;

	/* 64-bit TCE bypass region */
	bool			tce_bypass_enabled;
	uint64_t		tce_bypass_base;

	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	 * and -1 if not supported. (It's actually identical to the
	 * PE number)
	 */
	int			mve_number;

	/* PEs in compound case */
	struct pnv_ioda_pe	*master;
	struct list_head	slaves;

	/* Link in list of PE#s */
	struct list_head	list;
};

#define PNV_PHB_FLAG_EEH	(1 << 0)

struct pnv_phb {
	struct pci_controller	*hose;
	enum pnv_phb_type	type;
	enum pnv_phb_model	model;
	u64			hub_id;
	u64			opal_id;
	int			flags;
	void __iomem		*regs;
	int			initialized;
	spinlock_t		lock;

#ifdef CONFIG_DEBUG_FS
	int			has_dbgfs;
	struct dentry		*dbgfs;
#endif

#ifdef CONFIG_PCI_MSI
	unsigned int		msi_base;
	unsigned int		msi32_support;
	struct msi_bitmap	msi_bmp;
#endif
	int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
			 unsigned int hwirq, unsigned int virq,
			 unsigned int is_64, struct msi_msg *msg);
	void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
	void (*fixup_phb)(struct pci_controller *hose);
	int (*init_m64)(struct pnv_phb *phb);
	void (*reserve_m64_pe)(struct pci_bus *bus,
			       unsigned long *pe_bitmap, bool all);
	struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
	int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
	void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
	int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);

	struct {
		/* Global bridge info */
		unsigned int		total_pe_num;
		unsigned int		reserved_pe_idx;

		/* 32-bit MMIO window */
		unsigned int		m32_size;
		unsigned int		m32_segsize;
		unsigned int		m32_pci_base;

		/* 64-bit MMIO window */
		unsigned int		m64_bar_idx;
		unsigned long		m64_size;
		unsigned long		m64_segsize;
		unsigned long		m64_base;
		unsigned long		m64_bar_alloc;

		/* IO ports */
		unsigned int		io_size;
		unsigned int		io_segsize;
		unsigned int		io_pci_base;

		/* PE allocation */
		struct mutex		pe_alloc_mutex;
		unsigned long		*pe_alloc;
		struct pnv_ioda_pe	*pe_array;

		/* M32 & IO segment maps */
		unsigned int		*m64_segmap;
		unsigned int		*m32_segmap;
		unsigned int		*io_segmap;

		/* DMA32 segment maps - IODA1 only */
		unsigned int		dma32_count;
		unsigned int		*dma32_segmap;

		/* IRQ chip */
		int			irq_chip_init;
		struct irq_chip		irq_chip;

		/* Sorted list of used PE's based
		 * on the sequence of creation
		 */
		struct list_head	pe_list;
		struct mutex            pe_list_mutex;

		/* Reverse map of PEs, will have to extend if
		 * we are to support more than 256 PEs, indexed
		 * bus { bus, devfn }
		 */
		unsigned char		pe_rmap[0x10000];

		/* TCE cache invalidate registers (physical and
		 * remapped)
		 */
		phys_addr_t		tce_inval_reg_phys;
		__be64 __iomem		*tce_inval_reg;
	} ioda;

	/* PHB and hub status structure */
	union {
		unsigned char			blob[PNV_PCI_DIAG_BUF_SIZE];
		struct OpalIoP7IOCPhbErrorData	p7ioc;
		struct OpalIoPhb3ErrorData	phb3;
		struct OpalIoP7IOCErrorData 	hub_diag;
	} diag;

};

extern struct pci_ops pnv_pci_ops;
extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
		unsigned long uaddr, enum dma_data_direction direction,
		struct dma_attrs *attrs);
extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
		unsigned long *hpa, enum dma_data_direction *direction);
extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);

void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
				unsigned char *log_buff);
int pnv_pci_cfg_read(struct pci_dn *pdn,
		     int where, int size, u32 *val);
int pnv_pci_cfg_write(struct pci_dn *pdn,
		      int where, int size, u32 val);
extern struct iommu_table *pnv_pci_table_alloc(int nid);

extern long pnv_pci_link_table_and_group(int node, int num,
		struct iommu_table *tbl,
		struct iommu_table_group *table_group);
extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
		struct iommu_table_group *table_group);
extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
				      void *tce_mem, u64 tce_size,
				      u64 dma_offset, unsigned page_shift);
extern void pnv_pci_init_ioda_hub(struct device_node *np);
extern void pnv_pci_init_ioda2_phb(struct device_node *np);
extern void pnv_pci_init_npu_phb(struct device_node *np);
extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
					__be64 *startp, __be64 *endp, bool rm);
extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);

extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);

extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
			    const char *fmt, ...);
#define pe_err(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
#define pe_warn(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
#define pe_info(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)

/* Nvlink functions */
extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
		struct iommu_table *tbl);
extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);

#endif /* __POWERNV_PCI_H */
Commit	Line	Data
61305a96 BH	1	#ifndef __POWERNV_PCI_H
	2	#define __POWERNV_PCI_H
	3
	4	struct pci_dn;
	5
	6	enum pnv_phb_type {
2de50e96 RC	7	PNV_PHB_IODA1 = 0,
	8	PNV_PHB_IODA2 = 1,
	9	PNV_PHB_NPU = 2,
61305a96 BH	10	};
61305a96 BH	11
cee72d5b BH	12	/* Precise PHB model for error management */
	13	enum pnv_phb_model {
	14	PNV_PHB_MODEL_UNKNOWN,
cee72d5b	15	PNV_PHB_MODEL_P7IOC,
aa0c033f	16	PNV_PHB_MODEL_PHB3,
5d2aa710	17	PNV_PHB_MODEL_NPU,
cee72d5b BH	18	};
cee72d5b BH	19
5c9d6d75	20	#define PNV_PCI_DIAG_BUF_SIZE 8192
7ebdf956 GS	21	#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
	22	#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
	23	#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
262af557 GC	24	#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
262af557 GC	25	#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
781a868f	26	#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
cee72d5b	27
184cd4a3	28	/* Data associated with a PE, including IOMMU tracking etc.. */
4cce9550	29	struct pnv_phb;
184cd4a3	30	struct pnv_ioda_pe {
7ebdf956	31	unsigned long flags;
4cce9550	32	struct pnv_phb *phb;
7ebdf956	33
184cd4a3 BH	34	/* A PE can be associated with a single device or an
	35	* entire bus (& children). In the former case, pdev
	36	* is populated, in the later case, pbus is.
	37	*/
781a868f WY	38	#ifdef CONFIG_PCI_IOV
	39	struct pci_dev *parent_dev;
	40	#endif
184cd4a3 BH	41	struct pci_dev *pdev;
	42	struct pci_bus *pbus;
	43
	44	/* Effective RID (device RID for a device PE and base bus
	45	* RID with devfn 0 for a bus PE)
	46	*/
	47	unsigned int rid;
	48
	49	/* PE number */
	50	unsigned int pe_number;
	51
184cd4a3	52	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
b348aa65	53	struct iommu_table_group table_group;
184cd4a3	54
cd15b048 BH	55	/* 64-bit TCE bypass region */
	56	bool tce_bypass_enabled;
	57	uint64_t tce_bypass_base;
184cd4a3 BH	58
	59	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	60	* and -1 if not supported. (It's actually identical to the
	61	* PE number)
	62	*/
	63	int mve_number;
	64
262af557 GC	65	/* PEs in compound case */
	66	struct pnv_ioda_pe *master;
	67	struct list_head slaves;
	68
184cd4a3	69	/* Link in list of PE#s */
7ebdf956	70	struct list_head list;
184cd4a3 BH	71	};
184cd4a3 BH	72
f5bc6b70 GS	73	#define PNV_PHB_FLAG_EEH (1 << 0)
f5bc6b70 GS	74
61305a96 BH	75	struct pnv_phb {
	76	struct pci_controller *hose;
	77	enum pnv_phb_type type;
cee72d5b	78	enum pnv_phb_model model;
8747f363	79	u64 hub_id;
61305a96	80	u64 opal_id;
f5bc6b70	81	int flags;
61305a96	82	void __iomem *regs;
db1266c8	83	int initialized;
61305a96 BH	84	spinlock_t lock;
61305a96 BH	85
37c367f2	86	#ifdef CONFIG_DEBUG_FS
7f52a526	87	int has_dbgfs;
37c367f2 GS	88	struct dentry *dbgfs;
	89	#endif
	90
c1a2562a	91	#ifdef CONFIG_PCI_MSI
c1a2562a	92	unsigned int msi_base;
c1a2562a	93	unsigned int msi32_support;
fb1b55d6	94	struct msi_bitmap msi_bmp;
c1a2562a BH	95	#endif
c1a2562a BH	96	int (msi_setup)(struct pnv_phb phb, struct pci_dev *dev,
137436c9 GS	97	unsigned int hwirq, unsigned int virq,
137436c9 GS	98	unsigned int is_64, struct msi_msg *msg);
61305a96 BH	99	void (dma_dev_setup)(struct pnv_phb phb, struct pci_dev *pdev);
61305a96 BH	100	void (fixup_phb)(struct pci_controller hose);
262af557	101	int (init_m64)(struct pnv_phb phb);
96a2f92b GS	102	void (reserve_m64_pe)(struct pci_bus bus,
96a2f92b GS	103	unsigned long *pe_bitmap, bool all);
1e916772	104	struct pnv_ioda_pe (pick_m64_pe)(struct pci_bus *bus, bool all);
49dec922 GS	105	int (get_pe_state)(struct pnv_phb phb, int pe_no);
	106	void (freeze_pe)(struct pnv_phb phb, int pe_no);
	107	int (unfreeze_pe)(struct pnv_phb phb, int pe_no, int opt);
61305a96	108
2de50e96 RC	109	struct {
2de50e96 RC	110	/* Global bridge info */
92b8f137 GS	111	unsigned int total_pe_num;
92b8f137 GS	112	unsigned int reserved_pe_idx;
2de50e96 RC	113
	114	/* 32-bit MMIO window */
	115	unsigned int m32_size;
	116	unsigned int m32_segsize;
	117	unsigned int m32_pci_base;
	118
	119	/* 64-bit MMIO window */
	120	unsigned int m64_bar_idx;
	121	unsigned long m64_size;
	122	unsigned long m64_segsize;
	123	unsigned long m64_base;
	124	unsigned long m64_bar_alloc;
	125
	126	/* IO ports */
	127	unsigned int io_size;
	128	unsigned int io_segsize;
	129	unsigned int io_pci_base;
	130
13ce7598	131	/* PE allocation */
2de50e96	132	struct mutex pe_alloc_mutex;
13ce7598 GS	133	unsigned long *pe_alloc;
13ce7598 GS	134	struct pnv_ioda_pe *pe_array;
2de50e96 RC	135
2de50e96 RC	136	/* M32 & IO segment maps */
93289d8c	137	unsigned int *m64_segmap;
2de50e96 RC	138	unsigned int *m32_segmap;
2de50e96 RC	139	unsigned int *io_segmap;
2de50e96	140
2b923ed1 GS	141	/* DMA32 segment maps - IODA1 only */
	142	unsigned int dma32_count;
	143	unsigned int *dma32_segmap;
	144
2de50e96 RC	145	/* IRQ chip */
	146	int irq_chip_init;
	147	struct irq_chip irq_chip;
	148
	149	/* Sorted list of used PE's based
	150	* on the sequence of creation
	151	*/
	152	struct list_head pe_list;
	153	struct mutex pe_list_mutex;
	154
	155	/* Reverse map of PEs, will have to extend if
	156	* we are to support more than 256 PEs, indexed
	157	* bus { bus, devfn }
	158	*/
	159	unsigned char pe_rmap[0x10000];
	160
2de50e96 RC	161	/* TCE cache invalidate registers (physical and
	162	* remapped)
	163	*/
	164	phys_addr_t tce_inval_reg_phys;
	165	__be64 __iomem *tce_inval_reg;
	166	} ioda;
cee72d5b	167
ca1de5de	168	/* PHB and hub status structure */
cee72d5b BH	169	union {
	170	unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
	171	struct OpalIoP7IOCPhbErrorData p7ioc;
93aef2a7	172	struct OpalIoPhb3ErrorData phb3;
ca1de5de	173	struct OpalIoP7IOCErrorData hub_diag;
cee72d5b	174	} diag;
ca1de5de	175
61305a96 BH	176	};
	177
	178	extern struct pci_ops pnv_pci_ops;
da004c36 AK	179	extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
	180	unsigned long uaddr, enum dma_data_direction direction,
	181	struct dma_attrs *attrs);
	182	extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
05c6cfb9 AK	183	extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
05c6cfb9 AK	184	unsigned long hpa, enum dma_data_direction direction);
da004c36	185	extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
61305a96	186
93aef2a7 GS	187	void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
93aef2a7 GS	188	unsigned char *log_buff);
3532a741	189	int pnv_pci_cfg_read(struct pci_dn *pdn,
9bf41be6	190	int where, int size, u32 *val);
3532a741	191	int pnv_pci_cfg_write(struct pci_dn *pdn,
9bf41be6	192	int where, int size, u32 val);
0eaf4def AK	193	extern struct iommu_table *pnv_pci_table_alloc(int nid);
	194
	195	extern long pnv_pci_link_table_and_group(int node, int num,
	196	struct iommu_table *tbl,
	197	struct iommu_table_group *table_group);
	198	extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
	199	struct iommu_table_group *table_group);
61305a96 BH	200	extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
61305a96 BH	201	void *tce_mem, u64 tce_size,
8fa5d454	202	u64 dma_offset, unsigned page_shift);
184cd4a3	203	extern void pnv_pci_init_ioda_hub(struct device_node *np);
aa0c033f	204	extern void pnv_pci_init_ioda2_phb(struct device_node *np);
5d2aa710	205	extern void pnv_pci_init_npu_phb(struct device_node *np);
4cce9550	206	extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
3ad26e5c	207	__be64 startp, __be64 endp, bool rm);
d92a208d	208	extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
cadf364d	209	extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
73ed148a	210
92ae0353	211	extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
1bc74f1c	212	extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
92ae0353 DA	213	extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
	214	extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
	215
7d623e42 AK	216	extern void pe_level_printk(const struct pnv_ioda_pe pe, const char level,
	217	const char *fmt, ...);
	218	#define pe_err(pe, fmt, ...) \
	219	pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
	220	#define pe_warn(pe, fmt, ...) \
	221	pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
	222	#define pe_info(pe, fmt, ...) \
	223	pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
	224
5d2aa710	225	/* Nvlink functions */
f9f83456	226	extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
0bbcdb43	227	extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
b5cb9ab1 AK	228	extern struct pnv_ioda_pe pnv_pci_npu_setup_iommu(struct pnv_ioda_pe npe);
	229	extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
	230	struct iommu_table *tbl);
	231	extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
	232	extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
	233	extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
5d2aa710	234
61305a96	235	#endif /* __POWERNV_PCI_H */