[deliverable/linux.git] / arch / powerpc / platforms / powernv / pci.h

#ifndef __POWERNV_PCI_H
#define __POWERNV_PCI_H

struct pci_dn;

enum pnv_phb_type {
	PNV_PHB_P5IOC2	= 0,
	PNV_PHB_IODA1	= 1,
	PNV_PHB_IODA2	= 2,
};

/* Precise PHB model for error management */
enum pnv_phb_model {
	PNV_PHB_MODEL_UNKNOWN,
	PNV_PHB_MODEL_P5IOC2,
	PNV_PHB_MODEL_P7IOC,
	PNV_PHB_MODEL_PHB3,
};

#define PNV_PCI_DIAG_BUF_SIZE	8192
#define PNV_IODA_PE_DEV		(1 << 0)	/* PE has single PCI device	*/
#define PNV_IODA_PE_BUS		(1 << 1)	/* PE has primary PCI bus	*/
#define PNV_IODA_PE_BUS_ALL	(1 << 2)	/* PE has subordinate buses	*/

/* Data associated with a PE, including IOMMU tracking etc.. */
struct pnv_phb;
struct pnv_ioda_pe {
	unsigned long		flags;
	struct pnv_phb		*phb;

	/* A PE can be associated with a single device or an
	 * entire bus (& children). In the former case, pdev
	 * is populated, in the later case, pbus is.
	 */
	struct pci_dev		*pdev;
	struct pci_bus		*pbus;

	/* Effective RID (device RID for a device PE and base bus
	 * RID with devfn 0 for a bus PE)
	 */
	unsigned int		rid;

	/* PE number */
	unsigned int		pe_number;

	/* "Weight" assigned to the PE for the sake of DMA resource
	 * allocations
	 */
	unsigned int		dma_weight;

	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
	int			tce32_seg;
	int			tce32_segcount;
	struct iommu_table	tce32_table;
	phys_addr_t		tce_inval_reg_phys;

	/* 64-bit TCE bypass region */
	bool			tce_bypass_enabled;
	uint64_t		tce_bypass_base;

	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	 * and -1 if not supported. (It's actually identical to the
	 * PE number)
	 */
	int			mve_number;

	/* Link in list of PE#s */
	struct list_head	dma_link;
	struct list_head	list;
};

/* IOC dependent EEH operations */
#ifdef CONFIG_EEH
struct pnv_eeh_ops {
	int (*post_init)(struct pci_controller *hose);
	int (*set_option)(struct eeh_pe *pe, int option);
	int (*get_state)(struct eeh_pe *pe);
	int (*reset)(struct eeh_pe *pe, int option);
	int (*get_log)(struct eeh_pe *pe, int severity,
		       char *drv_log, unsigned long len);
	int (*configure_bridge)(struct eeh_pe *pe);
	int (*next_error)(struct eeh_pe **pe);
};

#define PNV_EEH_STATE_ENABLED	(1 << 0)	/* EEH enabled	*/
#define PNV_EEH_STATE_REMOVED	(1 << 1)	/* PHB removed	*/

#endif /* CONFIG_EEH */

struct pnv_phb {
	struct pci_controller	*hose;
	enum pnv_phb_type	type;
	enum pnv_phb_model	model;
	u64			hub_id;
	u64			opal_id;
	void __iomem		*regs;
	int			initialized;
	spinlock_t		lock;

#ifdef CONFIG_EEH
	struct pnv_eeh_ops	*eeh_ops;
	int			eeh_state;
#endif

#ifdef CONFIG_DEBUG_FS
	struct dentry		*dbgfs;
#endif

#ifdef CONFIG_PCI_MSI
	unsigned int		msi_base;
	unsigned int		msi32_support;
	struct msi_bitmap	msi_bmp;
#endif
	int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
			 unsigned int hwirq, unsigned int virq,
			 unsigned int is_64, struct msi_msg *msg);
	void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
	int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev,
			    u64 dma_mask);
	void (*fixup_phb)(struct pci_controller *hose);
	u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
	void (*shutdown)(struct pnv_phb *phb);

	union {
		struct {
			struct iommu_table iommu_table;
		} p5ioc2;

		struct {
			/* Global bridge info */
			unsigned int		total_pe;
			unsigned int		reserved_pe;
			unsigned int		m32_size;
			unsigned int		m32_segsize;
			unsigned int		m32_pci_base;
			unsigned int		io_size;
			unsigned int		io_segsize;
			unsigned int		io_pci_base;

			/* PE allocation bitmap */
			unsigned long		*pe_alloc;

			/* M32 & IO segment maps */
			unsigned int		*m32_segmap;
			unsigned int		*io_segmap;
			struct pnv_ioda_pe	*pe_array;

			/* IRQ chip */
			int			irq_chip_init;
			struct irq_chip		irq_chip;

			/* Sorted list of used PE's based
			 * on the sequence of creation
			 */
			struct list_head	pe_list;

			/* Reverse map of PEs, will have to extend if
			 * we are to support more than 256 PEs, indexed
			 * bus { bus, devfn }
			 */
			unsigned char		pe_rmap[0x10000];

			/* 32-bit TCE tables allocation */
			unsigned long		tce32_count;

			/* Total "weight" for the sake of DMA resources
			 * allocation
			 */
			unsigned int		dma_weight;
			unsigned int		dma_pe_count;

			/* Sorted list of used PE's, sorted at
			 * boot for resource allocation purposes
			 */
			struct list_head	pe_dma_list;
		} ioda;
	};

	/* PHB and hub status structure */
	union {
		unsigned char			blob[PNV_PCI_DIAG_BUF_SIZE];
		struct OpalIoP7IOCPhbErrorData	p7ioc;
		struct OpalIoPhb3ErrorData	phb3;
		struct OpalIoP7IOCErrorData 	hub_diag;
	} diag;

};

extern struct pci_ops pnv_pci_ops;
#ifdef CONFIG_EEH
extern struct pnv_eeh_ops ioda_eeh_ops;
#endif

void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
				unsigned char *log_buff);
int pnv_pci_cfg_read(struct device_node *dn,
		     int where, int size, u32 *val);
int pnv_pci_cfg_write(struct device_node *dn,
		      int where, int size, u32 val);
extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
				      void *tce_mem, u64 tce_size,
				      u64 dma_offset);
extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
extern void pnv_pci_init_ioda_hub(struct device_node *np);
extern void pnv_pci_init_ioda2_phb(struct device_node *np);
extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
					__be64 *startp, __be64 *endp, bool rm);

#endif /* __POWERNV_PCI_H */
Commit	Line	Data
61305a96 BH	1	#ifndef __POWERNV_PCI_H
	2	#define __POWERNV_PCI_H
	3
	4	struct pci_dn;
	5
	6	enum pnv_phb_type {
aa0c033f GS	7	PNV_PHB_P5IOC2 = 0,
	8	PNV_PHB_IODA1 = 1,
	9	PNV_PHB_IODA2 = 2,
61305a96 BH	10	};
61305a96 BH	11
cee72d5b BH	12	/* Precise PHB model for error management */
	13	enum pnv_phb_model {
	14	PNV_PHB_MODEL_UNKNOWN,
	15	PNV_PHB_MODEL_P5IOC2,
	16	PNV_PHB_MODEL_P7IOC,
aa0c033f	17	PNV_PHB_MODEL_PHB3,
cee72d5b BH	18	};
cee72d5b BH	19
5c9d6d75	20	#define PNV_PCI_DIAG_BUF_SIZE 8192
7ebdf956 GS	21	#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
	22	#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
	23	#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
cee72d5b	24
184cd4a3	25	/* Data associated with a PE, including IOMMU tracking etc.. */
4cce9550	26	struct pnv_phb;
184cd4a3	27	struct pnv_ioda_pe {
7ebdf956	28	unsigned long flags;
4cce9550	29	struct pnv_phb *phb;
7ebdf956	30
184cd4a3 BH	31	/* A PE can be associated with a single device or an
	32	* entire bus (& children). In the former case, pdev
	33	* is populated, in the later case, pbus is.
	34	*/
	35	struct pci_dev *pdev;
	36	struct pci_bus *pbus;
	37
	38	/* Effective RID (device RID for a device PE and base bus
	39	* RID with devfn 0 for a bus PE)
	40	*/
	41	unsigned int rid;
	42
	43	/* PE number */
	44	unsigned int pe_number;
	45
	46	/* "Weight" assigned to the PE for the sake of DMA resource
	47	* allocations
	48	*/
	49	unsigned int dma_weight;
	50
184cd4a3 BH	51	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
	52	int tce32_seg;
	53	int tce32_segcount;
	54	struct iommu_table tce32_table;
8e0a1611	55	phys_addr_t tce_inval_reg_phys;
184cd4a3	56
cd15b048 BH	57	/* 64-bit TCE bypass region */
	58	bool tce_bypass_enabled;
	59	uint64_t tce_bypass_base;
184cd4a3 BH	60
	61	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	62	* and -1 if not supported. (It's actually identical to the
	63	* PE number)
	64	*/
	65	int mve_number;
	66
	67	/* Link in list of PE#s */
7ebdf956 GS	68	struct list_head dma_link;
7ebdf956 GS	69	struct list_head list;
184cd4a3 BH	70	};
184cd4a3 BH	71
8747f363 GS	72	/* IOC dependent EEH operations */
	73	#ifdef CONFIG_EEH
	74	struct pnv_eeh_ops {
	75	int (post_init)(struct pci_controller hose);
	76	int (set_option)(struct eeh_pe pe, int option);
	77	int (get_state)(struct eeh_pe pe);
	78	int (reset)(struct eeh_pe pe, int option);
	79	int (get_log)(struct eeh_pe pe, int severity,
	80	char *drv_log, unsigned long len);
	81	int (configure_bridge)(struct eeh_pe pe);
	82	int (next_error)(struct eeh_pe *pe);
	83	};
0b9e267d GS	84
	85	#define PNV_EEH_STATE_ENABLED (1 << 0) /* EEH enabled */
	86	#define PNV_EEH_STATE_REMOVED (1 << 1) /* PHB removed */
	87
8747f363 GS	88	#endif /* CONFIG_EEH */
8747f363 GS	89
61305a96 BH	90	struct pnv_phb {
	91	struct pci_controller *hose;
	92	enum pnv_phb_type type;
cee72d5b	93	enum pnv_phb_model model;
8747f363	94	u64 hub_id;
61305a96 BH	95	u64 opal_id;
61305a96 BH	96	void __iomem *regs;
db1266c8	97	int initialized;
61305a96 BH	98	spinlock_t lock;
61305a96 BH	99
8747f363 GS	100	#ifdef CONFIG_EEH
8747f363 GS	101	struct pnv_eeh_ops *eeh_ops;
0b9e267d	102	int eeh_state;
8747f363 GS	103	#endif
8747f363 GS	104
37c367f2 GS	105	#ifdef CONFIG_DEBUG_FS
	106	struct dentry *dbgfs;
	107	#endif
	108
c1a2562a	109	#ifdef CONFIG_PCI_MSI
c1a2562a	110	unsigned int msi_base;
c1a2562a	111	unsigned int msi32_support;
fb1b55d6	112	struct msi_bitmap msi_bmp;
c1a2562a BH	113	#endif
c1a2562a BH	114	int (msi_setup)(struct pnv_phb phb, struct pci_dev *dev,
137436c9 GS	115	unsigned int hwirq, unsigned int virq,
137436c9 GS	116	unsigned int is_64, struct msi_msg *msg);
61305a96	117	void (dma_dev_setup)(struct pnv_phb phb, struct pci_dev *pdev);
cd15b048 BH	118	int (dma_set_mask)(struct pnv_phb phb, struct pci_dev *pdev,
cd15b048 BH	119	u64 dma_mask);
61305a96 BH	120	void (fixup_phb)(struct pci_controller hose);
61305a96 BH	121	u32 (bdfn_to_pe)(struct pnv_phb phb, struct pci_bus *bus, u32 devfn);
73ed148a	122	void (shutdown)(struct pnv_phb phb);
61305a96 BH	123
	124	union {
	125	struct {
	126	struct iommu_table iommu_table;
	127	} p5ioc2;
184cd4a3 BH	128
	129	struct {
	130	/* Global bridge info */
	131	unsigned int total_pe;
36954dc7	132	unsigned int reserved_pe;
184cd4a3 BH	133	unsigned int m32_size;
	134	unsigned int m32_segsize;
	135	unsigned int m32_pci_base;
	136	unsigned int io_size;
	137	unsigned int io_segsize;
	138	unsigned int io_pci_base;
	139
	140	/* PE allocation bitmap */
	141	unsigned long *pe_alloc;
	142
	143	/* M32 & IO segment maps */
	144	unsigned int *m32_segmap;
	145	unsigned int *io_segmap;
	146	struct pnv_ioda_pe *pe_array;
	147
137436c9 GS	148	/* IRQ chip */
	149	int irq_chip_init;
	150	struct irq_chip irq_chip;
	151
7ebdf956 GS	152	/* Sorted list of used PE's based
	153	* on the sequence of creation
	154	*/
	155	struct list_head pe_list;
	156
184cd4a3 BH	157	/* Reverse map of PEs, will have to extend if
	158	* we are to support more than 256 PEs, indexed
	159	* bus { bus, devfn }
	160	*/
	161	unsigned char pe_rmap[0x10000];
	162
	163	/* 32-bit TCE tables allocation */
	164	unsigned long tce32_count;
	165
	166	/* Total "weight" for the sake of DMA resources
	167	* allocation
	168	*/
	169	unsigned int dma_weight;
	170	unsigned int dma_pe_count;
	171
	172	/* Sorted list of used PE's, sorted at
	173	* boot for resource allocation purposes
	174	*/
7ebdf956	175	struct list_head pe_dma_list;
184cd4a3	176	} ioda;
61305a96	177	};
cee72d5b	178
ca1de5de	179	/* PHB and hub status structure */
cee72d5b BH	180	union {
	181	unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
	182	struct OpalIoP7IOCPhbErrorData p7ioc;
93aef2a7	183	struct OpalIoPhb3ErrorData phb3;
ca1de5de	184	struct OpalIoP7IOCErrorData hub_diag;
cee72d5b	185	} diag;
ca1de5de	186
61305a96 BH	187	};
	188
	189	extern struct pci_ops pnv_pci_ops;
8747f363 GS	190	#ifdef CONFIG_EEH
	191	extern struct pnv_eeh_ops ioda_eeh_ops;
	192	#endif
61305a96	193
93aef2a7 GS	194	void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
93aef2a7 GS	195	unsigned char *log_buff);
9bf41be6 GS	196	int pnv_pci_cfg_read(struct device_node *dn,
	197	int where, int size, u32 *val);
	198	int pnv_pci_cfg_write(struct device_node *dn,
	199	int where, int size, u32 val);
61305a96 BH	200	extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
	201	void *tce_mem, u64 tce_size,
	202	u64 dma_offset);
	203	extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
184cd4a3	204	extern void pnv_pci_init_ioda_hub(struct device_node *np);
aa0c033f	205	extern void pnv_pci_init_ioda2_phb(struct device_node *np);
4cce9550	206	extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
3ad26e5c	207	__be64 startp, __be64 endp, bool rm);
73ed148a	208
61305a96	209	#endif /* __POWERNV_PCI_H */