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55190f88 BH |
1 | /* |
2 | * SMP support for PowerNV machines. | |
3 | * | |
4 | * Copyright 2011 IBM Corp. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/smp.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/cpu.h> | |
21 | ||
22 | #include <asm/irq.h> | |
23 | #include <asm/smp.h> | |
24 | #include <asm/paca.h> | |
25 | #include <asm/machdep.h> | |
26 | #include <asm/cputable.h> | |
27 | #include <asm/firmware.h> | |
55190f88 BH |
28 | #include <asm/rtas.h> |
29 | #include <asm/vdso_datapage.h> | |
30 | #include <asm/cputhreads.h> | |
31 | #include <asm/xics.h> | |
14a43e69 | 32 | #include <asm/opal.h> |
f2038911 | 33 | #include <asm/runlatch.h> |
2751b628 | 34 | #include <asm/code-patching.h> |
d4e58e59 | 35 | #include <asm/dbell.h> |
755563bc PM |
36 | #include <asm/kvm_ppc.h> |
37 | #include <asm/ppc-opcode.h> | |
55190f88 BH |
38 | |
39 | #include "powernv.h" | |
40 | ||
344eb010 BH |
41 | #ifdef DEBUG |
42 | #include <asm/udbg.h> | |
43 | #define DBG(fmt...) udbg_printf(fmt) | |
44 | #else | |
45 | #define DBG(fmt...) | |
46 | #endif | |
47 | ||
061d19f2 | 48 | static void pnv_smp_setup_cpu(int cpu) |
55190f88 BH |
49 | { |
50 | if (cpu != boot_cpuid) | |
51 | xics_setup_cpu(); | |
d4e58e59 MN |
52 | |
53 | #ifdef CONFIG_PPC_DOORBELL | |
54 | if (cpu_has_feature(CPU_FTR_DBELL)) | |
55 | doorbell_setup_this_cpu(); | |
56 | #endif | |
55190f88 BH |
57 | } |
58 | ||
e51df2c1 | 59 | static int pnv_smp_kick_cpu(int nr) |
14a43e69 BH |
60 | { |
61 | unsigned int pcpu = get_hard_smp_processor_id(nr); | |
2751b628 AB |
62 | unsigned long start_here = |
63 | __pa(ppc_function_entry(generic_secondary_smp_init)); | |
14a43e69 BH |
64 | long rc; |
65 | ||
66 | BUG_ON(nr < 0 || nr >= NR_CPUS); | |
67 | ||
b2b48584 BH |
68 | /* |
69 | * If we already started or OPALv2 is not supported, we just | |
70 | * kick the CPU via the PACA | |
14a43e69 | 71 | */ |
b2b48584 BH |
72 | if (paca[nr].cpu_start || !firmware_has_feature(FW_FEATURE_OPALv2)) |
73 | goto kick; | |
74 | ||
75 | /* | |
76 | * At this point, the CPU can either be spinning on the way in | |
77 | * from kexec or be inside OPAL waiting to be started for the | |
78 | * first time. OPAL v3 allows us to query OPAL to know if it | |
79 | * has the CPUs, so we do that | |
80 | */ | |
81 | if (firmware_has_feature(FW_FEATURE_OPALv3)) { | |
82 | uint8_t status; | |
83 | ||
84 | rc = opal_query_cpu_status(pcpu, &status); | |
4ea9008b | 85 | if (rc != OPAL_SUCCESS) { |
b2b48584 | 86 | pr_warn("OPAL Error %ld querying CPU %d state\n", |
14a43e69 | 87 | rc, nr); |
4ea9008b BH |
88 | return -ENODEV; |
89 | } | |
b2b48584 BH |
90 | |
91 | /* | |
92 | * Already started, just kick it, probably coming from | |
93 | * kexec and spinning | |
94 | */ | |
95 | if (status == OPAL_THREAD_STARTED) | |
96 | goto kick; | |
97 | ||
98 | /* | |
99 | * Available/inactive, let's kick it | |
100 | */ | |
101 | if (status == OPAL_THREAD_INACTIVE) { | |
102 | pr_devel("OPAL: Starting CPU %d (HW 0x%x)...\n", | |
103 | nr, pcpu); | |
104 | rc = opal_start_cpu(pcpu, start_here); | |
105 | if (rc != OPAL_SUCCESS) { | |
106 | pr_warn("OPAL Error %ld starting CPU %d\n", | |
107 | rc, nr); | |
108 | return -ENODEV; | |
109 | } | |
110 | } else { | |
111 | /* | |
112 | * An unavailable CPU (or any other unknown status) | |
113 | * shouldn't be started. It should also | |
114 | * not be in the possible map but currently it can | |
115 | * happen | |
116 | */ | |
117 | pr_devel("OPAL: CPU %d (HW 0x%x) is unavailable" | |
118 | " (status %d)...\n", nr, pcpu, status); | |
119 | return -ENODEV; | |
120 | } | |
121 | } else { | |
122 | /* | |
123 | * On OPAL v2, we just kick it and hope for the best, | |
124 | * we must not test the error from opal_start_cpu() or | |
125 | * we would fail to get CPUs from kexec. | |
126 | */ | |
127 | opal_start_cpu(pcpu, start_here); | |
14a43e69 | 128 | } |
b2b48584 | 129 | kick: |
14a43e69 BH |
130 | return smp_generic_kick_cpu(nr); |
131 | } | |
132 | ||
344eb010 BH |
133 | #ifdef CONFIG_HOTPLUG_CPU |
134 | ||
135 | static int pnv_smp_cpu_disable(void) | |
136 | { | |
137 | int cpu = smp_processor_id(); | |
138 | ||
139 | /* This is identical to pSeries... might consolidate by | |
140 | * moving migrate_irqs_away to a ppc_md with default to | |
141 | * the generic fixup_irqs. --BenH. | |
142 | */ | |
143 | set_cpu_online(cpu, false); | |
144 | vdso_data->processorCount--; | |
145 | if (cpu == boot_cpuid) | |
146 | boot_cpuid = cpumask_any(cpu_online_mask); | |
147 | xics_migrate_irqs_away(); | |
148 | return 0; | |
149 | } | |
150 | ||
151 | static void pnv_smp_cpu_kill_self(void) | |
152 | { | |
153 | unsigned int cpu; | |
755563bc | 154 | unsigned long srr1, wmask; |
8eb8ac89 | 155 | u32 idle_states; |
344eb010 | 156 | |
344eb010 BH |
157 | /* Standard hot unplug procedure */ |
158 | local_irq_disable(); | |
159 | idle_task_exit(); | |
160 | current->active_mm = NULL; /* for sanity */ | |
161 | cpu = smp_processor_id(); | |
162 | DBG("CPU%d offline\n", cpu); | |
163 | generic_set_cpu_dead(cpu); | |
164 | smp_wmb(); | |
165 | ||
755563bc PM |
166 | wmask = SRR1_WAKEMASK; |
167 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) | |
168 | wmask = SRR1_WAKEMASK_P8; | |
169 | ||
8eb8ac89 | 170 | idle_states = pnv_get_supported_cpuidle_states(); |
344eb010 BH |
171 | /* We don't want to take decrementer interrupts while we are offline, |
172 | * so clear LPCR:PECE1. We keep PECE2 enabled. | |
173 | */ | |
174 | mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1); | |
175 | while (!generic_check_cpu_restart(cpu)) { | |
77b54e9f | 176 | |
f2038911 | 177 | ppc64_runlatch_off(); |
77b54e9f SP |
178 | |
179 | if (idle_states & OPAL_PM_WINKLE_ENABLED) | |
180 | srr1 = power7_winkle(); | |
181 | else if ((idle_states & OPAL_PM_SLEEP_ENABLED) || | |
7cba160a | 182 | (idle_states & OPAL_PM_SLEEP_ENABLED_ER1)) |
8eb8ac89 SP |
183 | srr1 = power7_sleep(); |
184 | else | |
185 | srr1 = power7_nap(1); | |
77b54e9f | 186 | |
f2038911 | 187 | ppc64_runlatch_on(); |
e2186023 | 188 | |
56548fc0 PM |
189 | /* |
190 | * If the SRR1 value indicates that we woke up due to | |
191 | * an external interrupt, then clear the interrupt. | |
192 | * We clear the interrupt before checking for the | |
193 | * reason, so as to avoid a race where we wake up for | |
194 | * some other reason, find nothing and clear the interrupt | |
195 | * just as some other cpu is sending us an interrupt. | |
196 | * If we returned from power7_nap as a result of | |
197 | * having finished executing in a KVM guest, then srr1 | |
198 | * contains 0. | |
199 | */ | |
755563bc | 200 | if ((srr1 & wmask) == SRR1_WAKEEE) { |
56548fc0 PM |
201 | icp_native_flush_interrupt(); |
202 | local_paca->irq_happened &= PACA_IRQ_HARD_DIS; | |
203 | smp_mb(); | |
755563bc PM |
204 | } else if ((srr1 & wmask) == SRR1_WAKEHDBELL) { |
205 | unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER); | |
206 | asm volatile(PPC_MSGCLR(%0) : : "r" (msg)); | |
207 | kvmppc_set_host_ipi(cpu, 0); | |
56548fc0 | 208 | } |
e2186023 ME |
209 | |
210 | if (cpu_core_split_required()) | |
211 | continue; | |
212 | ||
213 | if (!generic_check_cpu_restart(cpu)) | |
344eb010 | 214 | DBG("CPU%d Unexpected exit while offline !\n", cpu); |
344eb010 BH |
215 | } |
216 | mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_PECE1); | |
217 | DBG("CPU%d coming online...\n", cpu); | |
218 | } | |
219 | ||
220 | #endif /* CONFIG_HOTPLUG_CPU */ | |
221 | ||
d70a54e2 GK |
222 | static int pnv_cpu_bootable(unsigned int nr) |
223 | { | |
224 | /* | |
225 | * Starting with POWER8, the subcore logic relies on all threads of a | |
226 | * core being booted so that they can participate in split mode | |
227 | * switches. So on those machines we ignore the smt_enabled_at_boot | |
228 | * setting (smt-enabled on the kernel command line). | |
229 | */ | |
230 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) | |
231 | return 1; | |
232 | ||
233 | return smp_generic_cpu_bootable(nr); | |
234 | } | |
235 | ||
55190f88 BH |
236 | static struct smp_ops_t pnv_smp_ops = { |
237 | .message_pass = smp_muxed_ipi_message_pass, | |
238 | .cause_ipi = NULL, /* Filled at runtime by xics_smp_probe() */ | |
239 | .probe = xics_smp_probe, | |
14a43e69 | 240 | .kick_cpu = pnv_smp_kick_cpu, |
55190f88 | 241 | .setup_cpu = pnv_smp_setup_cpu, |
d70a54e2 | 242 | .cpu_bootable = pnv_cpu_bootable, |
344eb010 BH |
243 | #ifdef CONFIG_HOTPLUG_CPU |
244 | .cpu_disable = pnv_smp_cpu_disable, | |
245 | .cpu_die = generic_cpu_die, | |
246 | #endif /* CONFIG_HOTPLUG_CPU */ | |
55190f88 BH |
247 | }; |
248 | ||
249 | /* This is called very early during platform setup_arch */ | |
250 | void __init pnv_smp_init(void) | |
251 | { | |
252 | smp_ops = &pnv_smp_ops; | |
253 | ||
254 | /* XXX We don't yet have a proper entry point from HAL, for | |
255 | * now we rely on kexec-style entry from BML | |
256 | */ | |
257 | ||
258 | #ifdef CONFIG_PPC_RTAS | |
259 | /* Non-lpar has additional take/give timebase */ | |
260 | if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) { | |
261 | smp_ops->give_timebase = rtas_give_timebase; | |
262 | smp_ops->take_timebase = rtas_take_timebase; | |
263 | } | |
264 | #endif /* CONFIG_PPC_RTAS */ | |
344eb010 BH |
265 | |
266 | #ifdef CONFIG_HOTPLUG_CPU | |
267 | ppc_md.cpu_die = pnv_smp_cpu_kill_self; | |
268 | #endif | |
55190f88 | 269 | } |