Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * eeh.c | |
3 | * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation | |
69376502 | 4 | * |
1da177e4 LT |
5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
69376502 | 9 | * |
1da177e4 LT |
10 | * This program is distributed in the hope that it will be useful, |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
69376502 | 14 | * |
1da177e4 LT |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
6dee3fb9 | 20 | #include <linux/delay.h> |
1da177e4 LT |
21 | #include <linux/init.h> |
22 | #include <linux/list.h> | |
1da177e4 LT |
23 | #include <linux/pci.h> |
24 | #include <linux/proc_fs.h> | |
25 | #include <linux/rbtree.h> | |
26 | #include <linux/seq_file.h> | |
27 | #include <linux/spinlock.h> | |
69376502 | 28 | #include <asm/atomic.h> |
1da177e4 | 29 | #include <asm/eeh.h> |
172ca926 | 30 | #include <asm/eeh_event.h> |
1da177e4 LT |
31 | #include <asm/io.h> |
32 | #include <asm/machdep.h> | |
172ca926 | 33 | #include <asm/ppc-pci.h> |
1da177e4 | 34 | #include <asm/rtas.h> |
1da177e4 LT |
35 | |
36 | #undef DEBUG | |
37 | ||
38 | /** Overview: | |
39 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
40 | * dealing with PCI bus errors that can't be dealt with within the | |
41 | * usual PCI framework, except by check-stopping the CPU. Systems | |
42 | * that are designed for high-availability/reliability cannot afford | |
43 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
44 | * An EEH-capable bridge operates by converting a detected error | |
45 | * into a "slot freeze", taking the PCI adapter off-line, making | |
46 | * the slot behave, from the OS'es point of view, as if the slot | |
47 | * were "empty": all reads return 0xff's and all writes are silently | |
48 | * ignored. EEH slot isolation events can be triggered by parity | |
49 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
50 | * which in turn might be caused by low voltage on the bus, dust, |
51 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
52 | * |
53 | * Note, however, that one of the leading causes of EEH slot | |
54 | * freeze events are buggy device drivers, buggy device microcode, | |
55 | * or buggy device hardware. This is because any attempt by the | |
56 | * device to bus-master data to a memory address that is not | |
57 | * assigned to the device will trigger a slot freeze. (The idea | |
58 | * is to prevent devices-gone-wild from corrupting system memory). | |
59 | * Buggy hardware/drivers will have a miserable time co-existing | |
60 | * with EEH. | |
61 | * | |
62 | * Ideally, a PCI device driver, when suspecting that an isolation | |
63 | * event has occured (e.g. by reading 0xff's), will then ask EEH | |
64 | * whether this is the case, and then take appropriate steps to | |
65 | * reset the PCI slot, the PCI device, and then resume operations. | |
66 | * However, until that day, the checking is done here, with the | |
67 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
68 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
69 | * and sent out for processing. | |
70 | */ | |
71 | ||
5c1344e9 | 72 | /* If a device driver keeps reading an MMIO register in an interrupt |
1da177e4 LT |
73 | * handler after a slot isolation event has occurred, we assume it |
74 | * is broken and panic. This sets the threshold for how many read | |
75 | * attempts we allow before panicking. | |
76 | */ | |
2fd30be8 | 77 | #define EEH_MAX_FAILS 2100000 |
1da177e4 | 78 | |
17213c3b | 79 | /* Time to wait for a PCI slot to report status, in milliseconds */ |
9c547768 LV |
80 | #define PCI_BUS_RESET_WAIT_MSEC (60*1000) |
81 | ||
1da177e4 LT |
82 | /* RTAS tokens */ |
83 | static int ibm_set_eeh_option; | |
84 | static int ibm_set_slot_reset; | |
85 | static int ibm_read_slot_reset_state; | |
86 | static int ibm_read_slot_reset_state2; | |
87 | static int ibm_slot_error_detail; | |
25e591f6 | 88 | static int ibm_get_config_addr_info; |
147d6a37 | 89 | static int ibm_get_config_addr_info2; |
21e464dd | 90 | static int ibm_configure_bridge; |
1da177e4 | 91 | |
1e28a7dd DW |
92 | int eeh_subsystem_enabled; |
93 | EXPORT_SYMBOL(eeh_subsystem_enabled); | |
1da177e4 | 94 | |
fd761fd8 LV |
95 | /* Lock to avoid races due to multiple reports of an error */ |
96 | static DEFINE_SPINLOCK(confirm_error_lock); | |
97 | ||
17213c3b LV |
98 | /* Buffer for reporting slot-error-detail rtas calls. Its here |
99 | * in BSS, and not dynamically alloced, so that it ends up in | |
100 | * RMO where RTAS can access it. | |
101 | */ | |
1da177e4 LT |
102 | static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX]; |
103 | static DEFINE_SPINLOCK(slot_errbuf_lock); | |
104 | static int eeh_error_buf_size; | |
105 | ||
17213c3b LV |
106 | /* Buffer for reporting pci register dumps. Its here in BSS, and |
107 | * not dynamically alloced, so that it ends up in RMO where RTAS | |
108 | * can access it. | |
109 | */ | |
d99bb1db LV |
110 | #define EEH_PCI_REGS_LOG_LEN 4096 |
111 | static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; | |
112 | ||
1da177e4 | 113 | /* System monitoring statistics */ |
257ffc64 LV |
114 | static unsigned long no_device; |
115 | static unsigned long no_dn; | |
116 | static unsigned long no_cfg_addr; | |
117 | static unsigned long ignored_check; | |
118 | static unsigned long total_mmio_ffs; | |
119 | static unsigned long false_positives; | |
257ffc64 | 120 | static unsigned long slot_resets; |
1da177e4 | 121 | |
7684b40c LV |
122 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
123 | ||
1da177e4 | 124 | /* --------------------------------------------------------------- */ |
5d5a0936 | 125 | /* Below lies the EEH event infrastructure */ |
1da177e4 | 126 | |
d99bb1db LV |
127 | static void rtas_slot_error_detail(struct pci_dn *pdn, int severity, |
128 | char *driver_log, size_t loglen) | |
df7242b1 | 129 | { |
fcb7543e | 130 | int config_addr; |
df7242b1 LV |
131 | unsigned long flags; |
132 | int rc; | |
133 | ||
134 | /* Log the error with the rtas logger */ | |
135 | spin_lock_irqsave(&slot_errbuf_lock, flags); | |
136 | memset(slot_errbuf, 0, eeh_error_buf_size); | |
137 | ||
fcb7543e LV |
138 | /* Use PE configuration address, if present */ |
139 | config_addr = pdn->eeh_config_addr; | |
140 | if (pdn->eeh_pe_config_addr) | |
141 | config_addr = pdn->eeh_pe_config_addr; | |
142 | ||
df7242b1 | 143 | rc = rtas_call(ibm_slot_error_detail, |
fcb7543e | 144 | 8, 1, NULL, config_addr, |
df7242b1 | 145 | BUID_HI(pdn->phb->buid), |
d99bb1db LV |
146 | BUID_LO(pdn->phb->buid), |
147 | virt_to_phys(driver_log), loglen, | |
df7242b1 LV |
148 | virt_to_phys(slot_errbuf), |
149 | eeh_error_buf_size, | |
150 | severity); | |
151 | ||
152 | if (rc == 0) | |
153 | log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0); | |
154 | spin_unlock_irqrestore(&slot_errbuf_lock, flags); | |
155 | } | |
156 | ||
d99bb1db LV |
157 | /** |
158 | * gather_pci_data - copy assorted PCI config space registers to buff | |
159 | * @pdn: device to report data for | |
160 | * @buf: point to buffer in which to log | |
161 | * @len: amount of room in buffer | |
162 | * | |
163 | * This routine captures assorted PCI configuration space data, | |
164 | * and puts them into a buffer for RTAS error logging. | |
165 | */ | |
166 | static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len) | |
167 | { | |
168 | u32 cfg; | |
fcf9892b | 169 | int cap, i; |
d99bb1db LV |
170 | int n = 0; |
171 | ||
fcf9892b LV |
172 | n += scnprintf(buf+n, len-n, "%s\n", pdn->node->full_name); |
173 | printk(KERN_WARNING "EEH: of node=%s\n", pdn->node->full_name); | |
174 | ||
d99bb1db | 175 | rtas_read_config(pdn, PCI_VENDOR_ID, 4, &cfg); |
fcf9892b LV |
176 | n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); |
177 | printk(KERN_WARNING "EEH: PCI device/vendor: %08x\n", cfg); | |
178 | ||
d99bb1db LV |
179 | rtas_read_config(pdn, PCI_COMMAND, 4, &cfg); |
180 | n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); | |
fcf9892b LV |
181 | printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg); |
182 | ||
183 | /* Dump out the PCI-X command and status regs */ | |
184 | cap = pci_find_capability(pdn->pcidev, PCI_CAP_ID_PCIX); | |
185 | if (cap) { | |
186 | rtas_read_config(pdn, cap, 4, &cfg); | |
187 | n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); | |
188 | printk(KERN_WARNING "EEH: PCI-X cmd: %08x\n", cfg); | |
189 | ||
190 | rtas_read_config(pdn, cap+4, 4, &cfg); | |
191 | n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); | |
192 | printk(KERN_WARNING "EEH: PCI-X status: %08x\n", cfg); | |
193 | } | |
194 | ||
195 | /* If PCI-E capable, dump PCI-E cap 10, and the AER */ | |
196 | cap = pci_find_capability(pdn->pcidev, PCI_CAP_ID_EXP); | |
197 | if (cap) { | |
198 | n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); | |
199 | printk(KERN_WARNING | |
200 | "EEH: PCI-E capabilities and status follow:\n"); | |
201 | ||
202 | for (i=0; i<=8; i++) { | |
203 | rtas_read_config(pdn, cap+4*i, 4, &cfg); | |
204 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
205 | printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg); | |
206 | } | |
207 | ||
208 | cap = pci_find_ext_capability(pdn->pcidev,PCI_EXT_CAP_ID_ERR); | |
209 | if (cap) { | |
210 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); | |
211 | printk(KERN_WARNING | |
212 | "EEH: PCI-E AER capability register set follows:\n"); | |
213 | ||
214 | for (i=0; i<14; i++) { | |
215 | rtas_read_config(pdn, cap+4*i, 4, &cfg); | |
216 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
217 | printk(KERN_WARNING "EEH: PCI-E AER %02x: %08x\n", i, cfg); | |
218 | } | |
219 | } | |
220 | } | |
d99bb1db LV |
221 | return n; |
222 | } | |
223 | ||
224 | void eeh_slot_error_detail(struct pci_dn *pdn, int severity) | |
225 | { | |
226 | size_t loglen = 0; | |
17213c3b | 227 | pci_regs_buf[0] = 0; |
d99bb1db LV |
228 | |
229 | rtas_pci_enable(pdn, EEH_THAW_MMIO); | |
230 | loglen = gather_pci_data(pdn, pci_regs_buf, EEH_PCI_REGS_LOG_LEN); | |
231 | ||
232 | rtas_slot_error_detail(pdn, severity, pci_regs_buf, loglen); | |
233 | } | |
234 | ||
1da177e4 LT |
235 | /** |
236 | * read_slot_reset_state - Read the reset state of a device node's slot | |
237 | * @dn: device node to read | |
238 | * @rets: array to return results in | |
239 | */ | |
69376502 | 240 | static int read_slot_reset_state(struct pci_dn *pdn, int rets[]) |
1da177e4 LT |
241 | { |
242 | int token, outputs; | |
fcb7543e | 243 | int config_addr; |
1da177e4 LT |
244 | |
245 | if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) { | |
246 | token = ibm_read_slot_reset_state2; | |
247 | outputs = 4; | |
248 | } else { | |
249 | token = ibm_read_slot_reset_state; | |
69376502 | 250 | rets[2] = 0; /* fake PE Unavailable info */ |
1da177e4 LT |
251 | outputs = 3; |
252 | } | |
253 | ||
fcb7543e LV |
254 | /* Use PE configuration address, if present */ |
255 | config_addr = pdn->eeh_config_addr; | |
256 | if (pdn->eeh_pe_config_addr) | |
257 | config_addr = pdn->eeh_pe_config_addr; | |
258 | ||
259 | return rtas_call(token, 3, outputs, rets, config_addr, | |
1635317f | 260 | BUID_HI(pdn->phb->buid), BUID_LO(pdn->phb->buid)); |
1da177e4 LT |
261 | } |
262 | ||
9c547768 LV |
263 | /** |
264 | * eeh_wait_for_slot_status - returns error status of slot | |
265 | * @pdn pci device node | |
266 | * @max_wait_msecs maximum number to millisecs to wait | |
267 | * | |
268 | * Return negative value if a permanent error, else return | |
269 | * Partition Endpoint (PE) status value. | |
270 | * | |
271 | * If @max_wait_msecs is positive, then this routine will | |
272 | * sleep until a valid status can be obtained, or until | |
273 | * the max allowed wait time is exceeded, in which case | |
274 | * a -2 is returned. | |
275 | */ | |
276 | int | |
277 | eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs) | |
278 | { | |
279 | int rc; | |
280 | int rets[3]; | |
281 | int mwait; | |
282 | ||
283 | while (1) { | |
284 | rc = read_slot_reset_state(pdn, rets); | |
285 | if (rc) return rc; | |
286 | if (rets[1] == 0) return -1; /* EEH is not supported */ | |
287 | ||
288 | if (rets[0] != 5) return rets[0]; /* return actual status */ | |
289 | ||
290 | if (rets[2] == 0) return -1; /* permanently unavailable */ | |
291 | ||
292 | if (max_wait_msecs <= 0) return -1; | |
293 | ||
294 | mwait = rets[2]; | |
295 | if (mwait <= 0) { | |
296 | printk (KERN_WARNING | |
297 | "EEH: Firmware returned bad wait value=%d\n", mwait); | |
298 | mwait = 1000; | |
299 | } else if (mwait > 300*1000) { | |
300 | printk (KERN_WARNING | |
301 | "EEH: Firmware is taking too long, time=%d\n", mwait); | |
302 | mwait = 300*1000; | |
303 | } | |
304 | max_wait_msecs -= mwait; | |
305 | msleep (mwait); | |
306 | } | |
307 | ||
308 | printk(KERN_WARNING "EEH: Timed out waiting for slot status\n"); | |
309 | return -2; | |
310 | } | |
311 | ||
1da177e4 LT |
312 | /** |
313 | * eeh_token_to_phys - convert EEH address token to phys address | |
69376502 | 314 | * @token i/o token, should be address in the form 0xA.... |
1da177e4 LT |
315 | */ |
316 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
317 | { | |
318 | pte_t *ptep; | |
319 | unsigned long pa; | |
320 | ||
20cee16c | 321 | ptep = find_linux_pte(init_mm.pgd, token); |
1da177e4 LT |
322 | if (!ptep) |
323 | return token; | |
324 | pa = pte_pfn(*ptep) << PAGE_SHIFT; | |
325 | ||
326 | return pa | (token & (PAGE_SIZE-1)); | |
327 | } | |
328 | ||
fd761fd8 LV |
329 | /** |
330 | * Return the "partitionable endpoint" (pe) under which this device lies | |
331 | */ | |
9fb40eb8 | 332 | struct device_node * find_device_pe(struct device_node *dn) |
fd761fd8 LV |
333 | { |
334 | while ((dn->parent) && PCI_DN(dn->parent) && | |
335 | (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) { | |
336 | dn = dn->parent; | |
337 | } | |
338 | return dn; | |
339 | } | |
340 | ||
341 | /** Mark all devices that are peers of this device as failed. | |
342 | * Mark the device driver too, so that it can see the failure | |
343 | * immediately; this is critical, since some drivers poll | |
344 | * status registers in interrupts ... If a driver is polling, | |
345 | * and the slot is frozen, then the driver can deadlock in | |
346 | * an interrupt context, which is bad. | |
347 | */ | |
348 | ||
d9564ad1 | 349 | static void __eeh_mark_slot (struct device_node *dn, int mode_flag) |
fd761fd8 LV |
350 | { |
351 | while (dn) { | |
d9564ad1 | 352 | if (PCI_DN(dn)) { |
77bd7415 LV |
353 | /* Mark the pci device driver too */ |
354 | struct pci_dev *dev = PCI_DN(dn)->pcidev; | |
ea183a95 OJ |
355 | |
356 | PCI_DN(dn)->eeh_mode |= mode_flag; | |
357 | ||
77bd7415 LV |
358 | if (dev && dev->driver) |
359 | dev->error_state = pci_channel_io_frozen; | |
360 | ||
d9564ad1 LV |
361 | if (dn->child) |
362 | __eeh_mark_slot (dn->child, mode_flag); | |
363 | } | |
fd761fd8 LV |
364 | dn = dn->sibling; |
365 | } | |
366 | } | |
367 | ||
d9564ad1 LV |
368 | void eeh_mark_slot (struct device_node *dn, int mode_flag) |
369 | { | |
022d51b1 | 370 | struct pci_dev *dev; |
d9564ad1 | 371 | dn = find_device_pe (dn); |
3914ac7b LV |
372 | |
373 | /* Back up one, since config addrs might be shared */ | |
4980d5eb | 374 | if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent)) |
3914ac7b LV |
375 | dn = dn->parent; |
376 | ||
d9564ad1 | 377 | PCI_DN(dn)->eeh_mode |= mode_flag; |
022d51b1 LV |
378 | |
379 | /* Mark the pci device too */ | |
380 | dev = PCI_DN(dn)->pcidev; | |
381 | if (dev) | |
382 | dev->error_state = pci_channel_io_frozen; | |
383 | ||
d9564ad1 LV |
384 | __eeh_mark_slot (dn->child, mode_flag); |
385 | } | |
386 | ||
387 | static void __eeh_clear_slot (struct device_node *dn, int mode_flag) | |
fd761fd8 LV |
388 | { |
389 | while (dn) { | |
d9564ad1 LV |
390 | if (PCI_DN(dn)) { |
391 | PCI_DN(dn)->eeh_mode &= ~mode_flag; | |
392 | PCI_DN(dn)->eeh_check_count = 0; | |
393 | if (dn->child) | |
394 | __eeh_clear_slot (dn->child, mode_flag); | |
395 | } | |
fd761fd8 LV |
396 | dn = dn->sibling; |
397 | } | |
398 | } | |
399 | ||
d9564ad1 | 400 | void eeh_clear_slot (struct device_node *dn, int mode_flag) |
fd761fd8 LV |
401 | { |
402 | unsigned long flags; | |
403 | spin_lock_irqsave(&confirm_error_lock, flags); | |
3914ac7b | 404 | |
d9564ad1 | 405 | dn = find_device_pe (dn); |
3914ac7b LV |
406 | |
407 | /* Back up one, since config addrs might be shared */ | |
4980d5eb | 408 | if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent)) |
3914ac7b LV |
409 | dn = dn->parent; |
410 | ||
d9564ad1 LV |
411 | PCI_DN(dn)->eeh_mode &= ~mode_flag; |
412 | PCI_DN(dn)->eeh_check_count = 0; | |
413 | __eeh_clear_slot (dn->child, mode_flag); | |
fd761fd8 LV |
414 | spin_unlock_irqrestore(&confirm_error_lock, flags); |
415 | } | |
416 | ||
1da177e4 LT |
417 | /** |
418 | * eeh_dn_check_failure - check if all 1's data is due to EEH slot freeze | |
419 | * @dn device node | |
420 | * @dev pci device, if known | |
421 | * | |
422 | * Check for an EEH failure for the given device node. Call this | |
423 | * routine if the result of a read was all 0xff's and you want to | |
424 | * find out if this is due to an EEH slot freeze. This routine | |
425 | * will query firmware for the EEH status. | |
426 | * | |
427 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 428 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
429 | * |
430 | * It is safe to call this routine in an interrupt context. | |
431 | */ | |
432 | int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev) | |
433 | { | |
434 | int ret; | |
435 | int rets[3]; | |
436 | unsigned long flags; | |
1635317f | 437 | struct pci_dn *pdn; |
fd761fd8 | 438 | int rc = 0; |
1da177e4 | 439 | |
257ffc64 | 440 | total_mmio_ffs++; |
1da177e4 LT |
441 | |
442 | if (!eeh_subsystem_enabled) | |
443 | return 0; | |
444 | ||
177bc936 | 445 | if (!dn) { |
257ffc64 | 446 | no_dn++; |
1da177e4 | 447 | return 0; |
177bc936 | 448 | } |
69376502 | 449 | pdn = PCI_DN(dn); |
1da177e4 LT |
450 | |
451 | /* Access to IO BARs might get this far and still not want checking. */ | |
f8632c82 | 452 | if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) || |
1635317f | 453 | pdn->eeh_mode & EEH_MODE_NOCHECK) { |
257ffc64 | 454 | ignored_check++; |
177bc936 | 455 | #ifdef DEBUG |
f8632c82 LV |
456 | printk ("EEH:ignored check (%x) for %s %s\n", |
457 | pdn->eeh_mode, pci_name (dev), dn->full_name); | |
177bc936 | 458 | #endif |
1da177e4 LT |
459 | return 0; |
460 | } | |
461 | ||
fcb7543e | 462 | if (!pdn->eeh_config_addr && !pdn->eeh_pe_config_addr) { |
257ffc64 | 463 | no_cfg_addr++; |
1da177e4 LT |
464 | return 0; |
465 | } | |
466 | ||
fd761fd8 LV |
467 | /* If we already have a pending isolation event for this |
468 | * slot, we know it's bad already, we don't need to check. | |
469 | * Do this checking under a lock; as multiple PCI devices | |
470 | * in one slot might report errors simultaneously, and we | |
471 | * only want one error recovery routine running. | |
1da177e4 | 472 | */ |
fd761fd8 LV |
473 | spin_lock_irqsave(&confirm_error_lock, flags); |
474 | rc = 1; | |
1635317f | 475 | if (pdn->eeh_mode & EEH_MODE_ISOLATED) { |
5c1344e9 LV |
476 | pdn->eeh_check_count ++; |
477 | if (pdn->eeh_check_count >= EEH_MAX_FAILS) { | |
478 | printk (KERN_ERR "EEH: Device driver ignored %d bad reads, panicing\n", | |
479 | pdn->eeh_check_count); | |
480 | dump_stack(); | |
d0e70341 | 481 | msleep(5000); |
5c1344e9 | 482 | |
1da177e4 | 483 | /* re-read the slot reset state */ |
69376502 | 484 | if (read_slot_reset_state(pdn, rets) != 0) |
1da177e4 | 485 | rets[0] = -1; /* reset state unknown */ |
5c1344e9 LV |
486 | |
487 | /* If we are here, then we hit an infinite loop. Stop. */ | |
488 | panic("EEH: MMIO halt (%d) on device:%s\n", rets[0], pci_name(dev)); | |
1da177e4 | 489 | } |
fd761fd8 | 490 | goto dn_unlock; |
1da177e4 LT |
491 | } |
492 | ||
493 | /* | |
494 | * Now test for an EEH failure. This is VERY expensive. | |
495 | * Note that the eeh_config_addr may be a parent device | |
496 | * in the case of a device behind a bridge, or it may be | |
497 | * function zero of a multi-function device. | |
498 | * In any case they must share a common PHB. | |
499 | */ | |
69376502 | 500 | ret = read_slot_reset_state(pdn, rets); |
76e6faf7 LV |
501 | |
502 | /* If the call to firmware failed, punt */ | |
503 | if (ret != 0) { | |
504 | printk(KERN_WARNING "EEH: read_slot_reset_state() failed; rc=%d dn=%s\n", | |
505 | ret, dn->full_name); | |
257ffc64 | 506 | false_positives++; |
858955bd | 507 | pdn->eeh_false_positives ++; |
fd761fd8 LV |
508 | rc = 0; |
509 | goto dn_unlock; | |
76e6faf7 LV |
510 | } |
511 | ||
39d16e29 LV |
512 | /* Note that config-io to empty slots may fail; |
513 | * they are empty when they don't have children. */ | |
514 | if ((rets[0] == 5) && (dn->child == NULL)) { | |
515 | false_positives++; | |
858955bd | 516 | pdn->eeh_false_positives ++; |
39d16e29 LV |
517 | rc = 0; |
518 | goto dn_unlock; | |
519 | } | |
520 | ||
76e6faf7 LV |
521 | /* If EEH is not supported on this device, punt. */ |
522 | if (rets[1] != 1) { | |
523 | printk(KERN_WARNING "EEH: event on unsupported device, rc=%d dn=%s\n", | |
524 | ret, dn->full_name); | |
257ffc64 | 525 | false_positives++; |
858955bd | 526 | pdn->eeh_false_positives ++; |
fd761fd8 LV |
527 | rc = 0; |
528 | goto dn_unlock; | |
76e6faf7 LV |
529 | } |
530 | ||
531 | /* If not the kind of error we know about, punt. */ | |
90375f53 | 532 | if (rets[0] != 1 && rets[0] != 2 && rets[0] != 4 && rets[0] != 5) { |
257ffc64 | 533 | false_positives++; |
858955bd | 534 | pdn->eeh_false_positives ++; |
fd761fd8 LV |
535 | rc = 0; |
536 | goto dn_unlock; | |
76e6faf7 LV |
537 | } |
538 | ||
257ffc64 | 539 | slot_resets++; |
fd761fd8 LV |
540 | |
541 | /* Avoid repeated reports of this failure, including problems | |
542 | * with other functions on this device, and functions under | |
543 | * bridges. */ | |
d9564ad1 | 544 | eeh_mark_slot (dn, EEH_MODE_ISOLATED); |
fd761fd8 | 545 | spin_unlock_irqrestore(&confirm_error_lock, flags); |
1da177e4 | 546 | |
d0ab95ca | 547 | eeh_send_failure_event (dn, dev); |
77bd7415 | 548 | |
1da177e4 LT |
549 | /* Most EEH events are due to device driver bugs. Having |
550 | * a stack trace will help the device-driver authors figure | |
551 | * out what happened. So print that out. */ | |
90375f53 | 552 | dump_stack(); |
fd761fd8 LV |
553 | return 1; |
554 | ||
555 | dn_unlock: | |
556 | spin_unlock_irqrestore(&confirm_error_lock, flags); | |
557 | return rc; | |
1da177e4 LT |
558 | } |
559 | ||
fd761fd8 | 560 | EXPORT_SYMBOL_GPL(eeh_dn_check_failure); |
1da177e4 LT |
561 | |
562 | /** | |
563 | * eeh_check_failure - check if all 1's data is due to EEH slot freeze | |
564 | * @token i/o token, should be address in the form 0xA.... | |
565 | * @val value, should be all 1's (XXX why do we need this arg??) | |
566 | * | |
1da177e4 LT |
567 | * Check for an EEH failure at the given token address. Call this |
568 | * routine if the result of a read was all 0xff's and you want to | |
569 | * find out if this is due to an EEH slot freeze event. This routine | |
570 | * will query firmware for the EEH status. | |
571 | * | |
572 | * Note this routine is safe to call in an interrupt context. | |
573 | */ | |
574 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
575 | { | |
576 | unsigned long addr; | |
577 | struct pci_dev *dev; | |
578 | struct device_node *dn; | |
579 | ||
580 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
581 | addr = eeh_token_to_phys((unsigned long __force) token); | |
582 | dev = pci_get_device_by_addr(addr); | |
177bc936 | 583 | if (!dev) { |
257ffc64 | 584 | no_device++; |
1da177e4 | 585 | return val; |
177bc936 | 586 | } |
1da177e4 LT |
587 | |
588 | dn = pci_device_to_OF_node(dev); | |
589 | eeh_dn_check_failure (dn, dev); | |
590 | ||
591 | pci_dev_put(dev); | |
592 | return val; | |
593 | } | |
594 | ||
595 | EXPORT_SYMBOL(eeh_check_failure); | |
596 | ||
6dee3fb9 LV |
597 | /* ------------------------------------------------------------- */ |
598 | /* The code below deals with error recovery */ | |
599 | ||
47b5c838 LV |
600 | /** |
601 | * rtas_pci_enable - enable MMIO or DMA transfers for this slot | |
602 | * @pdn pci device node | |
603 | */ | |
604 | ||
605 | int | |
606 | rtas_pci_enable(struct pci_dn *pdn, int function) | |
607 | { | |
608 | int config_addr; | |
609 | int rc; | |
610 | ||
611 | /* Use PE configuration address, if present */ | |
612 | config_addr = pdn->eeh_config_addr; | |
613 | if (pdn->eeh_pe_config_addr) | |
614 | config_addr = pdn->eeh_pe_config_addr; | |
615 | ||
616 | rc = rtas_call(ibm_set_eeh_option, 4, 1, NULL, | |
617 | config_addr, | |
618 | BUID_HI(pdn->phb->buid), | |
619 | BUID_LO(pdn->phb->buid), | |
620 | function); | |
621 | ||
622 | if (rc) | |
fa1be476 | 623 | printk(KERN_WARNING "EEH: Unexpected state change %d, err=%d dn=%s\n", |
47b5c838 LV |
624 | function, rc, pdn->node->full_name); |
625 | ||
fa1be476 LV |
626 | rc = eeh_wait_for_slot_status (pdn, PCI_BUS_RESET_WAIT_MSEC); |
627 | if ((rc == 4) && (function == EEH_THAW_MMIO)) | |
628 | return 0; | |
629 | ||
47b5c838 LV |
630 | return rc; |
631 | } | |
632 | ||
cb5b5624 LV |
633 | /** |
634 | * rtas_pci_slot_reset - raises/lowers the pci #RST line | |
635 | * @pdn pci device node | |
636 | * @state: 1/0 to raise/lower the #RST | |
6dee3fb9 LV |
637 | * |
638 | * Clear the EEH-frozen condition on a slot. This routine | |
639 | * asserts the PCI #RST line if the 'state' argument is '1', | |
640 | * and drops the #RST line if 'state is '0'. This routine is | |
641 | * safe to call in an interrupt context. | |
642 | * | |
643 | */ | |
644 | ||
645 | static void | |
646 | rtas_pci_slot_reset(struct pci_dn *pdn, int state) | |
647 | { | |
25e591f6 | 648 | int config_addr; |
6dee3fb9 LV |
649 | int rc; |
650 | ||
651 | BUG_ON (pdn==NULL); | |
652 | ||
653 | if (!pdn->phb) { | |
654 | printk (KERN_WARNING "EEH: in slot reset, device node %s has no phb\n", | |
655 | pdn->node->full_name); | |
656 | return; | |
657 | } | |
658 | ||
25e591f6 LV |
659 | /* Use PE configuration address, if present */ |
660 | config_addr = pdn->eeh_config_addr; | |
661 | if (pdn->eeh_pe_config_addr) | |
662 | config_addr = pdn->eeh_pe_config_addr; | |
663 | ||
6dee3fb9 | 664 | rc = rtas_call(ibm_set_slot_reset,4,1, NULL, |
25e591f6 | 665 | config_addr, |
6dee3fb9 LV |
666 | BUID_HI(pdn->phb->buid), |
667 | BUID_LO(pdn->phb->buid), | |
668 | state); | |
e1029263 LV |
669 | if (rc) |
670 | printk (KERN_WARNING "EEH: Unable to reset the failed slot," | |
671 | " (%d) #RST=%d dn=%s\n", | |
6dee3fb9 | 672 | rc, state, pdn->node->full_name); |
6dee3fb9 LV |
673 | } |
674 | ||
00c2ae35 BK |
675 | /** |
676 | * pcibios_set_pcie_slot_reset - Set PCI-E reset state | |
677 | * @dev: pci device struct | |
678 | * @state: reset state to enter | |
679 | * | |
680 | * Return value: | |
681 | * 0 if success | |
682 | **/ | |
683 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
684 | { | |
685 | struct device_node *dn = pci_device_to_OF_node(dev); | |
686 | struct pci_dn *pdn = PCI_DN(dn); | |
687 | ||
688 | switch (state) { | |
689 | case pcie_deassert_reset: | |
690 | rtas_pci_slot_reset(pdn, 0); | |
691 | break; | |
692 | case pcie_hot_reset: | |
693 | rtas_pci_slot_reset(pdn, 1); | |
694 | break; | |
695 | case pcie_warm_reset: | |
696 | rtas_pci_slot_reset(pdn, 3); | |
697 | break; | |
698 | default: | |
699 | return -EINVAL; | |
700 | }; | |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
cb5b5624 LV |
705 | /** |
706 | * rtas_set_slot_reset -- assert the pci #RST line for 1/4 second | |
707 | * @pdn: pci device node to be reset. | |
b6495c0c LV |
708 | * |
709 | * Return 0 if success, else a non-zero value. | |
6dee3fb9 LV |
710 | */ |
711 | ||
e1029263 | 712 | static void __rtas_set_slot_reset(struct pci_dn *pdn) |
6dee3fb9 | 713 | { |
6dee3fb9 LV |
714 | rtas_pci_slot_reset (pdn, 1); |
715 | ||
716 | /* The PCI bus requires that the reset be held high for at least | |
717 | * a 100 milliseconds. We wait a bit longer 'just in case'. */ | |
718 | ||
719 | #define PCI_BUS_RST_HOLD_TIME_MSEC 250 | |
720 | msleep (PCI_BUS_RST_HOLD_TIME_MSEC); | |
d9564ad1 LV |
721 | |
722 | /* We might get hit with another EEH freeze as soon as the | |
723 | * pci slot reset line is dropped. Make sure we don't miss | |
724 | * these, and clear the flag now. */ | |
725 | eeh_clear_slot (pdn->node, EEH_MODE_ISOLATED); | |
726 | ||
6dee3fb9 LV |
727 | rtas_pci_slot_reset (pdn, 0); |
728 | ||
729 | /* After a PCI slot has been reset, the PCI Express spec requires | |
730 | * a 1.5 second idle time for the bus to stabilize, before starting | |
731 | * up traffic. */ | |
732 | #define PCI_BUS_SETTLE_TIME_MSEC 1800 | |
733 | msleep (PCI_BUS_SETTLE_TIME_MSEC); | |
e1029263 LV |
734 | } |
735 | ||
736 | int rtas_set_slot_reset(struct pci_dn *pdn) | |
737 | { | |
738 | int i, rc; | |
739 | ||
9c547768 LV |
740 | /* Take three shots at resetting the bus */ |
741 | for (i=0; i<3; i++) { | |
742 | __rtas_set_slot_reset(pdn); | |
6dee3fb9 | 743 | |
9c547768 | 744 | rc = eeh_wait_for_slot_status(pdn, PCI_BUS_RESET_WAIT_MSEC); |
b6495c0c LV |
745 | if (rc == 0) |
746 | return 0; | |
e1029263 | 747 | |
e1029263 LV |
748 | if (rc < 0) { |
749 | printk (KERN_ERR "EEH: unrecoverable slot failure %s\n", | |
750 | pdn->node->full_name); | |
b6495c0c | 751 | return -1; |
e1029263 | 752 | } |
9c547768 LV |
753 | printk (KERN_ERR "EEH: bus reset %d failed on slot %s\n", |
754 | i+1, pdn->node->full_name); | |
6dee3fb9 | 755 | } |
b6495c0c | 756 | |
9c547768 | 757 | return -1; |
6dee3fb9 LV |
758 | } |
759 | ||
8b553f32 LV |
760 | /* ------------------------------------------------------- */ |
761 | /** Save and restore of PCI BARs | |
762 | * | |
763 | * Although firmware will set up BARs during boot, it doesn't | |
764 | * set up device BAR's after a device reset, although it will, | |
765 | * if requested, set up bridge configuration. Thus, we need to | |
766 | * configure the PCI devices ourselves. | |
767 | */ | |
768 | ||
769 | /** | |
770 | * __restore_bars - Restore the Base Address Registers | |
cb5b5624 LV |
771 | * @pdn: pci device node |
772 | * | |
8b553f32 LV |
773 | * Loads the PCI configuration space base address registers, |
774 | * the expansion ROM base address, the latency timer, and etc. | |
775 | * from the saved values in the device node. | |
776 | */ | |
777 | static inline void __restore_bars (struct pci_dn *pdn) | |
778 | { | |
779 | int i; | |
780 | ||
781 | if (NULL==pdn->phb) return; | |
782 | for (i=4; i<10; i++) { | |
783 | rtas_write_config(pdn, i*4, 4, pdn->config_space[i]); | |
784 | } | |
785 | ||
786 | /* 12 == Expansion ROM Address */ | |
787 | rtas_write_config(pdn, 12*4, 4, pdn->config_space[12]); | |
788 | ||
789 | #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF)) | |
790 | #define SAVED_BYTE(OFF) (((u8 *)(pdn->config_space))[BYTE_SWAP(OFF)]) | |
791 | ||
792 | rtas_write_config (pdn, PCI_CACHE_LINE_SIZE, 1, | |
793 | SAVED_BYTE(PCI_CACHE_LINE_SIZE)); | |
794 | ||
795 | rtas_write_config (pdn, PCI_LATENCY_TIMER, 1, | |
796 | SAVED_BYTE(PCI_LATENCY_TIMER)); | |
797 | ||
798 | /* max latency, min grant, interrupt pin and line */ | |
799 | rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]); | |
800 | } | |
801 | ||
802 | /** | |
803 | * eeh_restore_bars - restore the PCI config space info | |
804 | * | |
805 | * This routine performs a recursive walk to the children | |
806 | * of this device as well. | |
807 | */ | |
808 | void eeh_restore_bars(struct pci_dn *pdn) | |
809 | { | |
810 | struct device_node *dn; | |
811 | if (!pdn) | |
812 | return; | |
813 | ||
7684b40c | 814 | if ((pdn->eeh_mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(pdn->class_code)) |
8b553f32 LV |
815 | __restore_bars (pdn); |
816 | ||
817 | dn = pdn->node->child; | |
818 | while (dn) { | |
819 | eeh_restore_bars (PCI_DN(dn)); | |
820 | dn = dn->sibling; | |
821 | } | |
822 | } | |
823 | ||
824 | /** | |
825 | * eeh_save_bars - save device bars | |
826 | * | |
827 | * Save the values of the device bars. Unlike the restore | |
828 | * routine, this routine is *not* recursive. This is because | |
829 | * PCI devices are added individuallly; but, for the restore, | |
830 | * an entire slot is reset at a time. | |
831 | */ | |
7684b40c | 832 | static void eeh_save_bars(struct pci_dn *pdn) |
8b553f32 LV |
833 | { |
834 | int i; | |
835 | ||
7684b40c | 836 | if (!pdn ) |
8b553f32 LV |
837 | return; |
838 | ||
839 | for (i = 0; i < 16; i++) | |
7684b40c | 840 | rtas_read_config(pdn, i * 4, 4, &pdn->config_space[i]); |
8b553f32 LV |
841 | } |
842 | ||
843 | void | |
844 | rtas_configure_bridge(struct pci_dn *pdn) | |
845 | { | |
fcb7543e | 846 | int config_addr; |
8b553f32 LV |
847 | int rc; |
848 | ||
fcb7543e LV |
849 | /* Use PE configuration address, if present */ |
850 | config_addr = pdn->eeh_config_addr; | |
851 | if (pdn->eeh_pe_config_addr) | |
852 | config_addr = pdn->eeh_pe_config_addr; | |
853 | ||
21e464dd | 854 | rc = rtas_call(ibm_configure_bridge,3,1, NULL, |
fcb7543e | 855 | config_addr, |
8b553f32 LV |
856 | BUID_HI(pdn->phb->buid), |
857 | BUID_LO(pdn->phb->buid)); | |
858 | if (rc) { | |
859 | printk (KERN_WARNING "EEH: Unable to configure device bridge (%d) for %s\n", | |
860 | rc, pdn->node->full_name); | |
861 | } | |
862 | } | |
863 | ||
172ca926 LV |
864 | /* ------------------------------------------------------------- */ |
865 | /* The code below deals with enabling EEH for devices during the | |
866 | * early boot sequence. EEH must be enabled before any PCI probing | |
867 | * can be done. | |
868 | */ | |
869 | ||
870 | #define EEH_ENABLE 1 | |
871 | ||
1da177e4 LT |
872 | struct eeh_early_enable_info { |
873 | unsigned int buid_hi; | |
874 | unsigned int buid_lo; | |
875 | }; | |
876 | ||
147d6a37 LV |
877 | static int get_pe_addr (int config_addr, |
878 | struct eeh_early_enable_info *info) | |
879 | { | |
880 | unsigned int rets[3]; | |
881 | int ret; | |
882 | ||
883 | /* Use latest config-addr token on power6 */ | |
884 | if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) { | |
885 | /* Make sure we have a PE in hand */ | |
886 | ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets, | |
887 | config_addr, info->buid_hi, info->buid_lo, 1); | |
888 | if (ret || (rets[0]==0)) | |
889 | return 0; | |
890 | ||
891 | ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets, | |
892 | config_addr, info->buid_hi, info->buid_lo, 0); | |
893 | if (ret) | |
894 | return 0; | |
895 | return rets[0]; | |
896 | } | |
897 | ||
898 | /* Use older config-addr token on power5 */ | |
899 | if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) { | |
900 | ret = rtas_call (ibm_get_config_addr_info, 4, 2, rets, | |
901 | config_addr, info->buid_hi, info->buid_lo, 0); | |
902 | if (ret) | |
903 | return 0; | |
904 | return rets[0]; | |
905 | } | |
906 | return 0; | |
907 | } | |
908 | ||
1da177e4 LT |
909 | /* Enable eeh for the given device node. */ |
910 | static void *early_enable_eeh(struct device_node *dn, void *data) | |
911 | { | |
25c4a46f | 912 | unsigned int rets[3]; |
1da177e4 LT |
913 | struct eeh_early_enable_info *info = data; |
914 | int ret; | |
e2eb6392 SR |
915 | const char *status = of_get_property(dn, "status", NULL); |
916 | const u32 *class_code = of_get_property(dn, "class-code", NULL); | |
917 | const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL); | |
918 | const u32 *device_id = of_get_property(dn, "device-id", NULL); | |
954a46e2 | 919 | const u32 *regs; |
1da177e4 | 920 | int enable; |
69376502 | 921 | struct pci_dn *pdn = PCI_DN(dn); |
1da177e4 | 922 | |
0f17574a | 923 | pdn->class_code = 0; |
1635317f | 924 | pdn->eeh_mode = 0; |
5c1344e9 LV |
925 | pdn->eeh_check_count = 0; |
926 | pdn->eeh_freeze_count = 0; | |
858955bd | 927 | pdn->eeh_false_positives = 0; |
1da177e4 LT |
928 | |
929 | if (status && strcmp(status, "ok") != 0) | |
930 | return NULL; /* ignore devices with bad status */ | |
931 | ||
932 | /* Ignore bad nodes. */ | |
933 | if (!class_code || !vendor_id || !device_id) | |
934 | return NULL; | |
935 | ||
936 | /* There is nothing to check on PCI to ISA bridges */ | |
937 | if (dn->type && !strcmp(dn->type, "isa")) { | |
1635317f | 938 | pdn->eeh_mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
939 | return NULL; |
940 | } | |
0f17574a | 941 | pdn->class_code = *class_code; |
1da177e4 LT |
942 | |
943 | /* | |
944 | * Now decide if we are going to "Disable" EEH checking | |
945 | * for this device. We still run with the EEH hardware active, | |
946 | * but we won't be checking for ff's. This means a driver | |
947 | * could return bad data (very bad!), an interrupt handler could | |
948 | * hang waiting on status bits that won't change, etc. | |
949 | * But there are a few cases like display devices that make sense. | |
950 | */ | |
951 | enable = 1; /* i.e. we will do checking */ | |
77bd7415 | 952 | #if 0 |
1da177e4 LT |
953 | if ((*class_code >> 16) == PCI_BASE_CLASS_DISPLAY) |
954 | enable = 0; | |
77bd7415 | 955 | #endif |
1da177e4 LT |
956 | |
957 | if (!enable) | |
1635317f | 958 | pdn->eeh_mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
959 | |
960 | /* Ok... see if this device supports EEH. Some do, some don't, | |
961 | * and the only way to find out is to check each and every one. */ | |
e2eb6392 | 962 | regs = of_get_property(dn, "reg", NULL); |
1da177e4 LT |
963 | if (regs) { |
964 | /* First register entry is addr (00BBSS00) */ | |
965 | /* Try to enable eeh */ | |
966 | ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL, | |
172ca926 LV |
967 | regs[0], info->buid_hi, info->buid_lo, |
968 | EEH_ENABLE); | |
969 | ||
25c4a46f | 970 | enable = 0; |
1da177e4 | 971 | if (ret == 0) { |
1635317f | 972 | pdn->eeh_config_addr = regs[0]; |
25e591f6 LV |
973 | |
974 | /* If the newer, better, ibm,get-config-addr-info is supported, | |
975 | * then use that instead. */ | |
147d6a37 | 976 | pdn->eeh_pe_config_addr = get_pe_addr(pdn->eeh_config_addr, info); |
25c4a46f LV |
977 | |
978 | /* Some older systems (Power4) allow the | |
979 | * ibm,set-eeh-option call to succeed even on nodes | |
980 | * where EEH is not supported. Verify support | |
981 | * explicitly. */ | |
982 | ret = read_slot_reset_state(pdn, rets); | |
983 | if ((ret == 0) && (rets[1] == 1)) | |
984 | enable = 1; | |
985 | } | |
986 | ||
987 | if (enable) { | |
988 | eeh_subsystem_enabled = 1; | |
989 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; | |
990 | ||
1da177e4 | 991 | #ifdef DEBUG |
25e591f6 LV |
992 | printk(KERN_DEBUG "EEH: %s: eeh enabled, config=%x pe_config=%x\n", |
993 | dn->full_name, pdn->eeh_config_addr, pdn->eeh_pe_config_addr); | |
1da177e4 LT |
994 | #endif |
995 | } else { | |
996 | ||
997 | /* This device doesn't support EEH, but it may have an | |
998 | * EEH parent, in which case we mark it as supported. */ | |
69376502 | 999 | if (dn->parent && PCI_DN(dn->parent) |
1635317f | 1000 | && (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) { |
1da177e4 | 1001 | /* Parent supports EEH. */ |
1635317f PM |
1002 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; |
1003 | pdn->eeh_config_addr = PCI_DN(dn->parent)->eeh_config_addr; | |
1da177e4 LT |
1004 | return NULL; |
1005 | } | |
1006 | } | |
1007 | } else { | |
1008 | printk(KERN_WARNING "EEH: %s: unable to get reg property.\n", | |
1009 | dn->full_name); | |
1010 | } | |
1011 | ||
7684b40c | 1012 | eeh_save_bars(pdn); |
69376502 | 1013 | return NULL; |
1da177e4 LT |
1014 | } |
1015 | ||
1016 | /* | |
1017 | * Initialize EEH by trying to enable it for all of the adapters in the system. | |
1018 | * As a side effect we can determine here if eeh is supported at all. | |
1019 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
1020 | * check. If a user turns off EEH for a particular adapter they are really | |
1021 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
1022 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
1023 | * EEH for all slots/all devices. | |
1024 | * | |
1025 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
1026 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
1027 | * newer systems can boot. | |
1028 | */ | |
1029 | void __init eeh_init(void) | |
1030 | { | |
1031 | struct device_node *phb, *np; | |
1032 | struct eeh_early_enable_info info; | |
1033 | ||
fd761fd8 | 1034 | spin_lock_init(&confirm_error_lock); |
df7242b1 LV |
1035 | spin_lock_init(&slot_errbuf_lock); |
1036 | ||
1da177e4 LT |
1037 | np = of_find_node_by_path("/rtas"); |
1038 | if (np == NULL) | |
1039 | return; | |
1040 | ||
1041 | ibm_set_eeh_option = rtas_token("ibm,set-eeh-option"); | |
1042 | ibm_set_slot_reset = rtas_token("ibm,set-slot-reset"); | |
1043 | ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2"); | |
1044 | ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state"); | |
1045 | ibm_slot_error_detail = rtas_token("ibm,slot-error-detail"); | |
25e591f6 | 1046 | ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info"); |
147d6a37 | 1047 | ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2"); |
21e464dd | 1048 | ibm_configure_bridge = rtas_token ("ibm,configure-bridge"); |
1da177e4 LT |
1049 | |
1050 | if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) | |
1051 | return; | |
1052 | ||
1053 | eeh_error_buf_size = rtas_token("rtas-error-log-max"); | |
1054 | if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) { | |
1055 | eeh_error_buf_size = 1024; | |
1056 | } | |
1057 | if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) { | |
1058 | printk(KERN_WARNING "EEH: rtas-error-log-max is bigger than allocated " | |
1059 | "buffer ! (%d vs %d)", eeh_error_buf_size, RTAS_ERROR_LOG_MAX); | |
1060 | eeh_error_buf_size = RTAS_ERROR_LOG_MAX; | |
1061 | } | |
1062 | ||
1063 | /* Enable EEH for all adapters. Note that eeh requires buid's */ | |
1064 | for (phb = of_find_node_by_name(NULL, "pci"); phb; | |
1065 | phb = of_find_node_by_name(phb, "pci")) { | |
1066 | unsigned long buid; | |
1067 | ||
1068 | buid = get_phb_buid(phb); | |
69376502 | 1069 | if (buid == 0 || PCI_DN(phb) == NULL) |
1da177e4 LT |
1070 | continue; |
1071 | ||
1072 | info.buid_lo = BUID_LO(buid); | |
1073 | info.buid_hi = BUID_HI(buid); | |
1074 | traverse_pci_devices(phb, early_enable_eeh, &info); | |
1075 | } | |
1076 | ||
1077 | if (eeh_subsystem_enabled) | |
1078 | printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n"); | |
1079 | else | |
1080 | printk(KERN_WARNING "EEH: No capable adapters found\n"); | |
1081 | } | |
1082 | ||
1083 | /** | |
1084 | * eeh_add_device_early - enable EEH for the indicated device_node | |
1085 | * @dn: device node for which to set up EEH | |
1086 | * | |
1087 | * This routine must be used to perform EEH initialization for PCI | |
1088 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1089 | * This routine must be called before any i/o is performed to the | |
1090 | * adapter (inluding any config-space i/o). | |
1091 | * Whether this actually enables EEH or not for this device depends | |
1092 | * on the CEC architecture, type of the device, on earlier boot | |
1093 | * command-line arguments & etc. | |
1094 | */ | |
794e085e | 1095 | static void eeh_add_device_early(struct device_node *dn) |
1da177e4 LT |
1096 | { |
1097 | struct pci_controller *phb; | |
1098 | struct eeh_early_enable_info info; | |
1099 | ||
69376502 | 1100 | if (!dn || !PCI_DN(dn)) |
1da177e4 | 1101 | return; |
1635317f | 1102 | phb = PCI_DN(dn)->phb; |
f751f841 LV |
1103 | |
1104 | /* USB Bus children of PCI devices will not have BUID's */ | |
1105 | if (NULL == phb || 0 == phb->buid) | |
1da177e4 | 1106 | return; |
1da177e4 LT |
1107 | |
1108 | info.buid_hi = BUID_HI(phb->buid); | |
1109 | info.buid_lo = BUID_LO(phb->buid); | |
1110 | early_enable_eeh(dn, &info); | |
1111 | } | |
1da177e4 | 1112 | |
e2a296ee LV |
1113 | void eeh_add_device_tree_early(struct device_node *dn) |
1114 | { | |
1115 | struct device_node *sib; | |
1116 | for (sib = dn->child; sib; sib = sib->sibling) | |
1117 | eeh_add_device_tree_early(sib); | |
1118 | eeh_add_device_early(dn); | |
1119 | } | |
1120 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
1121 | ||
1da177e4 LT |
1122 | /** |
1123 | * eeh_add_device_late - perform EEH initialization for the indicated pci device | |
1124 | * @dev: pci device for which to set up EEH | |
1125 | * | |
1126 | * This routine must be used to complete EEH initialization for PCI | |
1127 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1128 | */ | |
794e085e | 1129 | static void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 1130 | { |
56b0fca3 | 1131 | struct device_node *dn; |
8b553f32 | 1132 | struct pci_dn *pdn; |
56b0fca3 | 1133 | |
1da177e4 LT |
1134 | if (!dev || !eeh_subsystem_enabled) |
1135 | return; | |
1136 | ||
1137 | #ifdef DEBUG | |
982245f0 | 1138 | printk(KERN_DEBUG "EEH: adding device %s\n", pci_name(dev)); |
1da177e4 LT |
1139 | #endif |
1140 | ||
56b0fca3 LV |
1141 | pci_dev_get (dev); |
1142 | dn = pci_device_to_OF_node(dev); | |
8b553f32 LV |
1143 | pdn = PCI_DN(dn); |
1144 | pdn->pcidev = dev; | |
56b0fca3 | 1145 | |
e1d04c97 LV |
1146 | pci_addr_cache_insert_device(dev); |
1147 | eeh_sysfs_add_device(dev); | |
1da177e4 | 1148 | } |
794e085e NF |
1149 | |
1150 | void eeh_add_device_tree_late(struct pci_bus *bus) | |
1151 | { | |
1152 | struct pci_dev *dev; | |
1153 | ||
1154 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1155 | eeh_add_device_late(dev); | |
1156 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1157 | struct pci_bus *subbus = dev->subordinate; | |
1158 | if (subbus) | |
1159 | eeh_add_device_tree_late(subbus); | |
1160 | } | |
1161 | } | |
1162 | } | |
1163 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 LT |
1164 | |
1165 | /** | |
1166 | * eeh_remove_device - undo EEH setup for the indicated pci device | |
1167 | * @dev: pci device to be removed | |
1168 | * | |
794e085e NF |
1169 | * This routine should be called when a device is removed from |
1170 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
1171 | * the PCI device from the EEH subsystem. I/O errors affecting | |
1172 | * this device will no longer be detected after this call; thus, | |
1173 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 1174 | */ |
794e085e | 1175 | static void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 1176 | { |
56b0fca3 | 1177 | struct device_node *dn; |
1da177e4 LT |
1178 | if (!dev || !eeh_subsystem_enabled) |
1179 | return; | |
1180 | ||
1181 | /* Unregister the device with the EEH/PCI address search system */ | |
1182 | #ifdef DEBUG | |
982245f0 | 1183 | printk(KERN_DEBUG "EEH: remove device %s\n", pci_name(dev)); |
1da177e4 LT |
1184 | #endif |
1185 | pci_addr_cache_remove_device(dev); | |
e1d04c97 | 1186 | eeh_sysfs_remove_device(dev); |
56b0fca3 LV |
1187 | |
1188 | dn = pci_device_to_OF_node(dev); | |
b055a9e1 LV |
1189 | if (PCI_DN(dn)->pcidev) { |
1190 | PCI_DN(dn)->pcidev = NULL; | |
1191 | pci_dev_put (dev); | |
1192 | } | |
1da177e4 | 1193 | } |
1da177e4 | 1194 | |
e2a296ee LV |
1195 | void eeh_remove_bus_device(struct pci_dev *dev) |
1196 | { | |
794e085e NF |
1197 | struct pci_bus *bus = dev->subordinate; |
1198 | struct pci_dev *child, *tmp; | |
1199 | ||
e2a296ee | 1200 | eeh_remove_device(dev); |
794e085e NF |
1201 | |
1202 | if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1203 | list_for_each_entry_safe(child, tmp, &bus->devices, bus_list) | |
1204 | eeh_remove_bus_device(child); | |
e2a296ee LV |
1205 | } |
1206 | } | |
1207 | EXPORT_SYMBOL_GPL(eeh_remove_bus_device); | |
1208 | ||
1da177e4 LT |
1209 | static int proc_eeh_show(struct seq_file *m, void *v) |
1210 | { | |
1da177e4 LT |
1211 | if (0 == eeh_subsystem_enabled) { |
1212 | seq_printf(m, "EEH Subsystem is globally disabled\n"); | |
257ffc64 | 1213 | seq_printf(m, "eeh_total_mmio_ffs=%ld\n", total_mmio_ffs); |
1da177e4 LT |
1214 | } else { |
1215 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 LV |
1216 | seq_printf(m, |
1217 | "no device=%ld\n" | |
1218 | "no device node=%ld\n" | |
1219 | "no config address=%ld\n" | |
1220 | "check not wanted=%ld\n" | |
1221 | "eeh_total_mmio_ffs=%ld\n" | |
1222 | "eeh_false_positives=%ld\n" | |
177bc936 | 1223 | "eeh_slot_resets=%ld\n", |
257ffc64 LV |
1224 | no_device, no_dn, no_cfg_addr, |
1225 | ignored_check, total_mmio_ffs, | |
42253a68 | 1226 | false_positives, |
257ffc64 | 1227 | slot_resets); |
1da177e4 LT |
1228 | } |
1229 | ||
1230 | return 0; | |
1231 | } | |
1232 | ||
1233 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1234 | { | |
1235 | return single_open(file, proc_eeh_show, NULL); | |
1236 | } | |
1237 | ||
5dfe4c96 | 1238 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1239 | .open = proc_eeh_open, |
1240 | .read = seq_read, | |
1241 | .llseek = seq_lseek, | |
1242 | .release = single_release, | |
1243 | }; | |
1244 | ||
1245 | static int __init eeh_init_proc(void) | |
1246 | { | |
1247 | struct proc_dir_entry *e; | |
1248 | ||
e8222502 | 1249 | if (machine_is(pseries)) { |
1da177e4 LT |
1250 | e = create_proc_entry("ppc64/eeh", 0, NULL); |
1251 | if (e) | |
1252 | e->proc_fops = &proc_eeh_operations; | |
1253 | } | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | __initcall(eeh_init_proc); |