Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3c8c90ab LV |
2 | * Copyright IBM Corporation 2001, 2005, 2006 |
3 | * Copyright Dave Engebretsen & Todd Inglett 2001 | |
4 | * Copyright Linas Vepstas 2005, 2006 | |
cb3bc9d0 | 5 | * Copyright 2001-2012 IBM Corporation. |
69376502 | 6 | * |
1da177e4 LT |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
69376502 | 11 | * |
1da177e4 LT |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
69376502 | 16 | * |
1da177e4 LT |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
3c8c90ab LV |
20 | * |
21 | * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> | |
1da177e4 LT |
22 | */ |
23 | ||
6dee3fb9 | 24 | #include <linux/delay.h> |
cb3bc9d0 | 25 | #include <linux/sched.h> |
1da177e4 LT |
26 | #include <linux/init.h> |
27 | #include <linux/list.h> | |
1da177e4 LT |
28 | #include <linux/pci.h> |
29 | #include <linux/proc_fs.h> | |
30 | #include <linux/rbtree.h> | |
31 | #include <linux/seq_file.h> | |
32 | #include <linux/spinlock.h> | |
66b15db6 | 33 | #include <linux/export.h> |
acaa6176 SR |
34 | #include <linux/of.h> |
35 | ||
60063497 | 36 | #include <linux/atomic.h> |
1da177e4 | 37 | #include <asm/eeh.h> |
172ca926 | 38 | #include <asm/eeh_event.h> |
1da177e4 LT |
39 | #include <asm/io.h> |
40 | #include <asm/machdep.h> | |
172ca926 | 41 | #include <asm/ppc-pci.h> |
1da177e4 | 42 | #include <asm/rtas.h> |
1da177e4 | 43 | |
1da177e4 LT |
44 | |
45 | /** Overview: | |
46 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
47 | * dealing with PCI bus errors that can't be dealt with within the | |
48 | * usual PCI framework, except by check-stopping the CPU. Systems | |
49 | * that are designed for high-availability/reliability cannot afford | |
50 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
51 | * An EEH-capable bridge operates by converting a detected error | |
52 | * into a "slot freeze", taking the PCI adapter off-line, making | |
53 | * the slot behave, from the OS'es point of view, as if the slot | |
54 | * were "empty": all reads return 0xff's and all writes are silently | |
55 | * ignored. EEH slot isolation events can be triggered by parity | |
56 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
57 | * which in turn might be caused by low voltage on the bus, dust, |
58 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
59 | * |
60 | * Note, however, that one of the leading causes of EEH slot | |
61 | * freeze events are buggy device drivers, buggy device microcode, | |
62 | * or buggy device hardware. This is because any attempt by the | |
63 | * device to bus-master data to a memory address that is not | |
64 | * assigned to the device will trigger a slot freeze. (The idea | |
65 | * is to prevent devices-gone-wild from corrupting system memory). | |
66 | * Buggy hardware/drivers will have a miserable time co-existing | |
67 | * with EEH. | |
68 | * | |
69 | * Ideally, a PCI device driver, when suspecting that an isolation | |
25985edc | 70 | * event has occurred (e.g. by reading 0xff's), will then ask EEH |
1da177e4 LT |
71 | * whether this is the case, and then take appropriate steps to |
72 | * reset the PCI slot, the PCI device, and then resume operations. | |
73 | * However, until that day, the checking is done here, with the | |
74 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
75 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
76 | * and sent out for processing. | |
77 | */ | |
78 | ||
5c1344e9 | 79 | /* If a device driver keeps reading an MMIO register in an interrupt |
f36c5227 MM |
80 | * handler after a slot isolation event, it might be broken. |
81 | * This sets the threshold for how many read attempts we allow | |
82 | * before printing an error message. | |
1da177e4 | 83 | */ |
2fd30be8 | 84 | #define EEH_MAX_FAILS 2100000 |
1da177e4 | 85 | |
17213c3b | 86 | /* Time to wait for a PCI slot to report status, in milliseconds */ |
9c547768 LV |
87 | #define PCI_BUS_RESET_WAIT_MSEC (60*1000) |
88 | ||
aa1e6374 GS |
89 | /* Platform dependent EEH operations */ |
90 | struct eeh_ops *eeh_ops = NULL; | |
91 | ||
1e28a7dd DW |
92 | int eeh_subsystem_enabled; |
93 | EXPORT_SYMBOL(eeh_subsystem_enabled); | |
1da177e4 | 94 | |
fd761fd8 | 95 | /* Lock to avoid races due to multiple reports of an error */ |
3d372628 | 96 | static DEFINE_RAW_SPINLOCK(confirm_error_lock); |
fd761fd8 | 97 | |
17213c3b LV |
98 | /* Buffer for reporting pci register dumps. Its here in BSS, and |
99 | * not dynamically alloced, so that it ends up in RMO where RTAS | |
100 | * can access it. | |
101 | */ | |
d99bb1db LV |
102 | #define EEH_PCI_REGS_LOG_LEN 4096 |
103 | static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; | |
104 | ||
1da177e4 | 105 | /* System monitoring statistics */ |
257ffc64 LV |
106 | static unsigned long no_device; |
107 | static unsigned long no_dn; | |
108 | static unsigned long no_cfg_addr; | |
109 | static unsigned long ignored_check; | |
110 | static unsigned long total_mmio_ffs; | |
111 | static unsigned long false_positives; | |
257ffc64 | 112 | static unsigned long slot_resets; |
1da177e4 | 113 | |
7684b40c LV |
114 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
115 | ||
d99bb1db | 116 | /** |
cce4b2d2 | 117 | * eeh_gather_pci_data - Copy assorted PCI config space registers to buff |
f631acd3 | 118 | * @edev: device to report data for |
d99bb1db LV |
119 | * @buf: point to buffer in which to log |
120 | * @len: amount of room in buffer | |
121 | * | |
122 | * This routine captures assorted PCI configuration space data, | |
123 | * and puts them into a buffer for RTAS error logging. | |
124 | */ | |
f631acd3 | 125 | static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len) |
d99bb1db | 126 | { |
f631acd3 GS |
127 | struct device_node *dn = eeh_dev_to_of_node(edev); |
128 | struct pci_dev *dev = eeh_dev_to_pci_dev(edev); | |
d99bb1db | 129 | u32 cfg; |
fcf9892b | 130 | int cap, i; |
d99bb1db LV |
131 | int n = 0; |
132 | ||
f631acd3 GS |
133 | n += scnprintf(buf+n, len-n, "%s\n", dn->full_name); |
134 | printk(KERN_WARNING "EEH: of node=%s\n", dn->full_name); | |
fcf9892b | 135 | |
f631acd3 | 136 | rtas_read_config(PCI_DN(dn), PCI_VENDOR_ID, 4, &cfg); |
fcf9892b LV |
137 | n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); |
138 | printk(KERN_WARNING "EEH: PCI device/vendor: %08x\n", cfg); | |
139 | ||
f631acd3 | 140 | rtas_read_config(PCI_DN(dn), PCI_COMMAND, 4, &cfg); |
d99bb1db | 141 | n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); |
fcf9892b LV |
142 | printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg); |
143 | ||
b37ceefe LV |
144 | if (!dev) { |
145 | printk(KERN_WARNING "EEH: no PCI device for this of node\n"); | |
146 | return n; | |
147 | } | |
148 | ||
0b9369f4 LV |
149 | /* Gather bridge-specific registers */ |
150 | if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) { | |
f631acd3 | 151 | rtas_read_config(PCI_DN(dn), PCI_SEC_STATUS, 2, &cfg); |
0b9369f4 LV |
152 | n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); |
153 | printk(KERN_WARNING "EEH: Bridge secondary status: %04x\n", cfg); | |
154 | ||
f631acd3 | 155 | rtas_read_config(PCI_DN(dn), PCI_BRIDGE_CONTROL, 2, &cfg); |
0b9369f4 LV |
156 | n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); |
157 | printk(KERN_WARNING "EEH: Bridge control: %04x\n", cfg); | |
158 | } | |
159 | ||
fcf9892b | 160 | /* Dump out the PCI-X command and status regs */ |
b37ceefe | 161 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
fcf9892b | 162 | if (cap) { |
f631acd3 | 163 | rtas_read_config(PCI_DN(dn), cap, 4, &cfg); |
fcf9892b LV |
164 | n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); |
165 | printk(KERN_WARNING "EEH: PCI-X cmd: %08x\n", cfg); | |
166 | ||
f631acd3 | 167 | rtas_read_config(PCI_DN(dn), cap+4, 4, &cfg); |
fcf9892b LV |
168 | n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); |
169 | printk(KERN_WARNING "EEH: PCI-X status: %08x\n", cfg); | |
170 | } | |
171 | ||
172 | /* If PCI-E capable, dump PCI-E cap 10, and the AER */ | |
b37ceefe | 173 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); |
fcf9892b LV |
174 | if (cap) { |
175 | n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); | |
176 | printk(KERN_WARNING | |
177 | "EEH: PCI-E capabilities and status follow:\n"); | |
178 | ||
179 | for (i=0; i<=8; i++) { | |
f631acd3 | 180 | rtas_read_config(PCI_DN(dn), cap+4*i, 4, &cfg); |
fcf9892b LV |
181 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
182 | printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg); | |
183 | } | |
184 | ||
b37ceefe | 185 | cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |
fcf9892b LV |
186 | if (cap) { |
187 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); | |
188 | printk(KERN_WARNING | |
189 | "EEH: PCI-E AER capability register set follows:\n"); | |
190 | ||
191 | for (i=0; i<14; i++) { | |
f631acd3 | 192 | rtas_read_config(PCI_DN(dn), cap+4*i, 4, &cfg); |
fcf9892b LV |
193 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
194 | printk(KERN_WARNING "EEH: PCI-E AER %02x: %08x\n", i, cfg); | |
195 | } | |
196 | } | |
197 | } | |
0b9369f4 LV |
198 | |
199 | /* Gather status on devices under the bridge */ | |
200 | if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) { | |
f631acd3 | 201 | struct device_node *child; |
acaa6176 | 202 | |
f631acd3 GS |
203 | for_each_child_of_node(dn, child) { |
204 | if (of_node_to_eeh_dev(child)) | |
205 | n += eeh_gather_pci_data(of_node_to_eeh_dev(child), buf+n, len-n); | |
0b9369f4 LV |
206 | } |
207 | } | |
208 | ||
d99bb1db LV |
209 | return n; |
210 | } | |
211 | ||
cb3bc9d0 GS |
212 | /** |
213 | * eeh_slot_error_detail - Generate combined log including driver log and error log | |
f631acd3 | 214 | * @edev: device to report error log for |
cb3bc9d0 GS |
215 | * @severity: temporary or permanent error log |
216 | * | |
217 | * This routine should be called to generate the combined log, which | |
218 | * is comprised of driver log and error log. The driver log is figured | |
219 | * out from the config space of the corresponding PCI device, while | |
220 | * the error log is fetched through platform dependent function call. | |
221 | */ | |
f631acd3 | 222 | void eeh_slot_error_detail(struct eeh_dev *edev, int severity) |
d99bb1db LV |
223 | { |
224 | size_t loglen = 0; | |
17213c3b | 225 | pci_regs_buf[0] = 0; |
d99bb1db | 226 | |
f631acd3 GS |
227 | eeh_pci_enable(edev, EEH_OPT_THAW_MMIO); |
228 | eeh_ops->configure_bridge(eeh_dev_to_of_node(edev)); | |
229 | eeh_restore_bars(edev); | |
230 | loglen = eeh_gather_pci_data(edev, pci_regs_buf, EEH_PCI_REGS_LOG_LEN); | |
d99bb1db | 231 | |
f631acd3 | 232 | eeh_ops->get_log(eeh_dev_to_of_node(edev), severity, pci_regs_buf, loglen); |
d99bb1db LV |
233 | } |
234 | ||
1da177e4 | 235 | /** |
cb3bc9d0 GS |
236 | * eeh_token_to_phys - Convert EEH address token to phys address |
237 | * @token: I/O token, should be address in the form 0xA.... | |
238 | * | |
239 | * This routine should be called to convert virtual I/O address | |
240 | * to physical one. | |
1da177e4 LT |
241 | */ |
242 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
243 | { | |
244 | pte_t *ptep; | |
245 | unsigned long pa; | |
246 | ||
20cee16c | 247 | ptep = find_linux_pte(init_mm.pgd, token); |
1da177e4 LT |
248 | if (!ptep) |
249 | return token; | |
250 | pa = pte_pfn(*ptep) << PAGE_SHIFT; | |
251 | ||
252 | return pa | (token & (PAGE_SIZE-1)); | |
253 | } | |
254 | ||
cb3bc9d0 | 255 | /** |
cce4b2d2 | 256 | * eeh_find_device_pe - Retrieve the PE for the given device |
cb3bc9d0 GS |
257 | * @dn: device node |
258 | * | |
259 | * Return the PE under which this device lies | |
fd761fd8 | 260 | */ |
cce4b2d2 | 261 | struct device_node *eeh_find_device_pe(struct device_node *dn) |
fd761fd8 | 262 | { |
f631acd3 GS |
263 | while (dn->parent && of_node_to_eeh_dev(dn->parent) && |
264 | (of_node_to_eeh_dev(dn->parent)->mode & EEH_MODE_SUPPORTED)) { | |
fd761fd8 LV |
265 | dn = dn->parent; |
266 | } | |
267 | return dn; | |
268 | } | |
269 | ||
cb3bc9d0 GS |
270 | /** |
271 | * __eeh_mark_slot - Mark all child devices as failed | |
272 | * @parent: parent device | |
273 | * @mode_flag: failure flag | |
274 | * | |
275 | * Mark all devices that are children of this device as failed. | |
276 | * Mark the device driver too, so that it can see the failure | |
277 | * immediately; this is critical, since some drivers poll | |
278 | * status registers in interrupts ... If a driver is polling, | |
279 | * and the slot is frozen, then the driver can deadlock in | |
280 | * an interrupt context, which is bad. | |
fd761fd8 | 281 | */ |
acaa6176 | 282 | static void __eeh_mark_slot(struct device_node *parent, int mode_flag) |
fd761fd8 | 283 | { |
acaa6176 SR |
284 | struct device_node *dn; |
285 | ||
286 | for_each_child_of_node(parent, dn) { | |
f631acd3 | 287 | if (of_node_to_eeh_dev(dn)) { |
77bd7415 | 288 | /* Mark the pci device driver too */ |
f631acd3 | 289 | struct pci_dev *dev = of_node_to_eeh_dev(dn)->pdev; |
ea183a95 | 290 | |
f631acd3 | 291 | of_node_to_eeh_dev(dn)->mode |= mode_flag; |
ea183a95 | 292 | |
77bd7415 LV |
293 | if (dev && dev->driver) |
294 | dev->error_state = pci_channel_io_frozen; | |
295 | ||
acaa6176 | 296 | __eeh_mark_slot(dn, mode_flag); |
d9564ad1 | 297 | } |
fd761fd8 LV |
298 | } |
299 | } | |
300 | ||
cb3bc9d0 GS |
301 | /** |
302 | * eeh_mark_slot - Mark the indicated device and its children as failed | |
303 | * @dn: parent device | |
304 | * @mode_flag: failure flag | |
305 | * | |
306 | * Mark the indicated device and its child devices as failed. | |
307 | * The device drivers are marked as failed as well. | |
308 | */ | |
309 | void eeh_mark_slot(struct device_node *dn, int mode_flag) | |
d9564ad1 | 310 | { |
022d51b1 | 311 | struct pci_dev *dev; |
cce4b2d2 | 312 | dn = eeh_find_device_pe(dn); |
3914ac7b LV |
313 | |
314 | /* Back up one, since config addrs might be shared */ | |
f631acd3 | 315 | if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent)) |
3914ac7b LV |
316 | dn = dn->parent; |
317 | ||
f631acd3 | 318 | of_node_to_eeh_dev(dn)->mode |= mode_flag; |
022d51b1 LV |
319 | |
320 | /* Mark the pci device too */ | |
f631acd3 | 321 | dev = of_node_to_eeh_dev(dn)->pdev; |
022d51b1 LV |
322 | if (dev) |
323 | dev->error_state = pci_channel_io_frozen; | |
324 | ||
acaa6176 | 325 | __eeh_mark_slot(dn, mode_flag); |
d9564ad1 LV |
326 | } |
327 | ||
cb3bc9d0 GS |
328 | /** |
329 | * __eeh_clear_slot - Clear failure flag for the child devices | |
330 | * @parent: parent device | |
331 | * @mode_flag: flag to be cleared | |
332 | * | |
333 | * Clear failure flag for the child devices. | |
334 | */ | |
acaa6176 | 335 | static void __eeh_clear_slot(struct device_node *parent, int mode_flag) |
fd761fd8 | 336 | { |
acaa6176 SR |
337 | struct device_node *dn; |
338 | ||
339 | for_each_child_of_node(parent, dn) { | |
f631acd3 GS |
340 | if (of_node_to_eeh_dev(dn)) { |
341 | of_node_to_eeh_dev(dn)->mode &= ~mode_flag; | |
342 | of_node_to_eeh_dev(dn)->check_count = 0; | |
acaa6176 | 343 | __eeh_clear_slot(dn, mode_flag); |
d9564ad1 | 344 | } |
fd761fd8 LV |
345 | } |
346 | } | |
347 | ||
cb3bc9d0 GS |
348 | /** |
349 | * eeh_clear_slot - Clear failure flag for the indicated device and its children | |
350 | * @dn: parent device | |
351 | * @mode_flag: flag to be cleared | |
352 | * | |
353 | * Clear failure flag for the indicated device and its children. | |
354 | */ | |
355 | void eeh_clear_slot(struct device_node *dn, int mode_flag) | |
fd761fd8 LV |
356 | { |
357 | unsigned long flags; | |
3d372628 | 358 | raw_spin_lock_irqsave(&confirm_error_lock, flags); |
3914ac7b | 359 | |
cce4b2d2 | 360 | dn = eeh_find_device_pe(dn); |
3914ac7b LV |
361 | |
362 | /* Back up one, since config addrs might be shared */ | |
f631acd3 | 363 | if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent)) |
3914ac7b LV |
364 | dn = dn->parent; |
365 | ||
f631acd3 GS |
366 | of_node_to_eeh_dev(dn)->mode &= ~mode_flag; |
367 | of_node_to_eeh_dev(dn)->check_count = 0; | |
acaa6176 | 368 | __eeh_clear_slot(dn, mode_flag); |
3d372628 | 369 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); |
fd761fd8 LV |
370 | } |
371 | ||
1da177e4 | 372 | /** |
cb3bc9d0 GS |
373 | * eeh_dn_check_failure - Check if all 1's data is due to EEH slot freeze |
374 | * @dn: device node | |
375 | * @dev: pci device, if known | |
1da177e4 LT |
376 | * |
377 | * Check for an EEH failure for the given device node. Call this | |
378 | * routine if the result of a read was all 0xff's and you want to | |
379 | * find out if this is due to an EEH slot freeze. This routine | |
380 | * will query firmware for the EEH status. | |
381 | * | |
382 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 383 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
384 | * |
385 | * It is safe to call this routine in an interrupt context. | |
386 | */ | |
387 | int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev) | |
388 | { | |
389 | int ret; | |
1da177e4 | 390 | unsigned long flags; |
f631acd3 | 391 | struct eeh_dev *edev; |
fd761fd8 | 392 | int rc = 0; |
f36c5227 | 393 | const char *location; |
1da177e4 | 394 | |
257ffc64 | 395 | total_mmio_ffs++; |
1da177e4 LT |
396 | |
397 | if (!eeh_subsystem_enabled) | |
398 | return 0; | |
399 | ||
177bc936 | 400 | if (!dn) { |
257ffc64 | 401 | no_dn++; |
1da177e4 | 402 | return 0; |
177bc936 | 403 | } |
cce4b2d2 | 404 | dn = eeh_find_device_pe(dn); |
f631acd3 | 405 | edev = of_node_to_eeh_dev(dn); |
1da177e4 LT |
406 | |
407 | /* Access to IO BARs might get this far and still not want checking. */ | |
f631acd3 GS |
408 | if (!(edev->mode & EEH_MODE_SUPPORTED) || |
409 | edev->mode & EEH_MODE_NOCHECK) { | |
257ffc64 | 410 | ignored_check++; |
57b066ff | 411 | pr_debug("EEH: Ignored check (%x) for %s %s\n", |
f631acd3 | 412 | edev->mode, eeh_pci_name(dev), dn->full_name); |
1da177e4 LT |
413 | return 0; |
414 | } | |
415 | ||
f631acd3 | 416 | if (!edev->config_addr && !edev->pe_config_addr) { |
257ffc64 | 417 | no_cfg_addr++; |
1da177e4 LT |
418 | return 0; |
419 | } | |
420 | ||
fd761fd8 LV |
421 | /* If we already have a pending isolation event for this |
422 | * slot, we know it's bad already, we don't need to check. | |
423 | * Do this checking under a lock; as multiple PCI devices | |
424 | * in one slot might report errors simultaneously, and we | |
425 | * only want one error recovery routine running. | |
1da177e4 | 426 | */ |
3d372628 | 427 | raw_spin_lock_irqsave(&confirm_error_lock, flags); |
fd761fd8 | 428 | rc = 1; |
f631acd3 GS |
429 | if (edev->mode & EEH_MODE_ISOLATED) { |
430 | edev->check_count++; | |
431 | if (edev->check_count % EEH_MAX_FAILS == 0) { | |
f36c5227 | 432 | location = of_get_property(dn, "ibm,loc-code", NULL); |
cb3bc9d0 | 433 | printk(KERN_ERR "EEH: %d reads ignored for recovering device at " |
f36c5227 | 434 | "location=%s driver=%s pci addr=%s\n", |
f631acd3 | 435 | edev->check_count, location, |
778a785f | 436 | eeh_driver_name(dev), eeh_pci_name(dev)); |
cb3bc9d0 | 437 | printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n", |
778a785f | 438 | eeh_driver_name(dev)); |
5c1344e9 | 439 | dump_stack(); |
1da177e4 | 440 | } |
fd761fd8 | 441 | goto dn_unlock; |
1da177e4 LT |
442 | } |
443 | ||
444 | /* | |
445 | * Now test for an EEH failure. This is VERY expensive. | |
446 | * Note that the eeh_config_addr may be a parent device | |
447 | * in the case of a device behind a bridge, or it may be | |
448 | * function zero of a multi-function device. | |
449 | * In any case they must share a common PHB. | |
450 | */ | |
f631acd3 | 451 | ret = eeh_ops->get_state(dn, NULL); |
76e6faf7 | 452 | |
39d16e29 | 453 | /* Note that config-io to empty slots may fail; |
cb3bc9d0 | 454 | * they are empty when they don't have children. |
eb594a47 GS |
455 | * We will punt with the following conditions: Failure to get |
456 | * PE's state, EEH not support and Permanently unavailable | |
457 | * state, PE is in good state. | |
cb3bc9d0 | 458 | */ |
eb594a47 GS |
459 | if ((ret < 0) || |
460 | (ret == EEH_STATE_NOT_SUPPORT) || | |
461 | (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) == | |
462 | (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) { | |
257ffc64 | 463 | false_positives++; |
f631acd3 | 464 | edev->false_positives ++; |
fd761fd8 LV |
465 | rc = 0; |
466 | goto dn_unlock; | |
76e6faf7 LV |
467 | } |
468 | ||
257ffc64 | 469 | slot_resets++; |
fd761fd8 LV |
470 | |
471 | /* Avoid repeated reports of this failure, including problems | |
472 | * with other functions on this device, and functions under | |
cb3bc9d0 GS |
473 | * bridges. |
474 | */ | |
475 | eeh_mark_slot(dn, EEH_MODE_ISOLATED); | |
3d372628 | 476 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); |
1da177e4 | 477 | |
40a7cd92 | 478 | eeh_send_failure_event(edev); |
77bd7415 | 479 | |
1da177e4 LT |
480 | /* Most EEH events are due to device driver bugs. Having |
481 | * a stack trace will help the device-driver authors figure | |
cb3bc9d0 GS |
482 | * out what happened. So print that out. |
483 | */ | |
90375f53 | 484 | dump_stack(); |
fd761fd8 LV |
485 | return 1; |
486 | ||
487 | dn_unlock: | |
3d372628 | 488 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); |
fd761fd8 | 489 | return rc; |
1da177e4 LT |
490 | } |
491 | ||
fd761fd8 | 492 | EXPORT_SYMBOL_GPL(eeh_dn_check_failure); |
1da177e4 LT |
493 | |
494 | /** | |
cb3bc9d0 GS |
495 | * eeh_check_failure - Check if all 1's data is due to EEH slot freeze |
496 | * @token: I/O token, should be address in the form 0xA.... | |
497 | * @val: value, should be all 1's (XXX why do we need this arg??) | |
1da177e4 | 498 | * |
1da177e4 LT |
499 | * Check for an EEH failure at the given token address. Call this |
500 | * routine if the result of a read was all 0xff's and you want to | |
501 | * find out if this is due to an EEH slot freeze event. This routine | |
502 | * will query firmware for the EEH status. | |
503 | * | |
504 | * Note this routine is safe to call in an interrupt context. | |
505 | */ | |
506 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
507 | { | |
508 | unsigned long addr; | |
509 | struct pci_dev *dev; | |
510 | struct device_node *dn; | |
511 | ||
512 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
513 | addr = eeh_token_to_phys((unsigned long __force) token); | |
def9d83d | 514 | dev = pci_addr_cache_get_device(addr); |
177bc936 | 515 | if (!dev) { |
257ffc64 | 516 | no_device++; |
1da177e4 | 517 | return val; |
177bc936 | 518 | } |
1da177e4 LT |
519 | |
520 | dn = pci_device_to_OF_node(dev); | |
cb3bc9d0 | 521 | eeh_dn_check_failure(dn, dev); |
1da177e4 LT |
522 | |
523 | pci_dev_put(dev); | |
524 | return val; | |
525 | } | |
526 | ||
527 | EXPORT_SYMBOL(eeh_check_failure); | |
528 | ||
6dee3fb9 | 529 | |
47b5c838 | 530 | /** |
cce4b2d2 | 531 | * eeh_pci_enable - Enable MMIO or DMA transfers for this slot |
f631acd3 | 532 | * @edev: pci device node |
cb3bc9d0 GS |
533 | * |
534 | * This routine should be called to reenable frozen MMIO or DMA | |
535 | * so that it would work correctly again. It's useful while doing | |
536 | * recovery or log collection on the indicated device. | |
47b5c838 | 537 | */ |
f631acd3 | 538 | int eeh_pci_enable(struct eeh_dev *edev, int function) |
47b5c838 | 539 | { |
47b5c838 | 540 | int rc; |
f631acd3 | 541 | struct device_node *dn = eeh_dev_to_of_node(edev); |
47b5c838 | 542 | |
f631acd3 | 543 | rc = eeh_ops->set_option(dn, function); |
47b5c838 | 544 | if (rc) |
fa1be476 | 545 | printk(KERN_WARNING "EEH: Unexpected state change %d, err=%d dn=%s\n", |
f631acd3 | 546 | function, rc, dn->full_name); |
47b5c838 | 547 | |
f631acd3 | 548 | rc = eeh_ops->wait_state(dn, PCI_BUS_RESET_WAIT_MSEC); |
eb594a47 GS |
549 | if (rc > 0 && (rc & EEH_STATE_MMIO_ENABLED) && |
550 | (function == EEH_OPT_THAW_MMIO)) | |
fa1be476 LV |
551 | return 0; |
552 | ||
47b5c838 LV |
553 | return rc; |
554 | } | |
555 | ||
00c2ae35 BK |
556 | /** |
557 | * pcibios_set_pcie_slot_reset - Set PCI-E reset state | |
cb3bc9d0 GS |
558 | * @dev: pci device struct |
559 | * @state: reset state to enter | |
00c2ae35 BK |
560 | * |
561 | * Return value: | |
562 | * 0 if success | |
cb3bc9d0 | 563 | */ |
00c2ae35 BK |
564 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) |
565 | { | |
566 | struct device_node *dn = pci_device_to_OF_node(dev); | |
00c2ae35 BK |
567 | |
568 | switch (state) { | |
569 | case pcie_deassert_reset: | |
2652481f | 570 | eeh_ops->reset(dn, EEH_RESET_DEACTIVATE); |
00c2ae35 BK |
571 | break; |
572 | case pcie_hot_reset: | |
2652481f | 573 | eeh_ops->reset(dn, EEH_RESET_HOT); |
00c2ae35 BK |
574 | break; |
575 | case pcie_warm_reset: | |
2652481f | 576 | eeh_ops->reset(dn, EEH_RESET_FUNDAMENTAL); |
00c2ae35 BK |
577 | break; |
578 | default: | |
579 | return -EINVAL; | |
580 | }; | |
581 | ||
582 | return 0; | |
583 | } | |
584 | ||
cb5b5624 | 585 | /** |
cb3bc9d0 GS |
586 | * __eeh_set_pe_freset - Check the required reset for child devices |
587 | * @parent: parent device | |
588 | * @freset: return value | |
589 | * | |
590 | * Each device might have its preferred reset type: fundamental or | |
591 | * hot reset. The routine is used to collect the information from | |
592 | * the child devices so that they could be reset accordingly. | |
6dee3fb9 | 593 | */ |
cb3bc9d0 GS |
594 | void __eeh_set_pe_freset(struct device_node *parent, unsigned int *freset) |
595 | { | |
596 | struct device_node *dn; | |
597 | ||
598 | for_each_child_of_node(parent, dn) { | |
f631acd3 GS |
599 | if (of_node_to_eeh_dev(dn)) { |
600 | struct pci_dev *dev = of_node_to_eeh_dev(dn)->pdev; | |
cb3bc9d0 GS |
601 | |
602 | if (dev && dev->driver) | |
603 | *freset |= dev->needs_freset; | |
604 | ||
605 | __eeh_set_pe_freset(dn, freset); | |
606 | } | |
607 | } | |
608 | } | |
609 | ||
610 | /** | |
611 | * eeh_set_pe_freset - Check the required reset for the indicated device and its children | |
612 | * @dn: parent device | |
613 | * @freset: return value | |
614 | * | |
615 | * Each device might have its preferred reset type: fundamental or | |
616 | * hot reset. The routine is used to collected the information for | |
617 | * the indicated device and its children so that the bunch of the | |
618 | * devices could be reset properly. | |
619 | */ | |
620 | void eeh_set_pe_freset(struct device_node *dn, unsigned int *freset) | |
621 | { | |
622 | struct pci_dev *dev; | |
cce4b2d2 | 623 | dn = eeh_find_device_pe(dn); |
cb3bc9d0 GS |
624 | |
625 | /* Back up one, since config addrs might be shared */ | |
f631acd3 | 626 | if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent)) |
cb3bc9d0 | 627 | dn = dn->parent; |
6dee3fb9 | 628 | |
f631acd3 | 629 | dev = of_node_to_eeh_dev(dn)->pdev; |
cb3bc9d0 GS |
630 | if (dev) |
631 | *freset |= dev->needs_freset; | |
632 | ||
633 | __eeh_set_pe_freset(dn, freset); | |
634 | } | |
635 | ||
636 | /** | |
cce4b2d2 | 637 | * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second |
f631acd3 | 638 | * @edev: pci device node to be reset. |
cb3bc9d0 GS |
639 | * |
640 | * Assert the PCI #RST line for 1/4 second. | |
641 | */ | |
f631acd3 | 642 | static void eeh_reset_pe_once(struct eeh_dev *edev) |
6dee3fb9 | 643 | { |
308fc4f8 | 644 | unsigned int freset = 0; |
f631acd3 | 645 | struct device_node *dn = eeh_dev_to_of_node(edev); |
6e19314c | 646 | |
308fc4f8 RL |
647 | /* Determine type of EEH reset required for |
648 | * Partitionable Endpoint, a hot-reset (1) | |
649 | * or a fundamental reset (3). | |
650 | * A fundamental reset required by any device under | |
651 | * Partitionable Endpoint trumps hot-reset. | |
652 | */ | |
f631acd3 | 653 | eeh_set_pe_freset(dn, &freset); |
308fc4f8 RL |
654 | |
655 | if (freset) | |
f631acd3 | 656 | eeh_ops->reset(dn, EEH_RESET_FUNDAMENTAL); |
6e19314c | 657 | else |
f631acd3 | 658 | eeh_ops->reset(dn, EEH_RESET_HOT); |
6dee3fb9 LV |
659 | |
660 | /* The PCI bus requires that the reset be held high for at least | |
cb3bc9d0 GS |
661 | * a 100 milliseconds. We wait a bit longer 'just in case'. |
662 | */ | |
6dee3fb9 | 663 | #define PCI_BUS_RST_HOLD_TIME_MSEC 250 |
cb3bc9d0 | 664 | msleep(PCI_BUS_RST_HOLD_TIME_MSEC); |
d9564ad1 LV |
665 | |
666 | /* We might get hit with another EEH freeze as soon as the | |
667 | * pci slot reset line is dropped. Make sure we don't miss | |
cb3bc9d0 GS |
668 | * these, and clear the flag now. |
669 | */ | |
f631acd3 | 670 | eeh_clear_slot(dn, EEH_MODE_ISOLATED); |
d9564ad1 | 671 | |
f631acd3 | 672 | eeh_ops->reset(dn, EEH_RESET_DEACTIVATE); |
6dee3fb9 LV |
673 | |
674 | /* After a PCI slot has been reset, the PCI Express spec requires | |
675 | * a 1.5 second idle time for the bus to stabilize, before starting | |
cb3bc9d0 GS |
676 | * up traffic. |
677 | */ | |
6dee3fb9 | 678 | #define PCI_BUS_SETTLE_TIME_MSEC 1800 |
cb3bc9d0 | 679 | msleep(PCI_BUS_SETTLE_TIME_MSEC); |
e1029263 LV |
680 | } |
681 | ||
cb3bc9d0 | 682 | /** |
cce4b2d2 | 683 | * eeh_reset_pe - Reset the indicated PE |
f631acd3 | 684 | * @edev: PCI device associated EEH device |
cb3bc9d0 GS |
685 | * |
686 | * This routine should be called to reset indicated device, including | |
687 | * PE. A PE might include multiple PCI devices and sometimes PCI bridges | |
688 | * might be involved as well. | |
689 | */ | |
f631acd3 | 690 | int eeh_reset_pe(struct eeh_dev *edev) |
e1029263 LV |
691 | { |
692 | int i, rc; | |
f631acd3 | 693 | struct device_node *dn = eeh_dev_to_of_node(edev); |
e1029263 | 694 | |
9c547768 LV |
695 | /* Take three shots at resetting the bus */ |
696 | for (i=0; i<3; i++) { | |
f631acd3 | 697 | eeh_reset_pe_once(edev); |
6dee3fb9 | 698 | |
f631acd3 | 699 | rc = eeh_ops->wait_state(dn, PCI_BUS_RESET_WAIT_MSEC); |
eb594a47 | 700 | if (rc == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) |
b6495c0c | 701 | return 0; |
e1029263 | 702 | |
e1029263 | 703 | if (rc < 0) { |
12588da7 | 704 | printk(KERN_ERR "EEH: unrecoverable slot failure %s\n", |
f631acd3 | 705 | dn->full_name); |
b6495c0c | 706 | return -1; |
e1029263 | 707 | } |
12588da7 | 708 | printk(KERN_ERR "EEH: bus reset %d failed on slot %s, rc=%d\n", |
f631acd3 | 709 | i+1, dn->full_name, rc); |
6dee3fb9 | 710 | } |
b6495c0c | 711 | |
9c547768 | 712 | return -1; |
6dee3fb9 LV |
713 | } |
714 | ||
8b553f32 LV |
715 | /** Save and restore of PCI BARs |
716 | * | |
717 | * Although firmware will set up BARs during boot, it doesn't | |
718 | * set up device BAR's after a device reset, although it will, | |
719 | * if requested, set up bridge configuration. Thus, we need to | |
720 | * configure the PCI devices ourselves. | |
721 | */ | |
722 | ||
723 | /** | |
cce4b2d2 | 724 | * eeh_restore_one_device_bars - Restore the Base Address Registers for one device |
f631acd3 | 725 | * @edev: PCI device associated EEH device |
cb5b5624 | 726 | * |
8b553f32 LV |
727 | * Loads the PCI configuration space base address registers, |
728 | * the expansion ROM base address, the latency timer, and etc. | |
729 | * from the saved values in the device node. | |
730 | */ | |
f631acd3 | 731 | static inline void eeh_restore_one_device_bars(struct eeh_dev *edev) |
8b553f32 LV |
732 | { |
733 | int i; | |
cde274c0 | 734 | u32 cmd; |
f631acd3 GS |
735 | struct device_node *dn = eeh_dev_to_of_node(edev); |
736 | ||
737 | if (!edev->phb) | |
738 | return; | |
8b553f32 | 739 | |
8b553f32 | 740 | for (i=4; i<10; i++) { |
f631acd3 | 741 | rtas_write_config(PCI_DN(dn), i*4, 4, edev->config_space[i]); |
8b553f32 LV |
742 | } |
743 | ||
744 | /* 12 == Expansion ROM Address */ | |
f631acd3 | 745 | rtas_write_config(PCI_DN(dn), 12*4, 4, edev->config_space[12]); |
8b553f32 LV |
746 | |
747 | #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF)) | |
f631acd3 | 748 | #define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)]) |
8b553f32 | 749 | |
f631acd3 | 750 | rtas_write_config(PCI_DN(dn), PCI_CACHE_LINE_SIZE, 1, |
8b553f32 LV |
751 | SAVED_BYTE(PCI_CACHE_LINE_SIZE)); |
752 | ||
f631acd3 | 753 | rtas_write_config(PCI_DN(dn), PCI_LATENCY_TIMER, 1, |
8b553f32 LV |
754 | SAVED_BYTE(PCI_LATENCY_TIMER)); |
755 | ||
756 | /* max latency, min grant, interrupt pin and line */ | |
f631acd3 | 757 | rtas_write_config(PCI_DN(dn), 15*4, 4, edev->config_space[15]); |
cde274c0 MM |
758 | |
759 | /* Restore PERR & SERR bits, some devices require it, | |
cb3bc9d0 GS |
760 | * don't touch the other command bits |
761 | */ | |
f631acd3 GS |
762 | rtas_read_config(PCI_DN(dn), PCI_COMMAND, 4, &cmd); |
763 | if (edev->config_space[1] & PCI_COMMAND_PARITY) | |
cde274c0 MM |
764 | cmd |= PCI_COMMAND_PARITY; |
765 | else | |
766 | cmd &= ~PCI_COMMAND_PARITY; | |
f631acd3 | 767 | if (edev->config_space[1] & PCI_COMMAND_SERR) |
cde274c0 MM |
768 | cmd |= PCI_COMMAND_SERR; |
769 | else | |
770 | cmd &= ~PCI_COMMAND_SERR; | |
f631acd3 | 771 | rtas_write_config(PCI_DN(dn), PCI_COMMAND, 4, cmd); |
8b553f32 LV |
772 | } |
773 | ||
774 | /** | |
cb3bc9d0 | 775 | * eeh_restore_bars - Restore the PCI config space info |
f631acd3 | 776 | * @edev: EEH device |
8b553f32 LV |
777 | * |
778 | * This routine performs a recursive walk to the children | |
779 | * of this device as well. | |
780 | */ | |
f631acd3 | 781 | void eeh_restore_bars(struct eeh_dev *edev) |
8b553f32 LV |
782 | { |
783 | struct device_node *dn; | |
f631acd3 | 784 | if (!edev) |
8b553f32 LV |
785 | return; |
786 | ||
f631acd3 GS |
787 | if ((edev->mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(edev->class_code)) |
788 | eeh_restore_one_device_bars(edev); | |
8b553f32 | 789 | |
f631acd3 GS |
790 | for_each_child_of_node(eeh_dev_to_of_node(edev), dn) |
791 | eeh_restore_bars(of_node_to_eeh_dev(dn)); | |
8b553f32 LV |
792 | } |
793 | ||
794 | /** | |
cb3bc9d0 | 795 | * eeh_save_bars - Save device bars |
f631acd3 | 796 | * @edev: PCI device associated EEH device |
8b553f32 LV |
797 | * |
798 | * Save the values of the device bars. Unlike the restore | |
799 | * routine, this routine is *not* recursive. This is because | |
31116f0b | 800 | * PCI devices are added individually; but, for the restore, |
8b553f32 LV |
801 | * an entire slot is reset at a time. |
802 | */ | |
f631acd3 | 803 | static void eeh_save_bars(struct eeh_dev *edev) |
8b553f32 LV |
804 | { |
805 | int i; | |
f631acd3 | 806 | struct device_node *dn; |
8b553f32 | 807 | |
f631acd3 | 808 | if (!edev) |
8b553f32 | 809 | return; |
f631acd3 | 810 | dn = eeh_dev_to_of_node(edev); |
8b553f32 LV |
811 | |
812 | for (i = 0; i < 16; i++) | |
f631acd3 | 813 | rtas_read_config(PCI_DN(dn), i * 4, 4, &edev->config_space[i]); |
8b553f32 LV |
814 | } |
815 | ||
cb3bc9d0 | 816 | /** |
cce4b2d2 | 817 | * eeh_early_enable - Early enable EEH on the indicated device |
cb3bc9d0 GS |
818 | * @dn: device node |
819 | * @data: BUID | |
820 | * | |
821 | * Enable EEH functionality on the specified PCI device. The function | |
822 | * is expected to be called before real PCI probing is done. However, | |
823 | * the PHBs have been initialized at this point. | |
824 | */ | |
cce4b2d2 | 825 | static void *eeh_early_enable(struct device_node *dn, void *data) |
1da177e4 | 826 | { |
1da177e4 | 827 | int ret; |
e2eb6392 SR |
828 | const u32 *class_code = of_get_property(dn, "class-code", NULL); |
829 | const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL); | |
830 | const u32 *device_id = of_get_property(dn, "device-id", NULL); | |
954a46e2 | 831 | const u32 *regs; |
1da177e4 | 832 | int enable; |
f631acd3 | 833 | struct eeh_dev *edev = of_node_to_eeh_dev(dn); |
1da177e4 | 834 | |
f631acd3 GS |
835 | edev->class_code = 0; |
836 | edev->mode = 0; | |
837 | edev->check_count = 0; | |
838 | edev->freeze_count = 0; | |
839 | edev->false_positives = 0; | |
1da177e4 | 840 | |
c6d4d5a8 NL |
841 | if (!of_device_is_available(dn)) |
842 | return NULL; | |
1da177e4 LT |
843 | |
844 | /* Ignore bad nodes. */ | |
845 | if (!class_code || !vendor_id || !device_id) | |
846 | return NULL; | |
847 | ||
848 | /* There is nothing to check on PCI to ISA bridges */ | |
849 | if (dn->type && !strcmp(dn->type, "isa")) { | |
f631acd3 | 850 | edev->mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
851 | return NULL; |
852 | } | |
f631acd3 | 853 | edev->class_code = *class_code; |
1da177e4 | 854 | |
1da177e4 | 855 | /* Ok... see if this device supports EEH. Some do, some don't, |
cb3bc9d0 GS |
856 | * and the only way to find out is to check each and every one. |
857 | */ | |
e2eb6392 | 858 | regs = of_get_property(dn, "reg", NULL); |
1da177e4 LT |
859 | if (regs) { |
860 | /* First register entry is addr (00BBSS00) */ | |
861 | /* Try to enable eeh */ | |
8fb8f709 | 862 | ret = eeh_ops->set_option(dn, EEH_OPT_ENABLE); |
172ca926 | 863 | |
25c4a46f | 864 | enable = 0; |
1da177e4 | 865 | if (ret == 0) { |
f631acd3 | 866 | edev->config_addr = regs[0]; |
25e591f6 LV |
867 | |
868 | /* If the newer, better, ibm,get-config-addr-info is supported, | |
cb3bc9d0 GS |
869 | * then use that instead. |
870 | */ | |
f631acd3 | 871 | edev->pe_config_addr = eeh_ops->get_pe_addr(dn); |
25c4a46f LV |
872 | |
873 | /* Some older systems (Power4) allow the | |
874 | * ibm,set-eeh-option call to succeed even on nodes | |
875 | * where EEH is not supported. Verify support | |
cb3bc9d0 GS |
876 | * explicitly. |
877 | */ | |
f631acd3 | 878 | ret = eeh_ops->get_state(dn, NULL); |
eb594a47 | 879 | if (ret > 0 && ret != EEH_STATE_NOT_SUPPORT) |
25c4a46f LV |
880 | enable = 1; |
881 | } | |
882 | ||
883 | if (enable) { | |
884 | eeh_subsystem_enabled = 1; | |
f631acd3 | 885 | edev->mode |= EEH_MODE_SUPPORTED; |
25c4a46f | 886 | |
57b066ff | 887 | pr_debug("EEH: %s: eeh enabled, config=%x pe_config=%x\n", |
f631acd3 GS |
888 | dn->full_name, edev->config_addr, |
889 | edev->pe_config_addr); | |
1da177e4 LT |
890 | } else { |
891 | ||
892 | /* This device doesn't support EEH, but it may have an | |
cb3bc9d0 GS |
893 | * EEH parent, in which case we mark it as supported. |
894 | */ | |
f631acd3 GS |
895 | if (dn->parent && of_node_to_eeh_dev(dn->parent) && |
896 | (of_node_to_eeh_dev(dn->parent)->mode & EEH_MODE_SUPPORTED)) { | |
1da177e4 | 897 | /* Parent supports EEH. */ |
f631acd3 GS |
898 | edev->mode |= EEH_MODE_SUPPORTED; |
899 | edev->config_addr = of_node_to_eeh_dev(dn->parent)->config_addr; | |
1da177e4 LT |
900 | return NULL; |
901 | } | |
902 | } | |
903 | } else { | |
904 | printk(KERN_WARNING "EEH: %s: unable to get reg property.\n", | |
905 | dn->full_name); | |
906 | } | |
907 | ||
f631acd3 | 908 | eeh_save_bars(edev); |
69376502 | 909 | return NULL; |
1da177e4 LT |
910 | } |
911 | ||
aa1e6374 GS |
912 | /** |
913 | * eeh_ops_register - Register platform dependent EEH operations | |
914 | * @ops: platform dependent EEH operations | |
915 | * | |
916 | * Register the platform dependent EEH operation callback | |
917 | * functions. The platform should call this function before | |
918 | * any other EEH operations. | |
919 | */ | |
920 | int __init eeh_ops_register(struct eeh_ops *ops) | |
921 | { | |
922 | if (!ops->name) { | |
923 | pr_warning("%s: Invalid EEH ops name for %p\n", | |
924 | __func__, ops); | |
925 | return -EINVAL; | |
926 | } | |
927 | ||
928 | if (eeh_ops && eeh_ops != ops) { | |
929 | pr_warning("%s: EEH ops of platform %s already existing (%s)\n", | |
930 | __func__, eeh_ops->name, ops->name); | |
931 | return -EEXIST; | |
932 | } | |
933 | ||
934 | eeh_ops = ops; | |
935 | ||
936 | return 0; | |
937 | } | |
938 | ||
939 | /** | |
940 | * eeh_ops_unregister - Unreigster platform dependent EEH operations | |
941 | * @name: name of EEH platform operations | |
942 | * | |
943 | * Unregister the platform dependent EEH operation callback | |
944 | * functions. | |
945 | */ | |
946 | int __exit eeh_ops_unregister(const char *name) | |
947 | { | |
948 | if (!name || !strlen(name)) { | |
949 | pr_warning("%s: Invalid EEH ops name\n", | |
950 | __func__); | |
951 | return -EINVAL; | |
952 | } | |
953 | ||
954 | if (eeh_ops && !strcmp(eeh_ops->name, name)) { | |
955 | eeh_ops = NULL; | |
956 | return 0; | |
957 | } | |
958 | ||
959 | return -EEXIST; | |
960 | } | |
961 | ||
cb3bc9d0 GS |
962 | /** |
963 | * eeh_init - EEH initialization | |
964 | * | |
1da177e4 LT |
965 | * Initialize EEH by trying to enable it for all of the adapters in the system. |
966 | * As a side effect we can determine here if eeh is supported at all. | |
967 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
968 | * check. If a user turns off EEH for a particular adapter they are really | |
969 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
970 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
971 | * EEH for all slots/all devices. | |
972 | * | |
973 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
974 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
975 | * newer systems can boot. | |
976 | */ | |
977 | void __init eeh_init(void) | |
978 | { | |
979 | struct device_node *phb, *np; | |
e2af155c GS |
980 | int ret; |
981 | ||
982 | /* call platform initialization function */ | |
983 | if (!eeh_ops) { | |
984 | pr_warning("%s: Platform EEH operation not found\n", | |
985 | __func__); | |
986 | return; | |
987 | } else if ((ret = eeh_ops->init())) { | |
988 | pr_warning("%s: Failed to call platform init function (%d)\n", | |
989 | __func__, ret); | |
990 | return; | |
991 | } | |
1da177e4 | 992 | |
3d372628 | 993 | raw_spin_lock_init(&confirm_error_lock); |
df7242b1 | 994 | |
1da177e4 LT |
995 | np = of_find_node_by_path("/rtas"); |
996 | if (np == NULL) | |
997 | return; | |
998 | ||
1da177e4 LT |
999 | /* Enable EEH for all adapters. Note that eeh requires buid's */ |
1000 | for (phb = of_find_node_by_name(NULL, "pci"); phb; | |
1001 | phb = of_find_node_by_name(phb, "pci")) { | |
1002 | unsigned long buid; | |
1003 | ||
1004 | buid = get_phb_buid(phb); | |
f631acd3 | 1005 | if (buid == 0 || !of_node_to_eeh_dev(phb)) |
1da177e4 LT |
1006 | continue; |
1007 | ||
c8c29b38 | 1008 | traverse_pci_devices(phb, eeh_early_enable, NULL); |
1da177e4 LT |
1009 | } |
1010 | ||
1011 | if (eeh_subsystem_enabled) | |
1012 | printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n"); | |
1013 | else | |
1014 | printk(KERN_WARNING "EEH: No capable adapters found\n"); | |
1015 | } | |
1016 | ||
1017 | /** | |
cb3bc9d0 | 1018 | * eeh_add_device_early - Enable EEH for the indicated device_node |
1da177e4 LT |
1019 | * @dn: device node for which to set up EEH |
1020 | * | |
1021 | * This routine must be used to perform EEH initialization for PCI | |
1022 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1023 | * This routine must be called before any i/o is performed to the | |
1024 | * adapter (inluding any config-space i/o). | |
1025 | * Whether this actually enables EEH or not for this device depends | |
1026 | * on the CEC architecture, type of the device, on earlier boot | |
1027 | * command-line arguments & etc. | |
1028 | */ | |
794e085e | 1029 | static void eeh_add_device_early(struct device_node *dn) |
1da177e4 LT |
1030 | { |
1031 | struct pci_controller *phb; | |
1da177e4 | 1032 | |
f631acd3 | 1033 | if (!dn || !of_node_to_eeh_dev(dn)) |
1da177e4 | 1034 | return; |
f631acd3 | 1035 | phb = of_node_to_eeh_dev(dn)->phb; |
f751f841 LV |
1036 | |
1037 | /* USB Bus children of PCI devices will not have BUID's */ | |
1038 | if (NULL == phb || 0 == phb->buid) | |
1da177e4 | 1039 | return; |
1da177e4 | 1040 | |
c8c29b38 | 1041 | eeh_early_enable(dn, NULL); |
1da177e4 | 1042 | } |
1da177e4 | 1043 | |
cb3bc9d0 GS |
1044 | /** |
1045 | * eeh_add_device_tree_early - Enable EEH for the indicated device | |
1046 | * @dn: device node | |
1047 | * | |
1048 | * This routine must be used to perform EEH initialization for the | |
1049 | * indicated PCI device that was added after system boot (e.g. | |
1050 | * hotplug, dlpar). | |
1051 | */ | |
e2a296ee LV |
1052 | void eeh_add_device_tree_early(struct device_node *dn) |
1053 | { | |
1054 | struct device_node *sib; | |
acaa6176 SR |
1055 | |
1056 | for_each_child_of_node(dn, sib) | |
e2a296ee LV |
1057 | eeh_add_device_tree_early(sib); |
1058 | eeh_add_device_early(dn); | |
1059 | } | |
1060 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
1061 | ||
1da177e4 | 1062 | /** |
cb3bc9d0 | 1063 | * eeh_add_device_late - Perform EEH initialization for the indicated pci device |
1da177e4 LT |
1064 | * @dev: pci device for which to set up EEH |
1065 | * | |
1066 | * This routine must be used to complete EEH initialization for PCI | |
1067 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1068 | */ | |
794e085e | 1069 | static void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 1070 | { |
56b0fca3 | 1071 | struct device_node *dn; |
f631acd3 | 1072 | struct eeh_dev *edev; |
56b0fca3 | 1073 | |
1da177e4 LT |
1074 | if (!dev || !eeh_subsystem_enabled) |
1075 | return; | |
1076 | ||
57b066ff | 1077 | pr_debug("EEH: Adding device %s\n", pci_name(dev)); |
1da177e4 | 1078 | |
56b0fca3 | 1079 | dn = pci_device_to_OF_node(dev); |
f631acd3 GS |
1080 | edev = pci_dev_to_eeh_dev(dev); |
1081 | if (edev->pdev == dev) { | |
57b066ff BH |
1082 | pr_debug("EEH: Already referenced !\n"); |
1083 | return; | |
1084 | } | |
f631acd3 | 1085 | WARN_ON(edev->pdev); |
57b066ff | 1086 | |
cb3bc9d0 | 1087 | pci_dev_get(dev); |
f631acd3 GS |
1088 | edev->pdev = dev; |
1089 | dev->dev.archdata.edev = edev; | |
56b0fca3 | 1090 | |
e1d04c97 LV |
1091 | pci_addr_cache_insert_device(dev); |
1092 | eeh_sysfs_add_device(dev); | |
1da177e4 | 1093 | } |
794e085e | 1094 | |
cb3bc9d0 GS |
1095 | /** |
1096 | * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus | |
1097 | * @bus: PCI bus | |
1098 | * | |
1099 | * This routine must be used to perform EEH initialization for PCI | |
1100 | * devices which are attached to the indicated PCI bus. The PCI bus | |
1101 | * is added after system boot through hotplug or dlpar. | |
1102 | */ | |
794e085e NF |
1103 | void eeh_add_device_tree_late(struct pci_bus *bus) |
1104 | { | |
1105 | struct pci_dev *dev; | |
1106 | ||
1107 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1108 | eeh_add_device_late(dev); | |
1109 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1110 | struct pci_bus *subbus = dev->subordinate; | |
1111 | if (subbus) | |
1112 | eeh_add_device_tree_late(subbus); | |
1113 | } | |
1114 | } | |
1115 | } | |
1116 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 LT |
1117 | |
1118 | /** | |
cb3bc9d0 | 1119 | * eeh_remove_device - Undo EEH setup for the indicated pci device |
1da177e4 LT |
1120 | * @dev: pci device to be removed |
1121 | * | |
794e085e NF |
1122 | * This routine should be called when a device is removed from |
1123 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
1124 | * the PCI device from the EEH subsystem. I/O errors affecting | |
1125 | * this device will no longer be detected after this call; thus, | |
1126 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 1127 | */ |
794e085e | 1128 | static void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 1129 | { |
f631acd3 GS |
1130 | struct eeh_dev *edev; |
1131 | ||
1da177e4 LT |
1132 | if (!dev || !eeh_subsystem_enabled) |
1133 | return; | |
f631acd3 | 1134 | edev = pci_dev_to_eeh_dev(dev); |
1da177e4 LT |
1135 | |
1136 | /* Unregister the device with the EEH/PCI address search system */ | |
57b066ff | 1137 | pr_debug("EEH: Removing device %s\n", pci_name(dev)); |
56b0fca3 | 1138 | |
f631acd3 | 1139 | if (!edev || !edev->pdev) { |
57b066ff BH |
1140 | pr_debug("EEH: Not referenced !\n"); |
1141 | return; | |
b055a9e1 | 1142 | } |
f631acd3 GS |
1143 | edev->pdev = NULL; |
1144 | dev->dev.archdata.edev = NULL; | |
cb3bc9d0 | 1145 | pci_dev_put(dev); |
57b066ff BH |
1146 | |
1147 | pci_addr_cache_remove_device(dev); | |
1148 | eeh_sysfs_remove_device(dev); | |
1da177e4 | 1149 | } |
1da177e4 | 1150 | |
cb3bc9d0 GS |
1151 | /** |
1152 | * eeh_remove_bus_device - Undo EEH setup for the indicated PCI device | |
1153 | * @dev: PCI device | |
1154 | * | |
1155 | * This routine must be called when a device is removed from the | |
1156 | * running system through hotplug or dlpar. The corresponding | |
1157 | * PCI address cache will be removed. | |
1158 | */ | |
e2a296ee LV |
1159 | void eeh_remove_bus_device(struct pci_dev *dev) |
1160 | { | |
794e085e NF |
1161 | struct pci_bus *bus = dev->subordinate; |
1162 | struct pci_dev *child, *tmp; | |
1163 | ||
e2a296ee | 1164 | eeh_remove_device(dev); |
794e085e NF |
1165 | |
1166 | if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1167 | list_for_each_entry_safe(child, tmp, &bus->devices, bus_list) | |
1168 | eeh_remove_bus_device(child); | |
e2a296ee LV |
1169 | } |
1170 | } | |
1171 | EXPORT_SYMBOL_GPL(eeh_remove_bus_device); | |
1172 | ||
1da177e4 LT |
1173 | static int proc_eeh_show(struct seq_file *m, void *v) |
1174 | { | |
1da177e4 LT |
1175 | if (0 == eeh_subsystem_enabled) { |
1176 | seq_printf(m, "EEH Subsystem is globally disabled\n"); | |
257ffc64 | 1177 | seq_printf(m, "eeh_total_mmio_ffs=%ld\n", total_mmio_ffs); |
1da177e4 LT |
1178 | } else { |
1179 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 LV |
1180 | seq_printf(m, |
1181 | "no device=%ld\n" | |
1182 | "no device node=%ld\n" | |
1183 | "no config address=%ld\n" | |
1184 | "check not wanted=%ld\n" | |
1185 | "eeh_total_mmio_ffs=%ld\n" | |
1186 | "eeh_false_positives=%ld\n" | |
177bc936 | 1187 | "eeh_slot_resets=%ld\n", |
257ffc64 LV |
1188 | no_device, no_dn, no_cfg_addr, |
1189 | ignored_check, total_mmio_ffs, | |
42253a68 | 1190 | false_positives, |
257ffc64 | 1191 | slot_resets); |
1da177e4 LT |
1192 | } |
1193 | ||
1194 | return 0; | |
1195 | } | |
1196 | ||
1197 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1198 | { | |
1199 | return single_open(file, proc_eeh_show, NULL); | |
1200 | } | |
1201 | ||
5dfe4c96 | 1202 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1203 | .open = proc_eeh_open, |
1204 | .read = seq_read, | |
1205 | .llseek = seq_lseek, | |
1206 | .release = single_release, | |
1207 | }; | |
1208 | ||
1209 | static int __init eeh_init_proc(void) | |
1210 | { | |
66747138 | 1211 | if (machine_is(pseries)) |
8feaa434 | 1212 | proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations); |
1da177e4 LT |
1213 | return 0; |
1214 | } | |
1215 | __initcall(eeh_init_proc); |