[deliverable/linux.git] / arch / powerpc / platforms / pseries / eeh_cache.c

/*
 * PCI address cache; allows the lookup of PCI devices based on I/O address
 *
 * Copyright IBM Corporation 2004
 * Copyright Linas Vepstas <linas@austin.ibm.com> 2004
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/list.h>
#include <linux/pci.h>
#include <linux/rbtree.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/atomic.h>
#include <asm/pci-bridge.h>
#include <asm/ppc-pci.h>


/**
 * The pci address cache subsystem.  This subsystem places
 * PCI device address resources into a red-black tree, sorted
 * according to the address range, so that given only an i/o
 * address, the corresponding PCI device can be **quickly**
 * found. It is safe to perform an address lookup in an interrupt
 * context; this ability is an important feature.
 *
 * Currently, the only customer of this code is the EEH subsystem;
 * thus, this code has been somewhat tailored to suit EEH better.
 * In particular, the cache does *not* hold the addresses of devices
 * for which EEH is not enabled.
 *
 * (Implementation Note: The RB tree seems to be better/faster
 * than any hash algo I could think of for this problem, even
 * with the penalty of slow pointer chases for d-cache misses).
 */
struct pci_io_addr_range {
	struct rb_node rb_node;
	unsigned long addr_lo;
	unsigned long addr_hi;
	struct eeh_dev *edev;
	struct pci_dev *pcidev;
	unsigned int flags;
};

static struct pci_io_addr_cache {
	struct rb_root rb_root;
	spinlock_t piar_lock;
} pci_io_addr_cache_root;

static inline struct eeh_dev *__pci_addr_cache_get_device(unsigned long addr)
{
	struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node;

	while (n) {
		struct pci_io_addr_range *piar;
		piar = rb_entry(n, struct pci_io_addr_range, rb_node);

		if (addr < piar->addr_lo) {
			n = n->rb_left;
		} else {
			if (addr > piar->addr_hi) {
				n = n->rb_right;
			} else {
				pci_dev_get(piar->pcidev);
				return piar->edev;
			}
		}
	}

	return NULL;
}

/**
 * pci_addr_cache_get_device - Get device, given only address
 * @addr: mmio (PIO) phys address or i/o port number
 *
 * Given an mmio phys address, or a port number, find a pci device
 * that implements this address.  Be sure to pci_dev_put the device
 * when finished.  I/O port numbers are assumed to be offset
 * from zero (that is, they do *not* have pci_io_addr added in).
 * It is safe to call this function within an interrupt.
 */
struct eeh_dev *pci_addr_cache_get_device(unsigned long addr)
{
	struct eeh_dev *edev;
	unsigned long flags;

	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
	edev = __pci_addr_cache_get_device(addr);
	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
	return edev;
}

#ifdef DEBUG
/*
 * Handy-dandy debug print routine, does nothing more
 * than print out the contents of our addr cache.
 */
static void pci_addr_cache_print(struct pci_io_addr_cache *cache)
{
	struct rb_node *n;
	int cnt = 0;

	n = rb_first(&cache->rb_root);
	while (n) {
		struct pci_io_addr_range *piar;
		piar = rb_entry(n, struct pci_io_addr_range, rb_node);
		printk(KERN_DEBUG "PCI: %s addr range %d [%lx-%lx]: %s\n",
		       (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt,
		       piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev));
		cnt++;
		n = rb_next(n);
	}
}
#endif

/* Insert address range into the rb tree. */
static struct pci_io_addr_range *
pci_addr_cache_insert(struct pci_dev *dev, unsigned long alo,
		      unsigned long ahi, unsigned int flags)
{
	struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node;
	struct rb_node *parent = NULL;
	struct pci_io_addr_range *piar;

	/* Walk tree, find a place to insert into tree */
	while (*p) {
		parent = *p;
		piar = rb_entry(parent, struct pci_io_addr_range, rb_node);
		if (ahi < piar->addr_lo) {
			p = &parent->rb_left;
		} else if (alo > piar->addr_hi) {
			p = &parent->rb_right;
		} else {
			if (dev != piar->pcidev ||
			    alo != piar->addr_lo || ahi != piar->addr_hi) {
				printk(KERN_WARNING "PIAR: overlapping address range\n");
			}
			return piar;
		}
	}
	piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC);
	if (!piar)
		return NULL;

	pci_dev_get(dev);
	piar->addr_lo = alo;
	piar->addr_hi = ahi;
	piar->edev = pci_dev_to_eeh_dev(dev);
	piar->pcidev = dev;
	piar->flags = flags;

#ifdef DEBUG
	printk(KERN_DEBUG "PIAR: insert range=[%lx:%lx] dev=%s\n",
	                  alo, ahi, pci_name(dev));
#endif

	rb_link_node(&piar->rb_node, parent, p);
	rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root);

	return piar;
}

static void __pci_addr_cache_insert_device(struct pci_dev *dev)
{
	struct device_node *dn;
	struct eeh_dev *edev;
	int i;

	dn = pci_device_to_OF_node(dev);
	if (!dn) {
		printk(KERN_WARNING "PCI: no pci dn found for dev=%s\n", pci_name(dev));
		return;
	}

	edev = of_node_to_eeh_dev(dn);
	if (!edev) {
		pr_warning("PCI: no EEH dev found for dn=%s\n",
			dn->full_name);
		return;
	}

	/* Skip any devices for which EEH is not enabled. */
	if (!edev->pe) {
#ifdef DEBUG
		pr_info("PCI: skip building address cache for=%s - %s\n",
			pci_name(dev), dn->full_name);
#endif
		return;
	}

	/* Walk resources on this device, poke them into the tree */
	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
		unsigned long start = pci_resource_start(dev,i);
		unsigned long end = pci_resource_end(dev,i);
		unsigned int flags = pci_resource_flags(dev,i);

		/* We are interested only bus addresses, not dma or other stuff */
		if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if (start == 0 || ~start == 0 || end == 0 || ~end == 0)
			 continue;
		pci_addr_cache_insert(dev, start, end, flags);
	}
}

/**
 * pci_addr_cache_insert_device - Add a device to the address cache
 * @dev: PCI device whose I/O addresses we are interested in.
 *
 * In order to support the fast lookup of devices based on addresses,
 * we maintain a cache of devices that can be quickly searched.
 * This routine adds a device to that cache.
 */
void pci_addr_cache_insert_device(struct pci_dev *dev)
{
	unsigned long flags;

	/* Ignore PCI bridges */
	if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
		return;

	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
	__pci_addr_cache_insert_device(dev);
	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
}

static inline void __pci_addr_cache_remove_device(struct pci_dev *dev)
{
	struct rb_node *n;

restart:
	n = rb_first(&pci_io_addr_cache_root.rb_root);
	while (n) {
		struct pci_io_addr_range *piar;
		piar = rb_entry(n, struct pci_io_addr_range, rb_node);

		if (piar->pcidev == dev) {
			rb_erase(n, &pci_io_addr_cache_root.rb_root);
			pci_dev_put(piar->pcidev);
			kfree(piar);
			goto restart;
		}
		n = rb_next(n);
	}
}

/**
 * pci_addr_cache_remove_device - remove pci device from addr cache
 * @dev: device to remove
 *
 * Remove a device from the addr-cache tree.
 * This is potentially expensive, since it will walk
 * the tree multiple times (once per resource).
 * But so what; device removal doesn't need to be that fast.
 */
void pci_addr_cache_remove_device(struct pci_dev *dev)
{
	unsigned long flags;

	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
	__pci_addr_cache_remove_device(dev);
	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
}

/**
 * pci_addr_cache_build - Build a cache of I/O addresses
 *
 * Build a cache of pci i/o addresses.  This cache will be used to
 * find the pci device that corresponds to a given address.
 * This routine scans all pci busses to build the cache.
 * Must be run late in boot process, after the pci controllers
 * have been scanned for devices (after all device resources are known).
 */
void __init pci_addr_cache_build(void)
{
	struct device_node *dn;
	struct eeh_dev *edev;
	struct pci_dev *dev = NULL;

	spin_lock_init(&pci_io_addr_cache_root.piar_lock);

	for_each_pci_dev(dev) {
		pci_addr_cache_insert_device(dev);

		dn = pci_device_to_OF_node(dev);
		if (!dn)
			continue;

		edev = of_node_to_eeh_dev(dn);
		if (!edev)
			continue;

		pci_dev_get(dev);  /* matching put is in eeh_remove_device() */
		dev->dev.archdata.edev = edev;
		edev->pdev = dev;

		eeh_sysfs_add_device(dev);
	}

#ifdef DEBUG
	/* Verify tree built up above, echo back the list of addrs. */
	pci_addr_cache_print(&pci_io_addr_cache_root);
#endif
}
Commit	Line	Data
5d5a0936	1	/*
5d5a0936 LV	2	* PCI address cache; allows the lookup of PCI devices based on I/O address
5d5a0936 LV	3	*
3c8c90ab LV	4	* Copyright IBM Corporation 2004
3c8c90ab LV	5	* Copyright Linas Vepstas <linas@austin.ibm.com> 2004
5d5a0936 LV	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
	22	#include <linux/list.h>
	23	#include <linux/pci.h>
	24	#include <linux/rbtree.h>
5a0e3ad6	25	#include <linux/slab.h>
5d5a0936	26	#include <linux/spinlock.h>
60063497	27	#include <linux/atomic.h>
5d5a0936 LV	28	#include <asm/pci-bridge.h>
5d5a0936 LV	29	#include <asm/ppc-pci.h>
5d5a0936	30
5d5a0936 LV	31
	32	/**
	33	* The pci address cache subsystem. This subsystem places
	34	* PCI device address resources into a red-black tree, sorted
	35	* according to the address range, so that given only an i/o
	36	* address, the corresponding PCI device can be quickly
	37	* found. It is safe to perform an address lookup in an interrupt
	38	* context; this ability is an important feature.
	39	*
	40	* Currently, the only customer of this code is the EEH subsystem;
	41	* thus, this code has been somewhat tailored to suit EEH better.
	42	* In particular, the cache does not hold the addresses of devices
	43	* for which EEH is not enabled.
	44	*
	45	* (Implementation Note: The RB tree seems to be better/faster
	46	* than any hash algo I could think of for this problem, even
	47	* with the penalty of slow pointer chases for d-cache misses).
	48	*/
29f8bf1b	49	struct pci_io_addr_range {
5d5a0936 LV	50	struct rb_node rb_node;
	51	unsigned long addr_lo;
	52	unsigned long addr_hi;
f8f7d63f	53	struct eeh_dev *edev;
5d5a0936 LV	54	struct pci_dev *pcidev;
	55	unsigned int flags;
	56	};
	57
29f8bf1b	58	static struct pci_io_addr_cache {
5d5a0936 LV	59	struct rb_root rb_root;
	60	spinlock_t piar_lock;
	61	} pci_io_addr_cache_root;
	62
f8f7d63f	63	static inline struct eeh_dev *__pci_addr_cache_get_device(unsigned long addr)
5d5a0936 LV	64	{
	65	struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node;
	66
	67	while (n) {
	68	struct pci_io_addr_range *piar;
	69	piar = rb_entry(n, struct pci_io_addr_range, rb_node);
	70
	71	if (addr < piar->addr_lo) {
	72	n = n->rb_left;
	73	} else {
	74	if (addr > piar->addr_hi) {
	75	n = n->rb_right;
	76	} else {
	77	pci_dev_get(piar->pcidev);
f8f7d63f	78	return piar->edev;
5d5a0936 LV	79	}
	80	}
	81	}
	82
	83	return NULL;
	84	}
	85
	86	/**
def9d83d	87	* pci_addr_cache_get_device - Get device, given only address
5d5a0936 LV	88	* @addr: mmio (PIO) phys address or i/o port number
	89	*
	90	* Given an mmio phys address, or a port number, find a pci device
	91	* that implements this address. Be sure to pci_dev_put the device
	92	* when finished. I/O port numbers are assumed to be offset
	93	* from zero (that is, they do not have pci_io_addr added in).
	94	* It is safe to call this function within an interrupt.
	95	*/
f8f7d63f	96	struct eeh_dev *pci_addr_cache_get_device(unsigned long addr)
5d5a0936	97	{
f8f7d63f	98	struct eeh_dev *edev;
5d5a0936 LV	99	unsigned long flags;
	100
	101	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
f8f7d63f	102	edev = __pci_addr_cache_get_device(addr);
5d5a0936	103	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
f8f7d63f	104	return edev;
5d5a0936 LV	105	}
	106
	107	#ifdef DEBUG
	108	/*
	109	* Handy-dandy debug print routine, does nothing more
	110	* than print out the contents of our addr cache.
	111	*/
	112	static void pci_addr_cache_print(struct pci_io_addr_cache *cache)
	113	{
	114	struct rb_node *n;
	115	int cnt = 0;
	116
	117	n = rb_first(&cache->rb_root);
	118	while (n) {
	119	struct pci_io_addr_range *piar;
	120	piar = rb_entry(n, struct pci_io_addr_range, rb_node);
	121	printk(KERN_DEBUG "PCI: %s addr range %d [%lx-%lx]: %s\n",
	122	(piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt,
	123	piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev));
	124	cnt++;
	125	n = rb_next(n);
	126	}
	127	}
	128	#endif
	129
	130	/* Insert address range into the rb tree. */
	131	static struct pci_io_addr_range *
	132	pci_addr_cache_insert(struct pci_dev *dev, unsigned long alo,
	133	unsigned long ahi, unsigned int flags)
	134	{
	135	struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node;
	136	struct rb_node *parent = NULL;
	137	struct pci_io_addr_range *piar;
	138
	139	/* Walk tree, find a place to insert into tree */
	140	while (*p) {
	141	parent = *p;
	142	piar = rb_entry(parent, struct pci_io_addr_range, rb_node);
	143	if (ahi < piar->addr_lo) {
	144	p = &parent->rb_left;
	145	} else if (alo > piar->addr_hi) {
	146	p = &parent->rb_right;
	147	} else {
	148	if (dev != piar->pcidev \|\|
	149	alo != piar->addr_lo \|\| ahi != piar->addr_hi) {
	150	printk(KERN_WARNING "PIAR: overlapping address range\n");
	151	}
	152	return piar;
	153	}
	154	}
7e4bbaf0	155	piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC);
5d5a0936 LV	156	if (!piar)
	157	return NULL;
	158
af525592	159	pci_dev_get(dev);
5d5a0936 LV	160	piar->addr_lo = alo;
5d5a0936 LV	161	piar->addr_hi = ahi;
f8f7d63f	162	piar->edev = pci_dev_to_eeh_dev(dev);
5d5a0936 LV	163	piar->pcidev = dev;
	164	piar->flags = flags;
	165
	166	#ifdef DEBUG
	167	printk(KERN_DEBUG "PIAR: insert range=[%lx:%lx] dev=%s\n",
29f8bf1b	168	alo, ahi, pci_name(dev));
5d5a0936 LV	169	#endif
	170
	171	rb_link_node(&piar->rb_node, parent, p);
	172	rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root);
	173
	174	return piar;
	175	}
	176
	177	static void __pci_addr_cache_insert_device(struct pci_dev *dev)
	178	{
	179	struct device_node *dn;
d50a7d4c	180	struct eeh_dev *edev;
5d5a0936	181	int i;
5d5a0936 LV	182
	183	dn = pci_device_to_OF_node(dev);
	184	if (!dn) {
	185	printk(KERN_WARNING "PCI: no pci dn found for dev=%s\n", pci_name(dev));
	186	return;
	187	}
	188
d50a7d4c GS	189	edev = of_node_to_eeh_dev(dn);
	190	if (!edev) {
	191	pr_warning("PCI: no EEH dev found for dn=%s\n",
	192	dn->full_name);
	193	return;
	194	}
	195
5d5a0936	196	/* Skip any devices for which EEH is not enabled. */
dbbceee1	197	if (!edev->pe) {
5d5a0936	198	#ifdef DEBUG
d50a7d4c GS	199	pr_info("PCI: skip building address cache for=%s - %s\n",
d50a7d4c GS	200	pci_name(dev), dn->full_name);
5d5a0936 LV	201	#endif
	202	return;
	203	}
	204
5d5a0936 LV	205	/* Walk resources on this device, poke them into the tree */
	206	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
	207	unsigned long start = pci_resource_start(dev,i);
	208	unsigned long end = pci_resource_end(dev,i);
	209	unsigned int flags = pci_resource_flags(dev,i);
	210
	211	/* We are interested only bus addresses, not dma or other stuff */
	212	if (0 == (flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	213	continue;
	214	if (start == 0 \|\| ~start == 0 \|\| end == 0 \|\| ~end == 0)
	215	continue;
	216	pci_addr_cache_insert(dev, start, end, flags);
5d5a0936	217	}
5d5a0936 LV	218	}
	219
	220	/**
	221	* pci_addr_cache_insert_device - Add a device to the address cache
	222	* @dev: PCI device whose I/O addresses we are interested in.
	223	*
	224	* In order to support the fast lookup of devices based on addresses,
	225	* we maintain a cache of devices that can be quickly searched.
	226	* This routine adds a device to that cache.
	227	*/
	228	void pci_addr_cache_insert_device(struct pci_dev *dev)
	229	{
	230	unsigned long flags;
	231
093eda3c LV	232	/* Ignore PCI bridges */
	233	if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
	234	return;
	235
5d5a0936 LV	236	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
	237	__pci_addr_cache_insert_device(dev);
	238	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
	239	}
	240
	241	static inline void __pci_addr_cache_remove_device(struct pci_dev *dev)
	242	{
	243	struct rb_node *n;
5d5a0936 LV	244
	245	restart:
	246	n = rb_first(&pci_io_addr_cache_root.rb_root);
	247	while (n) {
	248	struct pci_io_addr_range *piar;
	249	piar = rb_entry(n, struct pci_io_addr_range, rb_node);
	250
	251	if (piar->pcidev == dev) {
	252	rb_erase(n, &pci_io_addr_cache_root.rb_root);
af525592	253	pci_dev_put(piar->pcidev);
5d5a0936 LV	254	kfree(piar);
	255	goto restart;
	256	}
	257	n = rb_next(n);
	258	}
5d5a0936 LV	259	}
	260
	261	/**
	262	* pci_addr_cache_remove_device - remove pci device from addr cache
	263	* @dev: device to remove
	264	*
	265	* Remove a device from the addr-cache tree.
	266	* This is potentially expensive, since it will walk
	267	* the tree multiple times (once per resource).
	268	* But so what; device removal doesn't need to be that fast.
	269	*/
	270	void pci_addr_cache_remove_device(struct pci_dev *dev)
	271	{
	272	unsigned long flags;
	273
	274	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
	275	__pci_addr_cache_remove_device(dev);
	276	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
	277	}
	278
	279	/**
	280	* pci_addr_cache_build - Build a cache of I/O addresses
	281	*
	282	* Build a cache of pci i/o addresses. This cache will be used to
	283	* find the pci device that corresponds to a given address.
	284	* This routine scans all pci busses to build the cache.
	285	* Must be run late in boot process, after the pci controllers
d6e05edc	286	* have been scanned for devices (after all device resources are known).
5d5a0936 LV	287	*/
	288	void __init pci_addr_cache_build(void)
	289	{
	290	struct device_node *dn;
d50a7d4c	291	struct eeh_dev *edev;
5d5a0936 LV	292	struct pci_dev *dev = NULL;
	293
	294	spin_lock_init(&pci_io_addr_cache_root.piar_lock);
	295
6901c6cc	296	for_each_pci_dev(dev) {
5d5a0936 LV	297	pci_addr_cache_insert_device(dev);
5d5a0936 LV	298
5d5a0936	299	dn = pci_device_to_OF_node(dev);
ccba051c NL	300	if (!dn)
ccba051c NL	301	continue;
d50a7d4c GS	302
	303	edev = of_node_to_eeh_dev(dn);
	304	if (!edev)
	305	continue;
	306
093eda3c	307	pci_dev_get(dev); /* matching put is in eeh_remove_device() */
d50a7d4c GS	308	dev->dev.archdata.edev = edev;
d50a7d4c GS	309	edev->pdev = dev;
e1d04c97 LV	310
e1d04c97 LV	311	eeh_sysfs_add_device(dev);
5d5a0936 LV	312	}
	313
	314	#ifdef DEBUG
	315	/* Verify tree built up above, echo back the list of addrs. */
	316	pci_addr_cache_print(&pci_io_addr_cache_root);
	317	#endif
	318	}
	319