Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
3 | * | |
bc97ce95 | 4 | * Rewrite, cleanup: |
1da177e4 | 5 | * |
91f14480 | 6 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
bc97ce95 | 7 | * Copyright (C) 2006 Olof Johansson <olof@lixom.net> |
1da177e4 LT |
8 | * |
9 | * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. | |
10 | * | |
bc97ce95 | 11 | * |
1da177e4 LT |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
bc97ce95 | 16 | * |
1da177e4 LT |
17 | * This program is distributed in the hope that it will be useful, |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
bc97ce95 | 21 | * |
1da177e4 LT |
22 | * You should have received a copy of the GNU General Public License |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/types.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/mm.h> | |
beacc6da | 31 | #include <linux/memblock.h> |
1da177e4 | 32 | #include <linux/spinlock.h> |
62fe91bb | 33 | #include <linux/sched.h> /* for show_stack */ |
1da177e4 LT |
34 | #include <linux/string.h> |
35 | #include <linux/pci.h> | |
36 | #include <linux/dma-mapping.h> | |
62a8bd6c | 37 | #include <linux/crash_dump.h> |
4e8b0cf4 | 38 | #include <linux/memory.h> |
1cf3d8b3 | 39 | #include <linux/of.h> |
1da177e4 LT |
40 | #include <asm/io.h> |
41 | #include <asm/prom.h> | |
42 | #include <asm/rtas.h> | |
1da177e4 LT |
43 | #include <asm/iommu.h> |
44 | #include <asm/pci-bridge.h> | |
45 | #include <asm/machdep.h> | |
1ababe11 | 46 | #include <asm/firmware.h> |
c707ffcf | 47 | #include <asm/tce.h> |
d387899f | 48 | #include <asm/ppc-pci.h> |
2249ca9d | 49 | #include <asm/udbg.h> |
4e8b0cf4 | 50 | #include <asm/mmzone.h> |
212bebb4 | 51 | #include <asm/plpar_wrappers.h> |
a1218720 | 52 | |
1da177e4 | 53 | |
8d3d589a MM |
54 | static void tce_invalidate_pSeries_sw(struct iommu_table *tbl, |
55 | u64 *startp, u64 *endp) | |
56 | { | |
57 | u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index; | |
58 | unsigned long start, end, inc; | |
59 | ||
60 | start = __pa(startp); | |
61 | end = __pa(endp); | |
62 | inc = L1_CACHE_BYTES; /* invalidate a cacheline of TCEs at a time */ | |
63 | ||
64 | /* If this is non-zero, change the format. We shift the | |
65 | * address and or in the magic from the device tree. */ | |
66 | if (tbl->it_busno) { | |
67 | start <<= 12; | |
68 | end <<= 12; | |
69 | inc <<= 12; | |
70 | start |= tbl->it_busno; | |
71 | end |= tbl->it_busno; | |
72 | } | |
73 | ||
74 | end |= inc - 1; /* round up end to be different than start */ | |
75 | ||
76 | mb(); /* Make sure TCEs in memory are written */ | |
77 | while (start <= end) { | |
78 | out_be64(invalidate, start); | |
79 | start += inc; | |
80 | } | |
81 | } | |
82 | ||
6490c490 | 83 | static int tce_build_pSeries(struct iommu_table *tbl, long index, |
bc97ce95 | 84 | long npages, unsigned long uaddr, |
4f3dd8a0 MN |
85 | enum dma_data_direction direction, |
86 | struct dma_attrs *attrs) | |
1da177e4 | 87 | { |
bc97ce95 | 88 | u64 proto_tce; |
8d3d589a | 89 | u64 *tcep, *tces; |
bc97ce95 | 90 | u64 rpn; |
1da177e4 | 91 | |
bc97ce95 | 92 | proto_tce = TCE_PCI_READ; // Read allowed |
1da177e4 LT |
93 | |
94 | if (direction != DMA_TO_DEVICE) | |
bc97ce95 | 95 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 | 96 | |
8d3d589a | 97 | tces = tcep = ((u64 *)tbl->it_base) + index; |
1da177e4 LT |
98 | |
99 | while (npages--) { | |
95f72d1e | 100 | /* can't move this out since we might cross MEMBLOCK boundary */ |
474e3d56 | 101 | rpn = __pa(uaddr) >> TCE_SHIFT; |
bc97ce95 | 102 | *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; |
1da177e4 | 103 | |
d0035c62 | 104 | uaddr += TCE_PAGE_SIZE; |
bc97ce95 | 105 | tcep++; |
1da177e4 | 106 | } |
8d3d589a | 107 | |
bc6dc752 | 108 | if (tbl->it_type & TCE_PCI_SWINV_CREATE) |
8d3d589a | 109 | tce_invalidate_pSeries_sw(tbl, tces, tcep - 1); |
6490c490 | 110 | return 0; |
1da177e4 LT |
111 | } |
112 | ||
113 | ||
114 | static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) | |
115 | { | |
8d3d589a | 116 | u64 *tcep, *tces; |
1da177e4 | 117 | |
8d3d589a | 118 | tces = tcep = ((u64 *)tbl->it_base) + index; |
bc97ce95 OJ |
119 | |
120 | while (npages--) | |
121 | *(tcep++) = 0; | |
8d3d589a | 122 | |
bc6dc752 | 123 | if (tbl->it_type & TCE_PCI_SWINV_FREE) |
8d3d589a | 124 | tce_invalidate_pSeries_sw(tbl, tces, tcep - 1); |
1da177e4 LT |
125 | } |
126 | ||
5f50867b HM |
127 | static unsigned long tce_get_pseries(struct iommu_table *tbl, long index) |
128 | { | |
129 | u64 *tcep; | |
130 | ||
5f50867b HM |
131 | tcep = ((u64 *)tbl->it_base) + index; |
132 | ||
133 | return *tcep; | |
134 | } | |
1da177e4 | 135 | |
6490c490 RJ |
136 | static void tce_free_pSeriesLP(struct iommu_table*, long, long); |
137 | static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long); | |
138 | ||
139 | static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
1da177e4 | 140 | long npages, unsigned long uaddr, |
4f3dd8a0 MN |
141 | enum dma_data_direction direction, |
142 | struct dma_attrs *attrs) | |
1da177e4 | 143 | { |
6490c490 | 144 | u64 rc = 0; |
bc97ce95 OJ |
145 | u64 proto_tce, tce; |
146 | u64 rpn; | |
6490c490 RJ |
147 | int ret = 0; |
148 | long tcenum_start = tcenum, npages_start = npages; | |
1da177e4 | 149 | |
474e3d56 | 150 | rpn = __pa(uaddr) >> TCE_SHIFT; |
bc97ce95 | 151 | proto_tce = TCE_PCI_READ; |
1da177e4 | 152 | if (direction != DMA_TO_DEVICE) |
bc97ce95 | 153 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 LT |
154 | |
155 | while (npages--) { | |
bc97ce95 OJ |
156 | tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; |
157 | rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce); | |
158 | ||
6490c490 RJ |
159 | if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { |
160 | ret = (int)rc; | |
161 | tce_free_pSeriesLP(tbl, tcenum_start, | |
162 | (npages_start - (npages + 1))); | |
163 | break; | |
164 | } | |
165 | ||
1da177e4 | 166 | if (rc && printk_ratelimit()) { |
fe333321 IM |
167 | printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); |
168 | printk("\tindex = 0x%llx\n", (u64)tbl->it_index); | |
169 | printk("\ttcenum = 0x%llx\n", (u64)tcenum); | |
170 | printk("\ttce val = 0x%llx\n", tce ); | |
1da177e4 LT |
171 | show_stack(current, (unsigned long *)__get_SP()); |
172 | } | |
bc97ce95 | 173 | |
1da177e4 | 174 | tcenum++; |
bc97ce95 | 175 | rpn++; |
1da177e4 | 176 | } |
6490c490 | 177 | return ret; |
1da177e4 LT |
178 | } |
179 | ||
a8daac8a | 180 | static DEFINE_PER_CPU(u64 *, tce_page); |
1da177e4 | 181 | |
6490c490 | 182 | static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, |
1da177e4 | 183 | long npages, unsigned long uaddr, |
4f3dd8a0 MN |
184 | enum dma_data_direction direction, |
185 | struct dma_attrs *attrs) | |
1da177e4 | 186 | { |
6490c490 | 187 | u64 rc = 0; |
bc97ce95 OJ |
188 | u64 proto_tce; |
189 | u64 *tcep; | |
190 | u64 rpn; | |
1da177e4 | 191 | long l, limit; |
6490c490 RJ |
192 | long tcenum_start = tcenum, npages_start = npages; |
193 | int ret = 0; | |
c1703e85 | 194 | unsigned long flags; |
1da177e4 | 195 | |
541b2755 | 196 | if (npages == 1) { |
6490c490 RJ |
197 | return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, |
198 | direction, attrs); | |
541b2755 | 199 | } |
1da177e4 | 200 | |
c1703e85 AB |
201 | local_irq_save(flags); /* to protect tcep and the page behind it */ |
202 | ||
1da177e4 LT |
203 | tcep = __get_cpu_var(tce_page); |
204 | ||
205 | /* This is safe to do since interrupts are off when we're called | |
206 | * from iommu_alloc{,_sg}() | |
207 | */ | |
208 | if (!tcep) { | |
bc97ce95 | 209 | tcep = (u64 *)__get_free_page(GFP_ATOMIC); |
1da177e4 | 210 | /* If allocation fails, fall back to the loop implementation */ |
541b2755 | 211 | if (!tcep) { |
c1703e85 | 212 | local_irq_restore(flags); |
6490c490 | 213 | return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, |
4f3dd8a0 | 214 | direction, attrs); |
541b2755 | 215 | } |
1da177e4 LT |
216 | __get_cpu_var(tce_page) = tcep; |
217 | } | |
218 | ||
474e3d56 | 219 | rpn = __pa(uaddr) >> TCE_SHIFT; |
bc97ce95 | 220 | proto_tce = TCE_PCI_READ; |
1da177e4 | 221 | if (direction != DMA_TO_DEVICE) |
bc97ce95 | 222 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 LT |
223 | |
224 | /* We can map max one pageful of TCEs at a time */ | |
225 | do { | |
226 | /* | |
227 | * Set up the page with TCE data, looping through and setting | |
228 | * the values. | |
229 | */ | |
bc97ce95 | 230 | limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE); |
1da177e4 LT |
231 | |
232 | for (l = 0; l < limit; l++) { | |
bc97ce95 OJ |
233 | tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; |
234 | rpn++; | |
1da177e4 LT |
235 | } |
236 | ||
237 | rc = plpar_tce_put_indirect((u64)tbl->it_index, | |
238 | (u64)tcenum << 12, | |
474e3d56 | 239 | (u64)__pa(tcep), |
1da177e4 LT |
240 | limit); |
241 | ||
242 | npages -= limit; | |
243 | tcenum += limit; | |
244 | } while (npages > 0 && !rc); | |
245 | ||
c1703e85 AB |
246 | local_irq_restore(flags); |
247 | ||
6490c490 RJ |
248 | if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { |
249 | ret = (int)rc; | |
250 | tce_freemulti_pSeriesLP(tbl, tcenum_start, | |
251 | (npages_start - (npages + limit))); | |
252 | return ret; | |
253 | } | |
254 | ||
1da177e4 | 255 | if (rc && printk_ratelimit()) { |
fe333321 IM |
256 | printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); |
257 | printk("\tindex = 0x%llx\n", (u64)tbl->it_index); | |
258 | printk("\tnpages = 0x%llx\n", (u64)npages); | |
259 | printk("\ttce[0] val = 0x%llx\n", tcep[0]); | |
1da177e4 LT |
260 | show_stack(current, (unsigned long *)__get_SP()); |
261 | } | |
6490c490 | 262 | return ret; |
1da177e4 LT |
263 | } |
264 | ||
265 | static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
266 | { | |
267 | u64 rc; | |
1da177e4 | 268 | |
1da177e4 | 269 | while (npages--) { |
bc97ce95 | 270 | rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0); |
1da177e4 LT |
271 | |
272 | if (rc && printk_ratelimit()) { | |
fe333321 IM |
273 | printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); |
274 | printk("\tindex = 0x%llx\n", (u64)tbl->it_index); | |
275 | printk("\ttcenum = 0x%llx\n", (u64)tcenum); | |
1da177e4 LT |
276 | show_stack(current, (unsigned long *)__get_SP()); |
277 | } | |
278 | ||
279 | tcenum++; | |
280 | } | |
281 | } | |
282 | ||
283 | ||
284 | static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
285 | { | |
286 | u64 rc; | |
1da177e4 | 287 | |
bc97ce95 | 288 | rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages); |
1da177e4 LT |
289 | |
290 | if (rc && printk_ratelimit()) { | |
291 | printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); | |
fe333321 IM |
292 | printk("\trc = %lld\n", rc); |
293 | printk("\tindex = 0x%llx\n", (u64)tbl->it_index); | |
294 | printk("\tnpages = 0x%llx\n", (u64)npages); | |
1da177e4 LT |
295 | show_stack(current, (unsigned long *)__get_SP()); |
296 | } | |
297 | } | |
298 | ||
5f50867b HM |
299 | static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum) |
300 | { | |
301 | u64 rc; | |
302 | unsigned long tce_ret; | |
303 | ||
5f50867b HM |
304 | rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret); |
305 | ||
306 | if (rc && printk_ratelimit()) { | |
fe333321 IM |
307 | printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc); |
308 | printk("\tindex = 0x%llx\n", (u64)tbl->it_index); | |
309 | printk("\ttcenum = 0x%llx\n", (u64)tcenum); | |
5f50867b HM |
310 | show_stack(current, (unsigned long *)__get_SP()); |
311 | } | |
312 | ||
313 | return tce_ret; | |
314 | } | |
315 | ||
25985edc | 316 | /* this is compatible with cells for the device tree property */ |
4e8b0cf4 NA |
317 | struct dynamic_dma_window_prop { |
318 | __be32 liobn; /* tce table number */ | |
319 | __be64 dma_base; /* address hi,lo */ | |
320 | __be32 tce_shift; /* ilog2(tce_page_size) */ | |
321 | __be32 window_shift; /* ilog2(tce_window_size) */ | |
322 | }; | |
323 | ||
324 | struct direct_window { | |
325 | struct device_node *device; | |
326 | const struct dynamic_dma_window_prop *prop; | |
327 | struct list_head list; | |
328 | }; | |
329 | ||
330 | /* Dynamic DMA Window support */ | |
331 | struct ddw_query_response { | |
332 | u32 windows_available; | |
333 | u32 largest_available_block; | |
334 | u32 page_size; | |
335 | u32 migration_capable; | |
336 | }; | |
337 | ||
338 | struct ddw_create_response { | |
339 | u32 liobn; | |
340 | u32 addr_hi; | |
341 | u32 addr_lo; | |
342 | }; | |
343 | ||
344 | static LIST_HEAD(direct_window_list); | |
345 | /* prevents races between memory on/offline and window creation */ | |
346 | static DEFINE_SPINLOCK(direct_window_list_lock); | |
347 | /* protects initializing window twice for same device */ | |
348 | static DEFINE_MUTEX(direct_window_init_mutex); | |
349 | #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info" | |
350 | ||
351 | static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn, | |
352 | unsigned long num_pfn, const void *arg) | |
353 | { | |
354 | const struct dynamic_dma_window_prop *maprange = arg; | |
355 | int rc; | |
356 | u64 tce_size, num_tce, dma_offset, next; | |
357 | u32 tce_shift; | |
358 | long limit; | |
359 | ||
360 | tce_shift = be32_to_cpu(maprange->tce_shift); | |
361 | tce_size = 1ULL << tce_shift; | |
362 | next = start_pfn << PAGE_SHIFT; | |
363 | num_tce = num_pfn << PAGE_SHIFT; | |
364 | ||
365 | /* round back to the beginning of the tce page size */ | |
366 | num_tce += next & (tce_size - 1); | |
367 | next &= ~(tce_size - 1); | |
368 | ||
369 | /* covert to number of tces */ | |
370 | num_tce |= tce_size - 1; | |
371 | num_tce >>= tce_shift; | |
372 | ||
373 | do { | |
374 | /* | |
375 | * Set up the page with TCE data, looping through and setting | |
376 | * the values. | |
377 | */ | |
378 | limit = min_t(long, num_tce, 512); | |
379 | dma_offset = next + be64_to_cpu(maprange->dma_base); | |
380 | ||
381 | rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn), | |
382 | dma_offset, | |
383 | 0, limit); | |
22b38298 | 384 | next += limit * tce_size; |
4e8b0cf4 NA |
385 | num_tce -= limit; |
386 | } while (num_tce > 0 && !rc); | |
387 | ||
388 | return rc; | |
389 | } | |
390 | ||
391 | static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn, | |
392 | unsigned long num_pfn, const void *arg) | |
393 | { | |
394 | const struct dynamic_dma_window_prop *maprange = arg; | |
395 | u64 *tcep, tce_size, num_tce, dma_offset, next, proto_tce, liobn; | |
396 | u32 tce_shift; | |
397 | u64 rc = 0; | |
398 | long l, limit; | |
399 | ||
400 | local_irq_disable(); /* to protect tcep and the page behind it */ | |
401 | tcep = __get_cpu_var(tce_page); | |
402 | ||
403 | if (!tcep) { | |
404 | tcep = (u64 *)__get_free_page(GFP_ATOMIC); | |
405 | if (!tcep) { | |
406 | local_irq_enable(); | |
407 | return -ENOMEM; | |
408 | } | |
409 | __get_cpu_var(tce_page) = tcep; | |
410 | } | |
411 | ||
412 | proto_tce = TCE_PCI_READ | TCE_PCI_WRITE; | |
413 | ||
414 | liobn = (u64)be32_to_cpu(maprange->liobn); | |
415 | tce_shift = be32_to_cpu(maprange->tce_shift); | |
416 | tce_size = 1ULL << tce_shift; | |
417 | next = start_pfn << PAGE_SHIFT; | |
418 | num_tce = num_pfn << PAGE_SHIFT; | |
419 | ||
420 | /* round back to the beginning of the tce page size */ | |
421 | num_tce += next & (tce_size - 1); | |
422 | next &= ~(tce_size - 1); | |
423 | ||
424 | /* covert to number of tces */ | |
425 | num_tce |= tce_size - 1; | |
426 | num_tce >>= tce_shift; | |
427 | ||
428 | /* We can map max one pageful of TCEs at a time */ | |
429 | do { | |
430 | /* | |
431 | * Set up the page with TCE data, looping through and setting | |
432 | * the values. | |
433 | */ | |
434 | limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE); | |
435 | dma_offset = next + be64_to_cpu(maprange->dma_base); | |
436 | ||
437 | for (l = 0; l < limit; l++) { | |
438 | tcep[l] = proto_tce | next; | |
439 | next += tce_size; | |
440 | } | |
441 | ||
442 | rc = plpar_tce_put_indirect(liobn, | |
443 | dma_offset, | |
474e3d56 | 444 | (u64)__pa(tcep), |
4e8b0cf4 NA |
445 | limit); |
446 | ||
447 | num_tce -= limit; | |
448 | } while (num_tce > 0 && !rc); | |
449 | ||
450 | /* error cleanup: caller will clear whole range */ | |
451 | ||
452 | local_irq_enable(); | |
453 | return rc; | |
454 | } | |
455 | ||
456 | static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn, | |
457 | unsigned long num_pfn, void *arg) | |
458 | { | |
459 | return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg); | |
460 | } | |
461 | ||
462 | ||
bed59275 | 463 | #ifdef CONFIG_PCI |
1da177e4 LT |
464 | static void iommu_table_setparms(struct pci_controller *phb, |
465 | struct device_node *dn, | |
bc97ce95 | 466 | struct iommu_table *tbl) |
1da177e4 LT |
467 | { |
468 | struct device_node *node; | |
8d3d589a | 469 | const unsigned long *basep, *sw_inval; |
9938c474 | 470 | const u32 *sizep; |
1da177e4 | 471 | |
44ef3390 | 472 | node = phb->dn; |
1da177e4 | 473 | |
e2eb6392 SR |
474 | basep = of_get_property(node, "linux,tce-base", NULL); |
475 | sizep = of_get_property(node, "linux,tce-size", NULL); | |
1da177e4 LT |
476 | if (basep == NULL || sizep == NULL) { |
477 | printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has " | |
478 | "missing tce entries !\n", dn->full_name); | |
479 | return; | |
480 | } | |
481 | ||
482 | tbl->it_base = (unsigned long)__va(*basep); | |
5f50867b | 483 | |
62a8bd6c | 484 | if (!is_kdump_kernel()) |
54622f10 | 485 | memset((void *)tbl->it_base, 0, *sizep); |
1da177e4 LT |
486 | |
487 | tbl->it_busno = phb->bus->number; | |
bc97ce95 | 488 | |
1da177e4 | 489 | /* Units of tce entries */ |
5d2efba6 | 490 | tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT; |
bc97ce95 | 491 | |
1da177e4 | 492 | /* Test if we are going over 2GB of DMA space */ |
3c2822cc OJ |
493 | if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) { |
494 | udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); | |
bc97ce95 | 495 | panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); |
3c2822cc | 496 | } |
bc97ce95 | 497 | |
1da177e4 LT |
498 | phb->dma_window_base_cur += phb->dma_window_size; |
499 | ||
500 | /* Set the tce table size - measured in entries */ | |
5d2efba6 | 501 | tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT; |
1da177e4 LT |
502 | |
503 | tbl->it_index = 0; | |
504 | tbl->it_blocksize = 16; | |
505 | tbl->it_type = TCE_PCI; | |
8d3d589a MM |
506 | |
507 | sw_inval = of_get_property(node, "linux,tce-sw-invalidate-info", NULL); | |
508 | if (sw_inval) { | |
509 | /* | |
510 | * This property contains information on how to | |
511 | * invalidate the TCE entry. The first property is | |
512 | * the base MMIO address used to invalidate entries. | |
513 | * The second property tells us the format of the TCE | |
514 | * invalidate (whether it needs to be shifted) and | |
515 | * some magic routing info to add to our invalidate | |
516 | * command. | |
517 | */ | |
518 | tbl->it_index = (unsigned long) ioremap(sw_inval[0], 8); | |
519 | tbl->it_busno = sw_inval[1]; /* overload this with magic */ | |
1f1616e8 | 520 | tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE; |
8d3d589a | 521 | } |
1da177e4 LT |
522 | } |
523 | ||
524 | /* | |
525 | * iommu_table_setparms_lpar | |
526 | * | |
527 | * Function: On pSeries LPAR systems, return TCE table info, given a pci bus. | |
1da177e4 LT |
528 | */ |
529 | static void iommu_table_setparms_lpar(struct pci_controller *phb, | |
530 | struct device_node *dn, | |
531 | struct iommu_table *tbl, | |
2083f681 | 532 | const __be32 *dma_window) |
1da177e4 | 533 | { |
4c76e0bc JK |
534 | unsigned long offset, size; |
535 | ||
4c76e0bc | 536 | of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size); |
1da177e4 | 537 | |
b8c49def | 538 | tbl->it_busno = phb->bus->number; |
1da177e4 | 539 | tbl->it_base = 0; |
1da177e4 LT |
540 | tbl->it_blocksize = 16; |
541 | tbl->it_type = TCE_PCI; | |
5d2efba6 LV |
542 | tbl->it_offset = offset >> IOMMU_PAGE_SHIFT; |
543 | tbl->it_size = size >> IOMMU_PAGE_SHIFT; | |
1da177e4 LT |
544 | } |
545 | ||
12d04eef | 546 | static void pci_dma_bus_setup_pSeries(struct pci_bus *bus) |
1da177e4 | 547 | { |
3c2822cc | 548 | struct device_node *dn; |
1da177e4 | 549 | struct iommu_table *tbl; |
3c2822cc OJ |
550 | struct device_node *isa_dn, *isa_dn_orig; |
551 | struct device_node *tmp; | |
552 | struct pci_dn *pci; | |
553 | int children; | |
1da177e4 | 554 | |
3c2822cc | 555 | dn = pci_bus_to_OF_node(bus); |
12d04eef | 556 | |
f7ebf352 | 557 | pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name); |
3c2822cc OJ |
558 | |
559 | if (bus->self) { | |
560 | /* This is not a root bus, any setup will be done for the | |
561 | * device-side of the bridge in iommu_dev_setup_pSeries(). | |
562 | */ | |
563 | return; | |
564 | } | |
12d04eef | 565 | pci = PCI_DN(dn); |
3c2822cc OJ |
566 | |
567 | /* Check if the ISA bus on the system is under | |
568 | * this PHB. | |
1da177e4 | 569 | */ |
3c2822cc | 570 | isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa"); |
1da177e4 | 571 | |
3c2822cc OJ |
572 | while (isa_dn && isa_dn != dn) |
573 | isa_dn = isa_dn->parent; | |
574 | ||
575 | if (isa_dn_orig) | |
576 | of_node_put(isa_dn_orig); | |
1da177e4 | 577 | |
d3c58fb1 | 578 | /* Count number of direct PCI children of the PHB. */ |
3c2822cc | 579 | for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling) |
d3c58fb1 | 580 | children++; |
1da177e4 | 581 | |
f7ebf352 | 582 | pr_debug("Children: %d\n", children); |
1da177e4 | 583 | |
3c2822cc OJ |
584 | /* Calculate amount of DMA window per slot. Each window must be |
585 | * a power of two (due to pci_alloc_consistent requirements). | |
586 | * | |
587 | * Keep 256MB aside for PHBs with ISA. | |
588 | */ | |
1da177e4 | 589 | |
3c2822cc OJ |
590 | if (!isa_dn) { |
591 | /* No ISA/IDE - just set window size and return */ | |
592 | pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ | |
593 | ||
594 | while (pci->phb->dma_window_size * children > 0x80000000ul) | |
595 | pci->phb->dma_window_size >>= 1; | |
41febbc8 | 596 | pr_debug("No ISA/IDE, window size is 0x%llx\n", |
f7ebf352 | 597 | pci->phb->dma_window_size); |
3c2822cc OJ |
598 | pci->phb->dma_window_base_cur = 0; |
599 | ||
600 | return; | |
1da177e4 | 601 | } |
3c2822cc OJ |
602 | |
603 | /* If we have ISA, then we probably have an IDE | |
604 | * controller too. Allocate a 128MB table but | |
605 | * skip the first 128MB to avoid stepping on ISA | |
606 | * space. | |
607 | */ | |
608 | pci->phb->dma_window_size = 0x8000000ul; | |
609 | pci->phb->dma_window_base_cur = 0x8000000ul; | |
610 | ||
7aa241fd | 611 | tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
ca1588e7 | 612 | pci->phb->node); |
3c2822cc OJ |
613 | |
614 | iommu_table_setparms(pci->phb, dn, tbl); | |
ca1588e7 | 615 | pci->iommu_table = iommu_init_table(tbl, pci->phb->node); |
5b25199e | 616 | iommu_register_group(tbl, pci_domain_nr(bus), 0); |
3c2822cc OJ |
617 | |
618 | /* Divide the rest (1.75GB) among the children */ | |
619 | pci->phb->dma_window_size = 0x80000000ul; | |
620 | while (pci->phb->dma_window_size * children > 0x70000000ul) | |
621 | pci->phb->dma_window_size >>= 1; | |
622 | ||
41febbc8 | 623 | pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size); |
1da177e4 LT |
624 | } |
625 | ||
626 | ||
12d04eef | 627 | static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus) |
1da177e4 LT |
628 | { |
629 | struct iommu_table *tbl; | |
630 | struct device_node *dn, *pdn; | |
1635317f | 631 | struct pci_dn *ppci; |
2083f681 | 632 | const __be32 *dma_window = NULL; |
1da177e4 | 633 | |
1da177e4 LT |
634 | dn = pci_bus_to_OF_node(bus); |
635 | ||
f7ebf352 ME |
636 | pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n", |
637 | dn->full_name); | |
12d04eef | 638 | |
1da177e4 LT |
639 | /* Find nearest ibm,dma-window, walking up the device tree */ |
640 | for (pdn = dn; pdn != NULL; pdn = pdn->parent) { | |
e2eb6392 | 641 | dma_window = of_get_property(pdn, "ibm,dma-window", NULL); |
1da177e4 LT |
642 | if (dma_window != NULL) |
643 | break; | |
644 | } | |
645 | ||
646 | if (dma_window == NULL) { | |
f7ebf352 | 647 | pr_debug(" no ibm,dma-window property !\n"); |
1da177e4 LT |
648 | return; |
649 | } | |
650 | ||
e07102db | 651 | ppci = PCI_DN(pdn); |
12d04eef | 652 | |
f7ebf352 ME |
653 | pr_debug(" parent is %s, iommu_table: 0x%p\n", |
654 | pdn->full_name, ppci->iommu_table); | |
12d04eef | 655 | |
1635317f | 656 | if (!ppci->iommu_table) { |
7aa241fd | 657 | tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
ca1588e7 | 658 | ppci->phb->node); |
b8c49def | 659 | iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window); |
ca1588e7 | 660 | ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node); |
5b25199e | 661 | iommu_register_group(tbl, pci_domain_nr(bus), 0); |
f7ebf352 | 662 | pr_debug(" created table: %p\n", ppci->iommu_table); |
1da177e4 | 663 | } |
1da177e4 LT |
664 | } |
665 | ||
666 | ||
12d04eef | 667 | static void pci_dma_dev_setup_pSeries(struct pci_dev *dev) |
1da177e4 | 668 | { |
12d04eef | 669 | struct device_node *dn; |
3c2822cc | 670 | struct iommu_table *tbl; |
1da177e4 | 671 | |
f7ebf352 | 672 | pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev)); |
1da177e4 | 673 | |
58f9b0b0 | 674 | dn = dev->dev.of_node; |
1da177e4 | 675 | |
3c2822cc OJ |
676 | /* If we're the direct child of a root bus, then we need to allocate |
677 | * an iommu table ourselves. The bus setup code should have setup | |
678 | * the window sizes already. | |
679 | */ | |
680 | if (!dev->bus->self) { | |
12d04eef BH |
681 | struct pci_controller *phb = PCI_DN(dn)->phb; |
682 | ||
f7ebf352 | 683 | pr_debug(" --> first child, no bridge. Allocating iommu table.\n"); |
7aa241fd | 684 | tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
12d04eef BH |
685 | phb->node); |
686 | iommu_table_setparms(phb, dn, tbl); | |
77319254 | 687 | PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node); |
5b25199e | 688 | iommu_register_group(tbl, pci_domain_nr(phb->bus), 0); |
738ef42e | 689 | set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table); |
3c2822cc OJ |
690 | return; |
691 | } | |
692 | ||
693 | /* If this device is further down the bus tree, search upwards until | |
694 | * an already allocated iommu table is found and use that. | |
695 | */ | |
696 | ||
e07102db | 697 | while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL) |
1da177e4 LT |
698 | dn = dn->parent; |
699 | ||
12d04eef | 700 | if (dn && PCI_DN(dn)) |
738ef42e | 701 | set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table); |
12d04eef BH |
702 | else |
703 | printk(KERN_WARNING "iommu: Device %s has no iommu table\n", | |
704 | pci_name(dev)); | |
1da177e4 LT |
705 | } |
706 | ||
4e8b0cf4 NA |
707 | static int __read_mostly disable_ddw; |
708 | ||
709 | static int __init disable_ddw_setup(char *str) | |
710 | { | |
711 | disable_ddw = 1; | |
712 | printk(KERN_INFO "ppc iommu: disabling ddw.\n"); | |
713 | ||
714 | return 0; | |
715 | } | |
716 | ||
717 | early_param("disable_ddw", disable_ddw_setup); | |
718 | ||
25ebc45b NA |
719 | static inline void __remove_ddw(struct device_node *np, const u32 *ddw_avail, u64 liobn) |
720 | { | |
721 | int ret; | |
722 | ||
723 | ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn); | |
724 | if (ret) | |
725 | pr_warning("%s: failed to remove DMA window: rtas returned " | |
726 | "%d to ibm,remove-pe-dma-window(%x) %llx\n", | |
727 | np->full_name, ret, ddw_avail[2], liobn); | |
728 | else | |
729 | pr_debug("%s: successfully removed DMA window: rtas returned " | |
730 | "%d to ibm,remove-pe-dma-window(%x) %llx\n", | |
731 | np->full_name, ret, ddw_avail[2], liobn); | |
732 | } | |
733 | ||
4e8b0cf4 NA |
734 | static void remove_ddw(struct device_node *np) |
735 | { | |
736 | struct dynamic_dma_window_prop *dwp; | |
737 | struct property *win64; | |
b73a635f | 738 | const u32 *ddw_avail; |
4e8b0cf4 NA |
739 | u64 liobn; |
740 | int len, ret; | |
741 | ||
b73a635f | 742 | ddw_avail = of_get_property(np, "ibm,ddw-applicable", &len); |
4e8b0cf4 | 743 | win64 = of_find_property(np, DIRECT64_PROPNAME, NULL); |
2573f684 | 744 | if (!win64) |
4e8b0cf4 NA |
745 | return; |
746 | ||
b73a635f | 747 | if (!ddw_avail || len < 3 * sizeof(u32) || win64->length < sizeof(*dwp)) |
2573f684 MM |
748 | goto delprop; |
749 | ||
4e8b0cf4 NA |
750 | dwp = win64->value; |
751 | liobn = (u64)be32_to_cpu(dwp->liobn); | |
752 | ||
753 | /* clear the whole window, note the arg is in kernel pages */ | |
754 | ret = tce_clearrange_multi_pSeriesLP(0, | |
755 | 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp); | |
756 | if (ret) | |
757 | pr_warning("%s failed to clear tces in window.\n", | |
758 | np->full_name); | |
759 | else | |
760 | pr_debug("%s successfully cleared tces in window.\n", | |
761 | np->full_name); | |
762 | ||
25ebc45b | 763 | __remove_ddw(np, ddw_avail, liobn); |
4e8b0cf4 | 764 | |
2573f684 | 765 | delprop: |
79d1c712 | 766 | ret = of_remove_property(np, win64); |
2573f684 | 767 | if (ret) |
c8566780 | 768 | pr_warning("%s: failed to remove direct window property: %d\n", |
2573f684 MM |
769 | np->full_name, ret); |
770 | } | |
4e8b0cf4 | 771 | |
b73a635f | 772 | static u64 find_existing_ddw(struct device_node *pdn) |
4e8b0cf4 | 773 | { |
4e8b0cf4 NA |
774 | struct direct_window *window; |
775 | const struct dynamic_dma_window_prop *direct64; | |
776 | u64 dma_addr = 0; | |
777 | ||
4e8b0cf4 NA |
778 | spin_lock(&direct_window_list_lock); |
779 | /* check if we already created a window and dupe that config if so */ | |
780 | list_for_each_entry(window, &direct_window_list, list) { | |
781 | if (window->device == pdn) { | |
782 | direct64 = window->prop; | |
783 | dma_addr = direct64->dma_base; | |
784 | break; | |
785 | } | |
786 | } | |
787 | spin_unlock(&direct_window_list_lock); | |
788 | ||
789 | return dma_addr; | |
790 | } | |
791 | ||
14b6f00f NA |
792 | static void __restore_default_window(struct eeh_dev *edev, |
793 | u32 ddw_restore_token) | |
794 | { | |
795 | u32 cfg_addr; | |
796 | u64 buid; | |
797 | int ret; | |
798 | ||
799 | /* | |
800 | * Get the config address and phb buid of the PE window. | |
801 | * Rely on eeh to retrieve this for us. | |
802 | * Retrieve them from the pci device, not the node with the | |
803 | * dma-window property | |
804 | */ | |
805 | cfg_addr = edev->config_addr; | |
806 | if (edev->pe_config_addr) | |
807 | cfg_addr = edev->pe_config_addr; | |
808 | buid = edev->phb->buid; | |
809 | ||
810 | do { | |
811 | ret = rtas_call(ddw_restore_token, 3, 1, NULL, cfg_addr, | |
812 | BUID_HI(buid), BUID_LO(buid)); | |
813 | } while (rtas_busy_delay(ret)); | |
814 | pr_info("ibm,reset-pe-dma-windows(%x) %x %x %x returned %d\n", | |
815 | ddw_restore_token, cfg_addr, BUID_HI(buid), BUID_LO(buid), ret); | |
816 | } | |
817 | ||
c8566780 | 818 | static int find_existing_ddw_windows(void) |
4e8b0cf4 | 819 | { |
c8566780 | 820 | struct device_node *pdn; |
4e8b0cf4 | 821 | const struct dynamic_dma_window_prop *direct64; |
14b6f00f | 822 | const u32 *ddw_extensions; |
4e8b0cf4 | 823 | |
c8566780 MM |
824 | if (!firmware_has_feature(FW_FEATURE_LPAR)) |
825 | return 0; | |
826 | ||
827 | for_each_node_with_property(pdn, DIRECT64_PROPNAME) { | |
14b6f00f | 828 | direct64 = of_get_property(pdn, DIRECT64_PROPNAME, NULL); |
c8566780 MM |
829 | if (!direct64) |
830 | continue; | |
831 | ||
14b6f00f NA |
832 | /* |
833 | * We need to ensure the IOMMU table is active when we | |
834 | * return from the IOMMU setup so that the common code | |
835 | * can clear the table or find the holes. To that end, | |
836 | * first, remove any existing DDW configuration. | |
837 | */ | |
838 | remove_ddw(pdn); | |
c8566780 | 839 | |
14b6f00f NA |
840 | /* |
841 | * Second, if we are running on a new enough level of | |
842 | * firmware where the restore API is present, use it to | |
843 | * restore the 32-bit window, which was removed in | |
844 | * create_ddw. | |
845 | * If the API is not present, then create_ddw couldn't | |
846 | * have removed the 32-bit window in the first place, so | |
847 | * removing the DDW configuration should be sufficient. | |
848 | */ | |
849 | ddw_extensions = of_get_property(pdn, "ibm,ddw-extensions", | |
850 | NULL); | |
851 | if (ddw_extensions && ddw_extensions[0] > 0) | |
852 | __restore_default_window(of_node_to_eeh_dev(pdn), | |
853 | ddw_extensions[1]); | |
4e8b0cf4 NA |
854 | } |
855 | ||
c8566780 | 856 | return 0; |
4e8b0cf4 | 857 | } |
c8566780 | 858 | machine_arch_initcall(pseries, find_existing_ddw_windows); |
4e8b0cf4 | 859 | |
b73a635f | 860 | static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail, |
4e8b0cf4 NA |
861 | struct ddw_query_response *query) |
862 | { | |
39baadbf | 863 | struct eeh_dev *edev; |
4e8b0cf4 NA |
864 | u32 cfg_addr; |
865 | u64 buid; | |
866 | int ret; | |
867 | ||
868 | /* | |
869 | * Get the config address and phb buid of the PE window. | |
870 | * Rely on eeh to retrieve this for us. | |
871 | * Retrieve them from the pci device, not the node with the | |
872 | * dma-window property | |
873 | */ | |
39baadbf GS |
874 | edev = pci_dev_to_eeh_dev(dev); |
875 | cfg_addr = edev->config_addr; | |
876 | if (edev->pe_config_addr) | |
877 | cfg_addr = edev->pe_config_addr; | |
878 | buid = edev->phb->buid; | |
879 | ||
b73a635f | 880 | ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query, |
4e8b0cf4 NA |
881 | cfg_addr, BUID_HI(buid), BUID_LO(buid)); |
882 | dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x" | |
b73a635f | 883 | " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid), |
4e8b0cf4 NA |
884 | BUID_LO(buid), ret); |
885 | return ret; | |
886 | } | |
887 | ||
b73a635f | 888 | static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail, |
4e8b0cf4 NA |
889 | struct ddw_create_response *create, int page_shift, |
890 | int window_shift) | |
891 | { | |
39baadbf | 892 | struct eeh_dev *edev; |
4e8b0cf4 NA |
893 | u32 cfg_addr; |
894 | u64 buid; | |
895 | int ret; | |
896 | ||
897 | /* | |
898 | * Get the config address and phb buid of the PE window. | |
899 | * Rely on eeh to retrieve this for us. | |
900 | * Retrieve them from the pci device, not the node with the | |
901 | * dma-window property | |
902 | */ | |
39baadbf GS |
903 | edev = pci_dev_to_eeh_dev(dev); |
904 | cfg_addr = edev->config_addr; | |
905 | if (edev->pe_config_addr) | |
906 | cfg_addr = edev->pe_config_addr; | |
907 | buid = edev->phb->buid; | |
4e8b0cf4 NA |
908 | |
909 | do { | |
910 | /* extra outputs are LIOBN and dma-addr (hi, lo) */ | |
b73a635f | 911 | ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create, cfg_addr, |
4e8b0cf4 NA |
912 | BUID_HI(buid), BUID_LO(buid), page_shift, window_shift); |
913 | } while (rtas_busy_delay(ret)); | |
914 | dev_info(&dev->dev, | |
915 | "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d " | |
b73a635f | 916 | "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1], |
4e8b0cf4 NA |
917 | cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift, |
918 | window_shift, ret, create->liobn, create->addr_hi, create->addr_lo); | |
919 | ||
920 | return ret; | |
921 | } | |
922 | ||
25ebc45b | 923 | static void restore_default_window(struct pci_dev *dev, |
a1dabade | 924 | u32 ddw_restore_token) |
25ebc45b | 925 | { |
14b6f00f | 926 | __restore_default_window(pci_dev_to_eeh_dev(dev), ddw_restore_token); |
25ebc45b NA |
927 | } |
928 | ||
61435690 NA |
929 | struct failed_ddw_pdn { |
930 | struct device_node *pdn; | |
931 | struct list_head list; | |
932 | }; | |
933 | ||
934 | static LIST_HEAD(failed_ddw_pdn_list); | |
935 | ||
4e8b0cf4 NA |
936 | /* |
937 | * If the PE supports dynamic dma windows, and there is space for a table | |
938 | * that can map all pages in a linear offset, then setup such a table, | |
939 | * and record the dma-offset in the struct device. | |
940 | * | |
941 | * dev: the pci device we are checking | |
942 | * pdn: the parent pe node with the ibm,dma_window property | |
943 | * Future: also check if we can remap the base window for our base page size | |
944 | * | |
945 | * returns the dma offset for use by dma_set_mask | |
946 | */ | |
947 | static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn) | |
948 | { | |
949 | int len, ret; | |
950 | struct ddw_query_response query; | |
951 | struct ddw_create_response create; | |
952 | int page_shift; | |
953 | u64 dma_addr, max_addr; | |
954 | struct device_node *dn; | |
b73a635f | 955 | const u32 *uninitialized_var(ddw_avail); |
25ebc45b NA |
956 | const u32 *uninitialized_var(ddw_extensions); |
957 | u32 ddw_restore_token = 0; | |
4e8b0cf4 | 958 | struct direct_window *window; |
76730334 | 959 | struct property *win64; |
4e8b0cf4 | 960 | struct dynamic_dma_window_prop *ddwprop; |
25ebc45b NA |
961 | const void *dma_window = NULL; |
962 | unsigned long liobn, offset, size; | |
61435690 | 963 | struct failed_ddw_pdn *fpdn; |
4e8b0cf4 NA |
964 | |
965 | mutex_lock(&direct_window_init_mutex); | |
966 | ||
b73a635f | 967 | dma_addr = find_existing_ddw(pdn); |
4e8b0cf4 NA |
968 | if (dma_addr != 0) |
969 | goto out_unlock; | |
970 | ||
61435690 NA |
971 | /* |
972 | * If we already went through this for a previous function of | |
973 | * the same device and failed, we don't want to muck with the | |
974 | * DMA window again, as it will race with in-flight operations | |
975 | * and can lead to EEHs. The above mutex protects access to the | |
976 | * list. | |
977 | */ | |
978 | list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) { | |
979 | if (!strcmp(fpdn->pdn->full_name, pdn->full_name)) | |
980 | goto out_unlock; | |
981 | } | |
982 | ||
4e8b0cf4 NA |
983 | /* |
984 | * the ibm,ddw-applicable property holds the tokens for: | |
985 | * ibm,query-pe-dma-window | |
986 | * ibm,create-pe-dma-window | |
987 | * ibm,remove-pe-dma-window | |
988 | * for the given node in that order. | |
989 | * the property is actually in the parent, not the PE | |
990 | */ | |
b73a635f MM |
991 | ddw_avail = of_get_property(pdn, "ibm,ddw-applicable", &len); |
992 | if (!ddw_avail || len < 3 * sizeof(u32)) | |
4e8b0cf4 NA |
993 | goto out_unlock; |
994 | ||
25ebc45b NA |
995 | /* |
996 | * the extensions property is only required to exist in certain | |
997 | * levels of firmware and later | |
998 | * the ibm,ddw-extensions property is a list with the first | |
999 | * element containing the number of extensions and each | |
1000 | * subsequent entry is a value corresponding to that extension | |
1001 | */ | |
1002 | ddw_extensions = of_get_property(pdn, "ibm,ddw-extensions", &len); | |
1003 | if (ddw_extensions) { | |
1004 | /* | |
1005 | * each new defined extension length should be added to | |
1006 | * the top of the switch so the "earlier" entries also | |
1007 | * get picked up | |
1008 | */ | |
1009 | switch (ddw_extensions[0]) { | |
1010 | /* ibm,reset-pe-dma-windows */ | |
1011 | case 1: | |
1012 | ddw_restore_token = ddw_extensions[1]; | |
1013 | break; | |
1014 | } | |
1015 | } | |
1016 | ||
1017 | /* | |
1018 | * Only remove the existing DMA window if we can restore back to | |
1019 | * the default state. Removing the existing window maximizes the | |
1020 | * resources available to firmware for dynamic window creation. | |
1021 | */ | |
1022 | if (ddw_restore_token) { | |
1023 | dma_window = of_get_property(pdn, "ibm,dma-window", NULL); | |
1024 | of_parse_dma_window(pdn, dma_window, &liobn, &offset, &size); | |
1025 | __remove_ddw(pdn, ddw_avail, liobn); | |
1026 | } | |
1027 | ||
1028 | /* | |
4e8b0cf4 NA |
1029 | * Query if there is a second window of size to map the |
1030 | * whole partition. Query returns number of windows, largest | |
1031 | * block assigned to PE (partition endpoint), and two bitmasks | |
1032 | * of page sizes: supported and supported for migrate-dma. | |
1033 | */ | |
1034 | dn = pci_device_to_OF_node(dev); | |
b73a635f | 1035 | ret = query_ddw(dev, ddw_avail, &query); |
4e8b0cf4 | 1036 | if (ret != 0) |
25ebc45b | 1037 | goto out_restore_window; |
4e8b0cf4 NA |
1038 | |
1039 | if (query.windows_available == 0) { | |
1040 | /* | |
1041 | * no additional windows are available for this device. | |
1042 | * We might be able to reallocate the existing window, | |
1043 | * trading in for a larger page size. | |
1044 | */ | |
1045 | dev_dbg(&dev->dev, "no free dynamic windows"); | |
25ebc45b | 1046 | goto out_restore_window; |
4e8b0cf4 NA |
1047 | } |
1048 | if (query.page_size & 4) { | |
1049 | page_shift = 24; /* 16MB */ | |
1050 | } else if (query.page_size & 2) { | |
1051 | page_shift = 16; /* 64kB */ | |
1052 | } else if (query.page_size & 1) { | |
1053 | page_shift = 12; /* 4kB */ | |
1054 | } else { | |
1055 | dev_dbg(&dev->dev, "no supported direct page size in mask %x", | |
1056 | query.page_size); | |
25ebc45b | 1057 | goto out_restore_window; |
4e8b0cf4 NA |
1058 | } |
1059 | /* verify the window * number of ptes will map the partition */ | |
1060 | /* check largest block * page size > max memory hotplug addr */ | |
1061 | max_addr = memory_hotplug_max(); | |
1062 | if (query.largest_available_block < (max_addr >> page_shift)) { | |
1063 | dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u " | |
1064 | "%llu-sized pages\n", max_addr, query.largest_available_block, | |
1065 | 1ULL << page_shift); | |
25ebc45b | 1066 | goto out_restore_window; |
4e8b0cf4 NA |
1067 | } |
1068 | len = order_base_2(max_addr); | |
1069 | win64 = kzalloc(sizeof(struct property), GFP_KERNEL); | |
1070 | if (!win64) { | |
1071 | dev_info(&dev->dev, | |
1072 | "couldn't allocate property for 64bit dma window\n"); | |
25ebc45b | 1073 | goto out_restore_window; |
4e8b0cf4 NA |
1074 | } |
1075 | win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL); | |
1076 | win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL); | |
76730334 | 1077 | win64->length = sizeof(*ddwprop); |
4e8b0cf4 NA |
1078 | if (!win64->name || !win64->value) { |
1079 | dev_info(&dev->dev, | |
1080 | "couldn't allocate property name and value\n"); | |
1081 | goto out_free_prop; | |
1082 | } | |
1083 | ||
b73a635f | 1084 | ret = create_ddw(dev, ddw_avail, &create, page_shift, len); |
4e8b0cf4 NA |
1085 | if (ret != 0) |
1086 | goto out_free_prop; | |
1087 | ||
1088 | ddwprop->liobn = cpu_to_be32(create.liobn); | |
1089 | ddwprop->dma_base = cpu_to_be64(of_read_number(&create.addr_hi, 2)); | |
1090 | ddwprop->tce_shift = cpu_to_be32(page_shift); | |
1091 | ddwprop->window_shift = cpu_to_be32(len); | |
1092 | ||
1093 | dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n", | |
1094 | create.liobn, dn->full_name); | |
1095 | ||
1096 | window = kzalloc(sizeof(*window), GFP_KERNEL); | |
1097 | if (!window) | |
1098 | goto out_clear_window; | |
1099 | ||
1100 | ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT, | |
1101 | win64->value, tce_setrange_multi_pSeriesLP_walk); | |
1102 | if (ret) { | |
1103 | dev_info(&dev->dev, "failed to map direct window for %s: %d\n", | |
1104 | dn->full_name, ret); | |
7a19081f | 1105 | goto out_free_window; |
4e8b0cf4 NA |
1106 | } |
1107 | ||
79d1c712 | 1108 | ret = of_add_property(pdn, win64); |
4e8b0cf4 NA |
1109 | if (ret) { |
1110 | dev_err(&dev->dev, "unable to add dma window property for %s: %d", | |
1111 | pdn->full_name, ret); | |
7a19081f | 1112 | goto out_free_window; |
4e8b0cf4 NA |
1113 | } |
1114 | ||
1115 | window->device = pdn; | |
1116 | window->prop = ddwprop; | |
1117 | spin_lock(&direct_window_list_lock); | |
1118 | list_add(&window->list, &direct_window_list); | |
1119 | spin_unlock(&direct_window_list_lock); | |
1120 | ||
1121 | dma_addr = of_read_number(&create.addr_hi, 2); | |
1122 | goto out_unlock; | |
1123 | ||
7a19081f JL |
1124 | out_free_window: |
1125 | kfree(window); | |
1126 | ||
4e8b0cf4 NA |
1127 | out_clear_window: |
1128 | remove_ddw(pdn); | |
1129 | ||
1130 | out_free_prop: | |
1131 | kfree(win64->name); | |
1132 | kfree(win64->value); | |
1133 | kfree(win64); | |
1134 | ||
25ebc45b NA |
1135 | out_restore_window: |
1136 | if (ddw_restore_token) | |
a1dabade | 1137 | restore_default_window(dev, ddw_restore_token); |
25ebc45b | 1138 | |
61435690 NA |
1139 | fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL); |
1140 | if (!fpdn) | |
1141 | goto out_unlock; | |
1142 | fpdn->pdn = pdn; | |
1143 | list_add(&fpdn->list, &failed_ddw_pdn_list); | |
1144 | ||
4e8b0cf4 NA |
1145 | out_unlock: |
1146 | mutex_unlock(&direct_window_init_mutex); | |
1147 | return dma_addr; | |
1148 | } | |
1149 | ||
12d04eef | 1150 | static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) |
1da177e4 LT |
1151 | { |
1152 | struct device_node *pdn, *dn; | |
1153 | struct iommu_table *tbl; | |
2083f681 | 1154 | const __be32 *dma_window = NULL; |
1635317f | 1155 | struct pci_dn *pci; |
1da177e4 | 1156 | |
f7ebf352 | 1157 | pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev)); |
12d04eef | 1158 | |
1da177e4 | 1159 | /* dev setup for LPAR is a little tricky, since the device tree might |
25985edc | 1160 | * contain the dma-window properties per-device and not necessarily |
1da177e4 LT |
1161 | * for the bus. So we need to search upwards in the tree until we |
1162 | * either hit a dma-window property, OR find a parent with a table | |
1163 | * already allocated. | |
1164 | */ | |
1165 | dn = pci_device_to_OF_node(dev); | |
f7ebf352 | 1166 | pr_debug(" node is %s\n", dn->full_name); |
5d2efba6 | 1167 | |
e07102db | 1168 | for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table; |
1635317f | 1169 | pdn = pdn->parent) { |
e2eb6392 | 1170 | dma_window = of_get_property(pdn, "ibm,dma-window", NULL); |
1da177e4 LT |
1171 | if (dma_window) |
1172 | break; | |
1173 | } | |
1174 | ||
650f7b3b LV |
1175 | if (!pdn || !PCI_DN(pdn)) { |
1176 | printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: " | |
1177 | "no DMA window found for pci dev=%s dn=%s\n", | |
74a7f084 | 1178 | pci_name(dev), of_node_full_name(dn)); |
650f7b3b LV |
1179 | return; |
1180 | } | |
f7ebf352 | 1181 | pr_debug(" parent is %s\n", pdn->full_name); |
12d04eef | 1182 | |
e07102db | 1183 | pci = PCI_DN(pdn); |
1635317f | 1184 | if (!pci->iommu_table) { |
7aa241fd | 1185 | tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
ca1588e7 | 1186 | pci->phb->node); |
b8c49def | 1187 | iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window); |
ca1588e7 | 1188 | pci->iommu_table = iommu_init_table(tbl, pci->phb->node); |
5b25199e | 1189 | iommu_register_group(tbl, pci_domain_nr(pci->phb->bus), 0); |
f7ebf352 | 1190 | pr_debug(" created table: %p\n", pci->iommu_table); |
de113217 | 1191 | } else { |
f7ebf352 | 1192 | pr_debug(" found DMA window, table: %p\n", pci->iommu_table); |
1da177e4 LT |
1193 | } |
1194 | ||
738ef42e | 1195 | set_iommu_table_base(&dev->dev, pci->iommu_table); |
1da177e4 | 1196 | } |
4e8b0cf4 NA |
1197 | |
1198 | static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask) | |
1199 | { | |
1200 | bool ddw_enabled = false; | |
1201 | struct device_node *pdn, *dn; | |
1202 | struct pci_dev *pdev; | |
2083f681 | 1203 | const __be32 *dma_window = NULL; |
4e8b0cf4 NA |
1204 | u64 dma_offset; |
1205 | ||
64ac822f | 1206 | if (!dev->dma_mask) |
4e8b0cf4 NA |
1207 | return -EIO; |
1208 | ||
64ac822f MM |
1209 | if (!dev_is_pci(dev)) |
1210 | goto check_mask; | |
1211 | ||
eb0dd411 NA |
1212 | pdev = to_pci_dev(dev); |
1213 | ||
4e8b0cf4 NA |
1214 | /* only attempt to use a new window if 64-bit DMA is requested */ |
1215 | if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) { | |
4e8b0cf4 NA |
1216 | dn = pci_device_to_OF_node(pdev); |
1217 | dev_dbg(dev, "node is %s\n", dn->full_name); | |
1218 | ||
1219 | /* | |
1220 | * the device tree might contain the dma-window properties | |
25985edc | 1221 | * per-device and not necessarily for the bus. So we need to |
4e8b0cf4 NA |
1222 | * search upwards in the tree until we either hit a dma-window |
1223 | * property, OR find a parent with a table already allocated. | |
1224 | */ | |
1225 | for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table; | |
1226 | pdn = pdn->parent) { | |
1227 | dma_window = of_get_property(pdn, "ibm,dma-window", NULL); | |
1228 | if (dma_window) | |
1229 | break; | |
1230 | } | |
1231 | if (pdn && PCI_DN(pdn)) { | |
1232 | dma_offset = enable_ddw(pdev, pdn); | |
1233 | if (dma_offset != 0) { | |
1234 | dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset); | |
1235 | set_dma_offset(dev, dma_offset); | |
1236 | set_dma_ops(dev, &dma_direct_ops); | |
1237 | ddw_enabled = true; | |
1238 | } | |
1239 | } | |
1240 | } | |
1241 | ||
64ac822f MM |
1242 | /* fall back on iommu ops, restore table pointer with ops */ |
1243 | if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) { | |
1244 | dev_info(dev, "Restoring 32-bit DMA via iommu\n"); | |
4e8b0cf4 | 1245 | set_dma_ops(dev, &dma_iommu_ops); |
eb0dd411 | 1246 | pci_dma_dev_setup_pSeriesLP(pdev); |
4e8b0cf4 NA |
1247 | } |
1248 | ||
64ac822f MM |
1249 | check_mask: |
1250 | if (!dma_supported(dev, dma_mask)) | |
1251 | return -EIO; | |
1252 | ||
4e8b0cf4 NA |
1253 | *dev->dma_mask = dma_mask; |
1254 | return 0; | |
1255 | } | |
1256 | ||
6a5c7be5 MM |
1257 | static u64 dma_get_required_mask_pSeriesLP(struct device *dev) |
1258 | { | |
1259 | if (!dev->dma_mask) | |
1260 | return 0; | |
1261 | ||
1262 | if (!disable_ddw && dev_is_pci(dev)) { | |
1263 | struct pci_dev *pdev = to_pci_dev(dev); | |
1264 | struct device_node *dn; | |
1265 | ||
1266 | dn = pci_device_to_OF_node(pdev); | |
1267 | ||
1268 | /* search upwards for ibm,dma-window */ | |
1269 | for (; dn && PCI_DN(dn) && !PCI_DN(dn)->iommu_table; | |
1270 | dn = dn->parent) | |
1271 | if (of_get_property(dn, "ibm,dma-window", NULL)) | |
1272 | break; | |
1273 | /* if there is a ibm,ddw-applicable property require 64 bits */ | |
1274 | if (dn && PCI_DN(dn) && | |
1275 | of_get_property(dn, "ibm,ddw-applicable", NULL)) | |
1276 | return DMA_BIT_MASK(64); | |
1277 | } | |
1278 | ||
d24f9c69 | 1279 | return dma_iommu_ops.get_required_mask(dev); |
6a5c7be5 MM |
1280 | } |
1281 | ||
bed59275 SR |
1282 | #else /* CONFIG_PCI */ |
1283 | #define pci_dma_bus_setup_pSeries NULL | |
1284 | #define pci_dma_dev_setup_pSeries NULL | |
1285 | #define pci_dma_bus_setup_pSeriesLP NULL | |
1286 | #define pci_dma_dev_setup_pSeriesLP NULL | |
4e8b0cf4 | 1287 | #define dma_set_mask_pSeriesLP NULL |
6a5c7be5 | 1288 | #define dma_get_required_mask_pSeriesLP NULL |
bed59275 SR |
1289 | #endif /* !CONFIG_PCI */ |
1290 | ||
4e8b0cf4 NA |
1291 | static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action, |
1292 | void *data) | |
1293 | { | |
1294 | struct direct_window *window; | |
1295 | struct memory_notify *arg = data; | |
1296 | int ret = 0; | |
1297 | ||
1298 | switch (action) { | |
1299 | case MEM_GOING_ONLINE: | |
1300 | spin_lock(&direct_window_list_lock); | |
1301 | list_for_each_entry(window, &direct_window_list, list) { | |
1302 | ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn, | |
1303 | arg->nr_pages, window->prop); | |
1304 | /* XXX log error */ | |
1305 | } | |
1306 | spin_unlock(&direct_window_list_lock); | |
1307 | break; | |
1308 | case MEM_CANCEL_ONLINE: | |
1309 | case MEM_OFFLINE: | |
1310 | spin_lock(&direct_window_list_lock); | |
1311 | list_for_each_entry(window, &direct_window_list, list) { | |
1312 | ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn, | |
1313 | arg->nr_pages, window->prop); | |
1314 | /* XXX log error */ | |
1315 | } | |
1316 | spin_unlock(&direct_window_list_lock); | |
1317 | break; | |
1318 | default: | |
1319 | break; | |
1320 | } | |
1321 | if (ret && action != MEM_CANCEL_ONLINE) | |
1322 | return NOTIFY_BAD; | |
1323 | ||
1324 | return NOTIFY_OK; | |
1325 | } | |
1326 | ||
1327 | static struct notifier_block iommu_mem_nb = { | |
1328 | .notifier_call = iommu_mem_notifier, | |
1329 | }; | |
1330 | ||
bed59275 SR |
1331 | static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) |
1332 | { | |
1333 | int err = NOTIFY_OK; | |
1334 | struct device_node *np = node; | |
1335 | struct pci_dn *pci = PCI_DN(np); | |
4e8b0cf4 | 1336 | struct direct_window *window; |
bed59275 SR |
1337 | |
1338 | switch (action) { | |
1cf3d8b3 | 1339 | case OF_RECONFIG_DETACH_NODE: |
71cf1def | 1340 | remove_ddw(np); |
7372cfb8 | 1341 | if (pci && pci->iommu_table) |
68d315f5 | 1342 | iommu_free_table(pci->iommu_table, np->full_name); |
4e8b0cf4 NA |
1343 | |
1344 | spin_lock(&direct_window_list_lock); | |
1345 | list_for_each_entry(window, &direct_window_list, list) { | |
1346 | if (window->device == np) { | |
1347 | list_del(&window->list); | |
1348 | kfree(window); | |
1349 | break; | |
1350 | } | |
1351 | } | |
1352 | spin_unlock(&direct_window_list_lock); | |
bed59275 SR |
1353 | break; |
1354 | default: | |
1355 | err = NOTIFY_DONE; | |
1356 | break; | |
1357 | } | |
1358 | return err; | |
1359 | } | |
1360 | ||
1361 | static struct notifier_block iommu_reconfig_nb = { | |
1362 | .notifier_call = iommu_reconfig_notifier, | |
1363 | }; | |
1da177e4 | 1364 | |
1da177e4 LT |
1365 | /* These are called very early. */ |
1366 | void iommu_init_early_pSeries(void) | |
1367 | { | |
a8daac8a | 1368 | if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL)) |
1da177e4 | 1369 | return; |
1da177e4 | 1370 | |
57cfb814 | 1371 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1ababe11 | 1372 | if (firmware_has_feature(FW_FEATURE_MULTITCE)) { |
1da177e4 LT |
1373 | ppc_md.tce_build = tce_buildmulti_pSeriesLP; |
1374 | ppc_md.tce_free = tce_freemulti_pSeriesLP; | |
1375 | } else { | |
1376 | ppc_md.tce_build = tce_build_pSeriesLP; | |
1377 | ppc_md.tce_free = tce_free_pSeriesLP; | |
1378 | } | |
5f50867b | 1379 | ppc_md.tce_get = tce_get_pSeriesLP; |
12d04eef BH |
1380 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP; |
1381 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP; | |
4e8b0cf4 | 1382 | ppc_md.dma_set_mask = dma_set_mask_pSeriesLP; |
6a5c7be5 | 1383 | ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP; |
1da177e4 LT |
1384 | } else { |
1385 | ppc_md.tce_build = tce_build_pSeries; | |
1386 | ppc_md.tce_free = tce_free_pSeries; | |
5f50867b | 1387 | ppc_md.tce_get = tce_get_pseries; |
12d04eef BH |
1388 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries; |
1389 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries; | |
1da177e4 LT |
1390 | } |
1391 | ||
1392 | ||
1cf3d8b3 | 1393 | of_reconfig_notifier_register(&iommu_reconfig_nb); |
4e8b0cf4 | 1394 | register_memory_notifier(&iommu_mem_nb); |
1da177e4 | 1395 | |
98747770 | 1396 | set_pci_dma_ops(&dma_iommu_ops); |
1da177e4 LT |
1397 | } |
1398 | ||
4e89a2d8 WS |
1399 | static int __init disable_multitce(char *str) |
1400 | { | |
1401 | if (strcmp(str, "off") == 0 && | |
1402 | firmware_has_feature(FW_FEATURE_LPAR) && | |
1403 | firmware_has_feature(FW_FEATURE_MULTITCE)) { | |
1404 | printk(KERN_INFO "Disabling MULTITCE firmware feature\n"); | |
1405 | ppc_md.tce_build = tce_build_pSeriesLP; | |
1406 | ppc_md.tce_free = tce_free_pSeriesLP; | |
1407 | powerpc_firmware_features &= ~FW_FEATURE_MULTITCE; | |
1408 | } | |
1409 | return 1; | |
1410 | } | |
1411 | ||
1412 | __setup("multitce=", disable_multitce); |