Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
3 | * | |
4 | * Rewrite, cleanup: | |
5 | * | |
91f14480 | 6 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
1da177e4 LT |
7 | * |
8 | * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <linux/config.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/types.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/string.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <asm/io.h> | |
36 | #include <asm/prom.h> | |
37 | #include <asm/rtas.h> | |
1da177e4 LT |
38 | #include <asm/iommu.h> |
39 | #include <asm/pci-bridge.h> | |
40 | #include <asm/machdep.h> | |
41 | #include <asm/abs_addr.h> | |
1da177e4 | 42 | #include <asm/pSeries_reconfig.h> |
1ababe11 | 43 | #include <asm/firmware.h> |
c707ffcf | 44 | #include <asm/tce.h> |
d387899f | 45 | #include <asm/ppc-pci.h> |
2249ca9d | 46 | #include <asm/udbg.h> |
1da177e4 | 47 | |
a1218720 ME |
48 | #include "plpar_wrappers.h" |
49 | ||
1da177e4 LT |
50 | #define DBG(fmt...) |
51 | ||
1da177e4 LT |
52 | static void tce_build_pSeries(struct iommu_table *tbl, long index, |
53 | long npages, unsigned long uaddr, | |
54 | enum dma_data_direction direction) | |
55 | { | |
56 | union tce_entry t; | |
57 | union tce_entry *tp; | |
58 | ||
d0035c62 OJ |
59 | index <<= TCE_PAGE_FACTOR; |
60 | npages <<= TCE_PAGE_FACTOR; | |
61 | ||
1da177e4 LT |
62 | t.te_word = 0; |
63 | t.te_rdwr = 1; // Read allowed | |
64 | ||
65 | if (direction != DMA_TO_DEVICE) | |
66 | t.te_pciwr = 1; | |
67 | ||
68 | tp = ((union tce_entry *)tbl->it_base) + index; | |
69 | ||
70 | while (npages--) { | |
71 | /* can't move this out since we might cross LMB boundary */ | |
d0035c62 | 72 | t.te_rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
1da177e4 LT |
73 | |
74 | tp->te_word = t.te_word; | |
75 | ||
d0035c62 | 76 | uaddr += TCE_PAGE_SIZE; |
1da177e4 LT |
77 | tp++; |
78 | } | |
79 | } | |
80 | ||
81 | ||
82 | static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) | |
83 | { | |
84 | union tce_entry t; | |
85 | union tce_entry *tp; | |
86 | ||
d0035c62 OJ |
87 | npages <<= TCE_PAGE_FACTOR; |
88 | index <<= TCE_PAGE_FACTOR; | |
89 | ||
1da177e4 LT |
90 | t.te_word = 0; |
91 | tp = ((union tce_entry *)tbl->it_base) + index; | |
92 | ||
93 | while (npages--) { | |
94 | tp->te_word = t.te_word; | |
95 | ||
96 | tp++; | |
97 | } | |
98 | } | |
99 | ||
100 | ||
101 | static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
102 | long npages, unsigned long uaddr, | |
103 | enum dma_data_direction direction) | |
104 | { | |
105 | u64 rc; | |
106 | union tce_entry tce; | |
107 | ||
cc8b5c96 MO |
108 | tcenum <<= TCE_PAGE_FACTOR; |
109 | npages <<= TCE_PAGE_FACTOR; | |
110 | ||
1da177e4 | 111 | tce.te_word = 0; |
d0035c62 | 112 | tce.te_rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
1da177e4 LT |
113 | tce.te_rdwr = 1; |
114 | if (direction != DMA_TO_DEVICE) | |
115 | tce.te_pciwr = 1; | |
116 | ||
117 | while (npages--) { | |
118 | rc = plpar_tce_put((u64)tbl->it_index, | |
119 | (u64)tcenum << 12, | |
120 | tce.te_word ); | |
121 | ||
122 | if (rc && printk_ratelimit()) { | |
123 | printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
124 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
125 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
126 | printk("\ttce val = 0x%lx\n", tce.te_word ); | |
127 | show_stack(current, (unsigned long *)__get_SP()); | |
128 | } | |
129 | ||
130 | tcenum++; | |
131 | tce.te_rpn++; | |
132 | } | |
133 | } | |
134 | ||
135 | static DEFINE_PER_CPU(void *, tce_page) = NULL; | |
136 | ||
137 | static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
138 | long npages, unsigned long uaddr, | |
139 | enum dma_data_direction direction) | |
140 | { | |
141 | u64 rc; | |
142 | union tce_entry tce, *tcep; | |
143 | long l, limit; | |
144 | ||
6fbb618f | 145 | if (TCE_PAGE_FACTOR == 0 && npages == 1) |
1da177e4 LT |
146 | return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, |
147 | direction); | |
148 | ||
149 | tcep = __get_cpu_var(tce_page); | |
150 | ||
151 | /* This is safe to do since interrupts are off when we're called | |
152 | * from iommu_alloc{,_sg}() | |
153 | */ | |
154 | if (!tcep) { | |
155 | tcep = (void *)__get_free_page(GFP_ATOMIC); | |
156 | /* If allocation fails, fall back to the loop implementation */ | |
157 | if (!tcep) | |
158 | return tce_build_pSeriesLP(tbl, tcenum, npages, | |
159 | uaddr, direction); | |
160 | __get_cpu_var(tce_page) = tcep; | |
161 | } | |
162 | ||
cc8b5c96 MO |
163 | tcenum <<= TCE_PAGE_FACTOR; |
164 | npages <<= TCE_PAGE_FACTOR; | |
165 | ||
1da177e4 | 166 | tce.te_word = 0; |
d0035c62 | 167 | tce.te_rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
1da177e4 LT |
168 | tce.te_rdwr = 1; |
169 | if (direction != DMA_TO_DEVICE) | |
170 | tce.te_pciwr = 1; | |
171 | ||
172 | /* We can map max one pageful of TCEs at a time */ | |
173 | do { | |
174 | /* | |
175 | * Set up the page with TCE data, looping through and setting | |
176 | * the values. | |
177 | */ | |
d0035c62 | 178 | limit = min_t(long, npages, 4096/sizeof(union tce_entry)); |
1da177e4 LT |
179 | |
180 | for (l = 0; l < limit; l++) { | |
181 | tcep[l] = tce; | |
182 | tce.te_rpn++; | |
183 | } | |
184 | ||
185 | rc = plpar_tce_put_indirect((u64)tbl->it_index, | |
186 | (u64)tcenum << 12, | |
187 | (u64)virt_to_abs(tcep), | |
188 | limit); | |
189 | ||
190 | npages -= limit; | |
191 | tcenum += limit; | |
192 | } while (npages > 0 && !rc); | |
193 | ||
194 | if (rc && printk_ratelimit()) { | |
195 | printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
196 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
197 | printk("\tnpages = 0x%lx\n", (u64)npages); | |
198 | printk("\ttce[0] val = 0x%lx\n", tcep[0].te_word); | |
199 | show_stack(current, (unsigned long *)__get_SP()); | |
200 | } | |
201 | } | |
202 | ||
203 | static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
204 | { | |
205 | u64 rc; | |
206 | union tce_entry tce; | |
207 | ||
d0035c62 OJ |
208 | tcenum <<= TCE_PAGE_FACTOR; |
209 | npages <<= TCE_PAGE_FACTOR; | |
210 | ||
1da177e4 LT |
211 | tce.te_word = 0; |
212 | ||
213 | while (npages--) { | |
214 | rc = plpar_tce_put((u64)tbl->it_index, | |
215 | (u64)tcenum << 12, | |
216 | tce.te_word); | |
217 | ||
218 | if (rc && printk_ratelimit()) { | |
219 | printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
220 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
221 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
222 | printk("\ttce val = 0x%lx\n", tce.te_word ); | |
223 | show_stack(current, (unsigned long *)__get_SP()); | |
224 | } | |
225 | ||
226 | tcenum++; | |
227 | } | |
228 | } | |
229 | ||
230 | ||
231 | static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
232 | { | |
233 | u64 rc; | |
234 | union tce_entry tce; | |
235 | ||
d0035c62 OJ |
236 | tcenum <<= TCE_PAGE_FACTOR; |
237 | npages <<= TCE_PAGE_FACTOR; | |
238 | ||
1da177e4 LT |
239 | tce.te_word = 0; |
240 | ||
241 | rc = plpar_tce_stuff((u64)tbl->it_index, | |
242 | (u64)tcenum << 12, | |
243 | tce.te_word, | |
244 | npages); | |
245 | ||
246 | if (rc && printk_ratelimit()) { | |
247 | printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); | |
248 | printk("\trc = %ld\n", rc); | |
249 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
250 | printk("\tnpages = 0x%lx\n", (u64)npages); | |
251 | printk("\ttce val = 0x%lx\n", tce.te_word ); | |
252 | show_stack(current, (unsigned long *)__get_SP()); | |
253 | } | |
254 | } | |
255 | ||
256 | static void iommu_table_setparms(struct pci_controller *phb, | |
257 | struct device_node *dn, | |
258 | struct iommu_table *tbl) | |
259 | { | |
260 | struct device_node *node; | |
261 | unsigned long *basep; | |
262 | unsigned int *sizep; | |
263 | ||
264 | node = (struct device_node *)phb->arch_data; | |
265 | ||
266 | basep = (unsigned long *)get_property(node, "linux,tce-base", NULL); | |
267 | sizep = (unsigned int *)get_property(node, "linux,tce-size", NULL); | |
268 | if (basep == NULL || sizep == NULL) { | |
269 | printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has " | |
270 | "missing tce entries !\n", dn->full_name); | |
271 | return; | |
272 | } | |
273 | ||
274 | tbl->it_base = (unsigned long)__va(*basep); | |
275 | memset((void *)tbl->it_base, 0, *sizep); | |
276 | ||
277 | tbl->it_busno = phb->bus->number; | |
278 | ||
279 | /* Units of tce entries */ | |
280 | tbl->it_offset = phb->dma_window_base_cur >> PAGE_SHIFT; | |
281 | ||
282 | /* Test if we are going over 2GB of DMA space */ | |
3c2822cc OJ |
283 | if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) { |
284 | udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); | |
1da177e4 | 285 | panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); |
3c2822cc | 286 | } |
1da177e4 LT |
287 | |
288 | phb->dma_window_base_cur += phb->dma_window_size; | |
289 | ||
290 | /* Set the tce table size - measured in entries */ | |
291 | tbl->it_size = phb->dma_window_size >> PAGE_SHIFT; | |
292 | ||
293 | tbl->it_index = 0; | |
294 | tbl->it_blocksize = 16; | |
295 | tbl->it_type = TCE_PCI; | |
296 | } | |
297 | ||
298 | /* | |
299 | * iommu_table_setparms_lpar | |
300 | * | |
301 | * Function: On pSeries LPAR systems, return TCE table info, given a pci bus. | |
302 | * | |
303 | * ToDo: properly interpret the ibm,dma-window property. The definition is: | |
304 | * logical-bus-number (1 word) | |
305 | * phys-address (#address-cells words) | |
306 | * size (#cell-size words) | |
307 | * | |
308 | * Currently we hard code these sizes (more or less). | |
309 | */ | |
310 | static void iommu_table_setparms_lpar(struct pci_controller *phb, | |
311 | struct device_node *dn, | |
312 | struct iommu_table *tbl, | |
313 | unsigned int *dma_window) | |
314 | { | |
1635317f | 315 | tbl->it_busno = PCI_DN(dn)->bussubno; |
1da177e4 LT |
316 | |
317 | /* TODO: Parse field size properties properly. */ | |
318 | tbl->it_size = (((unsigned long)dma_window[4] << 32) | | |
319 | (unsigned long)dma_window[5]) >> PAGE_SHIFT; | |
320 | tbl->it_offset = (((unsigned long)dma_window[2] << 32) | | |
321 | (unsigned long)dma_window[3]) >> PAGE_SHIFT; | |
322 | tbl->it_base = 0; | |
323 | tbl->it_index = dma_window[0]; | |
324 | tbl->it_blocksize = 16; | |
325 | tbl->it_type = TCE_PCI; | |
326 | } | |
327 | ||
328 | static void iommu_bus_setup_pSeries(struct pci_bus *bus) | |
329 | { | |
3c2822cc | 330 | struct device_node *dn; |
1da177e4 | 331 | struct iommu_table *tbl; |
3c2822cc OJ |
332 | struct device_node *isa_dn, *isa_dn_orig; |
333 | struct device_node *tmp; | |
334 | struct pci_dn *pci; | |
335 | int children; | |
1da177e4 LT |
336 | |
337 | DBG("iommu_bus_setup_pSeries, bus %p, bus->self %p\n", bus, bus->self); | |
338 | ||
3c2822cc OJ |
339 | dn = pci_bus_to_OF_node(bus); |
340 | pci = PCI_DN(dn); | |
341 | ||
342 | if (bus->self) { | |
343 | /* This is not a root bus, any setup will be done for the | |
344 | * device-side of the bridge in iommu_dev_setup_pSeries(). | |
345 | */ | |
346 | return; | |
347 | } | |
348 | ||
349 | /* Check if the ISA bus on the system is under | |
350 | * this PHB. | |
1da177e4 | 351 | */ |
3c2822cc | 352 | isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa"); |
1da177e4 | 353 | |
3c2822cc OJ |
354 | while (isa_dn && isa_dn != dn) |
355 | isa_dn = isa_dn->parent; | |
356 | ||
357 | if (isa_dn_orig) | |
358 | of_node_put(isa_dn_orig); | |
1da177e4 | 359 | |
3c2822cc OJ |
360 | /* Count number of direct PCI children of the PHB. |
361 | * All PCI device nodes have class-code property, so it's | |
362 | * an easy way to find them. | |
363 | */ | |
364 | for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling) | |
365 | if (get_property(tmp, "class-code", NULL)) | |
366 | children++; | |
1da177e4 | 367 | |
3c2822cc | 368 | DBG("Children: %d\n", children); |
1da177e4 | 369 | |
3c2822cc OJ |
370 | /* Calculate amount of DMA window per slot. Each window must be |
371 | * a power of two (due to pci_alloc_consistent requirements). | |
372 | * | |
373 | * Keep 256MB aside for PHBs with ISA. | |
374 | */ | |
1da177e4 | 375 | |
3c2822cc OJ |
376 | if (!isa_dn) { |
377 | /* No ISA/IDE - just set window size and return */ | |
378 | pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ | |
379 | ||
380 | while (pci->phb->dma_window_size * children > 0x80000000ul) | |
381 | pci->phb->dma_window_size >>= 1; | |
f951da37 AB |
382 | DBG("No ISA/IDE, window size is 0x%lx\n", |
383 | pci->phb->dma_window_size); | |
3c2822cc OJ |
384 | pci->phb->dma_window_base_cur = 0; |
385 | ||
386 | return; | |
1da177e4 | 387 | } |
3c2822cc OJ |
388 | |
389 | /* If we have ISA, then we probably have an IDE | |
390 | * controller too. Allocate a 128MB table but | |
391 | * skip the first 128MB to avoid stepping on ISA | |
392 | * space. | |
393 | */ | |
394 | pci->phb->dma_window_size = 0x8000000ul; | |
395 | pci->phb->dma_window_base_cur = 0x8000000ul; | |
396 | ||
397 | tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL); | |
398 | ||
399 | iommu_table_setparms(pci->phb, dn, tbl); | |
400 | pci->iommu_table = iommu_init_table(tbl); | |
401 | ||
402 | /* Divide the rest (1.75GB) among the children */ | |
403 | pci->phb->dma_window_size = 0x80000000ul; | |
404 | while (pci->phb->dma_window_size * children > 0x70000000ul) | |
405 | pci->phb->dma_window_size >>= 1; | |
406 | ||
f951da37 | 407 | DBG("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size); |
3c2822cc | 408 | |
1da177e4 LT |
409 | } |
410 | ||
411 | ||
412 | static void iommu_bus_setup_pSeriesLP(struct pci_bus *bus) | |
413 | { | |
414 | struct iommu_table *tbl; | |
415 | struct device_node *dn, *pdn; | |
1635317f | 416 | struct pci_dn *ppci; |
1da177e4 LT |
417 | unsigned int *dma_window = NULL; |
418 | ||
419 | DBG("iommu_bus_setup_pSeriesLP, bus %p, bus->self %p\n", bus, bus->self); | |
420 | ||
421 | dn = pci_bus_to_OF_node(bus); | |
422 | ||
423 | /* Find nearest ibm,dma-window, walking up the device tree */ | |
424 | for (pdn = dn; pdn != NULL; pdn = pdn->parent) { | |
425 | dma_window = (unsigned int *)get_property(pdn, "ibm,dma-window", NULL); | |
426 | if (dma_window != NULL) | |
427 | break; | |
428 | } | |
429 | ||
430 | if (dma_window == NULL) { | |
431 | DBG("iommu_bus_setup_pSeriesLP: bus %s seems to have no ibm,dma-window property\n", dn->full_name); | |
432 | return; | |
433 | } | |
434 | ||
e07102db | 435 | ppci = PCI_DN(pdn); |
1635317f | 436 | if (!ppci->iommu_table) { |
1da177e4 LT |
437 | /* Bussubno hasn't been copied yet. |
438 | * Do it now because iommu_table_setparms_lpar needs it. | |
439 | */ | |
1635317f PM |
440 | |
441 | ppci->bussubno = bus->number; | |
1da177e4 LT |
442 | |
443 | tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table), | |
444 | GFP_KERNEL); | |
445 | ||
1635317f | 446 | iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window); |
1da177e4 | 447 | |
1635317f | 448 | ppci->iommu_table = iommu_init_table(tbl); |
1da177e4 LT |
449 | } |
450 | ||
451 | if (pdn != dn) | |
1635317f | 452 | PCI_DN(dn)->iommu_table = ppci->iommu_table; |
1da177e4 LT |
453 | } |
454 | ||
455 | ||
456 | static void iommu_dev_setup_pSeries(struct pci_dev *dev) | |
457 | { | |
458 | struct device_node *dn, *mydn; | |
3c2822cc | 459 | struct iommu_table *tbl; |
1da177e4 | 460 | |
f951da37 | 461 | DBG("iommu_dev_setup_pSeries, dev %p (%s)\n", dev, pci_name(dev)); |
1da177e4 | 462 | |
1da177e4 LT |
463 | mydn = dn = pci_device_to_OF_node(dev); |
464 | ||
3c2822cc OJ |
465 | /* If we're the direct child of a root bus, then we need to allocate |
466 | * an iommu table ourselves. The bus setup code should have setup | |
467 | * the window sizes already. | |
468 | */ | |
469 | if (!dev->bus->self) { | |
470 | DBG(" --> first child, no bridge. Allocating iommu table.\n"); | |
471 | tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL); | |
472 | iommu_table_setparms(PCI_DN(dn)->phb, dn, tbl); | |
473 | PCI_DN(mydn)->iommu_table = iommu_init_table(tbl); | |
474 | ||
475 | return; | |
476 | } | |
477 | ||
478 | /* If this device is further down the bus tree, search upwards until | |
479 | * an already allocated iommu table is found and use that. | |
480 | */ | |
481 | ||
e07102db | 482 | while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL) |
1da177e4 LT |
483 | dn = dn->parent; |
484 | ||
e07102db | 485 | if (dn && PCI_DN(dn)) { |
1635317f | 486 | PCI_DN(mydn)->iommu_table = PCI_DN(dn)->iommu_table; |
1da177e4 | 487 | } else { |
f951da37 | 488 | DBG("iommu_dev_setup_pSeries, dev %p (%s) has no iommu table\n", dev, pci_name(dev)); |
1da177e4 LT |
489 | } |
490 | } | |
491 | ||
492 | static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) | |
493 | { | |
494 | int err = NOTIFY_OK; | |
495 | struct device_node *np = node; | |
e07102db | 496 | struct pci_dn *pci = PCI_DN(np); |
1da177e4 LT |
497 | |
498 | switch (action) { | |
499 | case PSERIES_RECONFIG_REMOVE: | |
8902e87f | 500 | if (pci && pci->iommu_table && |
1da177e4 LT |
501 | get_property(np, "ibm,dma-window", NULL)) |
502 | iommu_free_table(np); | |
503 | break; | |
504 | default: | |
505 | err = NOTIFY_DONE; | |
506 | break; | |
507 | } | |
508 | return err; | |
509 | } | |
510 | ||
511 | static struct notifier_block iommu_reconfig_nb = { | |
512 | .notifier_call = iommu_reconfig_notifier, | |
513 | }; | |
514 | ||
515 | static void iommu_dev_setup_pSeriesLP(struct pci_dev *dev) | |
516 | { | |
517 | struct device_node *pdn, *dn; | |
518 | struct iommu_table *tbl; | |
519 | int *dma_window = NULL; | |
1635317f | 520 | struct pci_dn *pci; |
1da177e4 | 521 | |
f951da37 | 522 | DBG("iommu_dev_setup_pSeriesLP, dev %p (%s)\n", dev, pci_name(dev)); |
1da177e4 LT |
523 | |
524 | /* dev setup for LPAR is a little tricky, since the device tree might | |
525 | * contain the dma-window properties per-device and not neccesarily | |
526 | * for the bus. So we need to search upwards in the tree until we | |
527 | * either hit a dma-window property, OR find a parent with a table | |
528 | * already allocated. | |
529 | */ | |
530 | dn = pci_device_to_OF_node(dev); | |
531 | ||
e07102db | 532 | for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table; |
1635317f PM |
533 | pdn = pdn->parent) { |
534 | dma_window = (unsigned int *) | |
535 | get_property(pdn, "ibm,dma-window", NULL); | |
1da177e4 LT |
536 | if (dma_window) |
537 | break; | |
538 | } | |
539 | ||
540 | /* Check for parent == NULL so we don't try to setup the empty EADS | |
541 | * slots on POWER4 machines. | |
542 | */ | |
543 | if (dma_window == NULL || pdn->parent == NULL) { | |
586a90eb AB |
544 | DBG("No dma window for device, linking to parent\n"); |
545 | PCI_DN(dn)->iommu_table = PCI_DN(pdn)->iommu_table; | |
1da177e4 LT |
546 | return; |
547 | } else { | |
548 | DBG("Found DMA window, allocating table\n"); | |
549 | } | |
550 | ||
e07102db | 551 | pci = PCI_DN(pdn); |
1635317f | 552 | if (!pci->iommu_table) { |
1da177e4 | 553 | /* iommu_table_setparms_lpar needs bussubno. */ |
1635317f | 554 | pci->bussubno = pci->phb->bus->number; |
1da177e4 LT |
555 | |
556 | tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table), | |
557 | GFP_KERNEL); | |
558 | ||
1635317f | 559 | iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window); |
1da177e4 | 560 | |
1635317f | 561 | pci->iommu_table = iommu_init_table(tbl); |
1da177e4 LT |
562 | } |
563 | ||
564 | if (pdn != dn) | |
1635317f | 565 | PCI_DN(dn)->iommu_table = pci->iommu_table; |
1da177e4 LT |
566 | } |
567 | ||
568 | static void iommu_bus_setup_null(struct pci_bus *b) { } | |
569 | static void iommu_dev_setup_null(struct pci_dev *d) { } | |
570 | ||
571 | /* These are called very early. */ | |
572 | void iommu_init_early_pSeries(void) | |
573 | { | |
574 | if (of_chosen && get_property(of_chosen, "linux,iommu-off", NULL)) { | |
575 | /* Direct I/O, IOMMU off */ | |
576 | ppc_md.iommu_dev_setup = iommu_dev_setup_null; | |
577 | ppc_md.iommu_bus_setup = iommu_bus_setup_null; | |
578 | pci_direct_iommu_init(); | |
579 | ||
580 | return; | |
581 | } | |
582 | ||
57cfb814 | 583 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1ababe11 | 584 | if (firmware_has_feature(FW_FEATURE_MULTITCE)) { |
1da177e4 LT |
585 | ppc_md.tce_build = tce_buildmulti_pSeriesLP; |
586 | ppc_md.tce_free = tce_freemulti_pSeriesLP; | |
587 | } else { | |
588 | ppc_md.tce_build = tce_build_pSeriesLP; | |
589 | ppc_md.tce_free = tce_free_pSeriesLP; | |
590 | } | |
591 | ppc_md.iommu_bus_setup = iommu_bus_setup_pSeriesLP; | |
592 | ppc_md.iommu_dev_setup = iommu_dev_setup_pSeriesLP; | |
593 | } else { | |
594 | ppc_md.tce_build = tce_build_pSeries; | |
595 | ppc_md.tce_free = tce_free_pSeries; | |
596 | ppc_md.iommu_bus_setup = iommu_bus_setup_pSeries; | |
597 | ppc_md.iommu_dev_setup = iommu_dev_setup_pSeries; | |
598 | } | |
599 | ||
600 | ||
601 | pSeries_reconfig_notifier_register(&iommu_reconfig_nb); | |
602 | ||
603 | pci_iommu_init(); | |
604 | } | |
605 |