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f2a0bd37 VB |
1 | /* |
2 | * General Purpose functions for the global management of the | |
3 | * Communication Processor Module. | |
4 | * Copyright (c) 1997 Dan error_act (dmalek@jlc.net) | |
5 | * | |
6 | * In addition to the individual control of the communication | |
7 | * channels, there are a few functions that globally affect the | |
8 | * communication processor. | |
9 | * | |
10 | * Buffer descriptors must be allocated from the dual ported memory | |
11 | * space. The allocator for that is here. When the communication | |
12 | * process is reset, we reclaim the memory available. There is | |
13 | * currently no deallocator for this memory. | |
14 | * The amount of space available is platform dependent. On the | |
15 | * MBX, the EPPC software loads additional microcode into the | |
16 | * communication processor, and uses some of the DP ram for this | |
17 | * purpose. Current, the first 512 bytes and the last 256 bytes of | |
18 | * memory are used. Right now I am conservative and only use the | |
19 | * memory that can never be used for microcode. If there are | |
20 | * applications that require more DP ram, we can expand the boundaries | |
21 | * but then we have to be careful of any downloaded microcode. | |
22 | */ | |
23 | #include <linux/errno.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/param.h> | |
28 | #include <linux/string.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/irq.h> | |
32 | #include <linux/module.h> | |
dc2380ec | 33 | #include <linux/spinlock.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
f2a0bd37 VB |
35 | #include <asm/page.h> |
36 | #include <asm/pgtable.h> | |
37 | #include <asm/8xx_immap.h> | |
b5677d84 | 38 | #include <asm/cpm1.h> |
f2a0bd37 VB |
39 | #include <asm/io.h> |
40 | #include <asm/tlbflush.h> | |
41 | #include <asm/rheap.h> | |
42 | #include <asm/prom.h> | |
15f8c604 | 43 | #include <asm/cpm.h> |
f2a0bd37 VB |
44 | |
45 | #include <asm/fs_pd.h> | |
46 | ||
dc2380ec JF |
47 | #ifdef CONFIG_8xx_GPIO |
48 | #include <linux/of_gpio.h> | |
49 | #endif | |
50 | ||
f2a0bd37 VB |
51 | #define CPM_MAP_SIZE (0x4000) |
52 | ||
fb533d0c SW |
53 | cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */ |
54 | immap_t __iomem *mpc8xx_immr; | |
55 | static cpic8xx_t __iomem *cpic_reg; | |
f2a0bd37 | 56 | |
bae1d8f1 | 57 | static struct irq_domain *cpm_pic_host; |
f2a0bd37 | 58 | |
a2073d54 | 59 | static void cpm_mask_irq(struct irq_data *d) |
f2a0bd37 | 60 | { |
476eb491 | 61 | unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); |
f2a0bd37 VB |
62 | |
63 | clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); | |
64 | } | |
65 | ||
a2073d54 | 66 | static void cpm_unmask_irq(struct irq_data *d) |
f2a0bd37 | 67 | { |
476eb491 | 68 | unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); |
f2a0bd37 VB |
69 | |
70 | setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); | |
71 | } | |
72 | ||
a2073d54 | 73 | static void cpm_end_irq(struct irq_data *d) |
f2a0bd37 | 74 | { |
476eb491 | 75 | unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); |
f2a0bd37 VB |
76 | |
77 | out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec)); | |
78 | } | |
79 | ||
80 | static struct irq_chip cpm_pic = { | |
fc380c0c | 81 | .name = "CPM PIC", |
a2073d54 LB |
82 | .irq_mask = cpm_mask_irq, |
83 | .irq_unmask = cpm_unmask_irq, | |
84 | .irq_eoi = cpm_end_irq, | |
f2a0bd37 VB |
85 | }; |
86 | ||
87 | int cpm_get_irq(void) | |
88 | { | |
89 | int cpm_vec; | |
90 | ||
91 | /* Get the vector by setting the ACK bit and then reading | |
92 | * the register. | |
93 | */ | |
94 | out_be16(&cpic_reg->cpic_civr, 1); | |
95 | cpm_vec = in_be16(&cpic_reg->cpic_civr); | |
96 | cpm_vec >>= 11; | |
97 | ||
98 | return irq_linear_revmap(cpm_pic_host, cpm_vec); | |
99 | } | |
100 | ||
bae1d8f1 | 101 | static int cpm_pic_host_map(struct irq_domain *h, unsigned int virq, |
f2a0bd37 VB |
102 | irq_hw_number_t hw) |
103 | { | |
104 | pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw); | |
105 | ||
98488db9 | 106 | irq_set_status_flags(virq, IRQ_LEVEL); |
ec775d0e | 107 | irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq); |
f2a0bd37 VB |
108 | return 0; |
109 | } | |
110 | ||
111 | /* The CPM can generate the error interrupt when there is a race condition | |
112 | * between generating and masking interrupts. All we have to do is ACK it | |
113 | * and return. This is a no-op function so we don't need any special | |
114 | * tests in the interrupt handler. | |
115 | */ | |
4b218e9b | 116 | static irqreturn_t cpm_error_interrupt(int irq, void *dev) |
f2a0bd37 VB |
117 | { |
118 | return IRQ_HANDLED; | |
119 | } | |
120 | ||
121 | static struct irqaction cpm_error_irqaction = { | |
122 | .handler = cpm_error_interrupt, | |
f2a0bd37 VB |
123 | .name = "error", |
124 | }; | |
125 | ||
9f70b8eb | 126 | static const struct irq_domain_ops cpm_pic_host_ops = { |
f2a0bd37 VB |
127 | .map = cpm_pic_host_map, |
128 | }; | |
129 | ||
130 | unsigned int cpm_pic_init(void) | |
131 | { | |
132 | struct device_node *np = NULL; | |
133 | struct resource res; | |
134 | unsigned int sirq = NO_IRQ, hwirq, eirq; | |
135 | int ret; | |
136 | ||
137 | pr_debug("cpm_pic_init\n"); | |
138 | ||
fb533d0c SW |
139 | np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic"); |
140 | if (np == NULL) | |
141 | np = of_find_compatible_node(NULL, "cpm-pic", "CPM"); | |
f2a0bd37 VB |
142 | if (np == NULL) { |
143 | printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n"); | |
144 | return sirq; | |
145 | } | |
fb533d0c | 146 | |
f2a0bd37 VB |
147 | ret = of_address_to_resource(np, 0, &res); |
148 | if (ret) | |
149 | goto end; | |
150 | ||
28f65c11 | 151 | cpic_reg = ioremap(res.start, resource_size(&res)); |
f2a0bd37 VB |
152 | if (cpic_reg == NULL) |
153 | goto end; | |
154 | ||
155 | sirq = irq_of_parse_and_map(np, 0); | |
156 | if (sirq == NO_IRQ) | |
157 | goto end; | |
158 | ||
159 | /* Initialize the CPM interrupt controller. */ | |
476eb491 | 160 | hwirq = (unsigned int)virq_to_hw(sirq); |
f2a0bd37 VB |
161 | out_be32(&cpic_reg->cpic_cicr, |
162 | (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | | |
163 | ((hwirq/2) << 13) | CICR_HP_MASK); | |
164 | ||
165 | out_be32(&cpic_reg->cpic_cimr, 0); | |
166 | ||
a8db8cf0 | 167 | cpm_pic_host = irq_domain_add_linear(np, 64, &cpm_pic_host_ops, NULL); |
f2a0bd37 VB |
168 | if (cpm_pic_host == NULL) { |
169 | printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n"); | |
170 | sirq = NO_IRQ; | |
171 | goto end; | |
172 | } | |
f2a0bd37 VB |
173 | |
174 | /* Install our own error handler. */ | |
fb533d0c SW |
175 | np = of_find_compatible_node(NULL, NULL, "fsl,cpm1"); |
176 | if (np == NULL) | |
177 | np = of_find_node_by_type(NULL, "cpm"); | |
f2a0bd37 VB |
178 | if (np == NULL) { |
179 | printk(KERN_ERR "CPM PIC init: can not find cpm node\n"); | |
180 | goto end; | |
181 | } | |
fb533d0c | 182 | |
4b218e9b | 183 | eirq = irq_of_parse_and_map(np, 0); |
f2a0bd37 VB |
184 | if (eirq == NO_IRQ) |
185 | goto end; | |
186 | ||
187 | if (setup_irq(eirq, &cpm_error_irqaction)) | |
188 | printk(KERN_ERR "Could not allocate CPM error IRQ!"); | |
189 | ||
190 | setbits32(&cpic_reg->cpic_cicr, CICR_IEN); | |
191 | ||
192 | end: | |
193 | of_node_put(np); | |
194 | return sirq; | |
195 | } | |
196 | ||
15f8c604 | 197 | void __init cpm_reset(void) |
f2a0bd37 | 198 | { |
fb533d0c | 199 | sysconf8xx_t __iomem *siu_conf; |
f2a0bd37 | 200 | |
fb533d0c SW |
201 | mpc8xx_immr = ioremap(get_immrbase(), 0x4000); |
202 | if (!mpc8xx_immr) { | |
203 | printk(KERN_CRIT "Could not map IMMR\n"); | |
204 | return; | |
205 | } | |
f2a0bd37 | 206 | |
fb533d0c SW |
207 | cpmp = &mpc8xx_immr->im_cpm; |
208 | ||
209 | #ifndef CONFIG_PPC_EARLY_DEBUG_CPM | |
f2a0bd37 VB |
210 | /* Perform a reset. |
211 | */ | |
fb533d0c | 212 | out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG); |
f2a0bd37 VB |
213 | |
214 | /* Wait for it. | |
215 | */ | |
fb533d0c SW |
216 | while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG); |
217 | #endif | |
f2a0bd37 | 218 | |
fb533d0c SW |
219 | #ifdef CONFIG_UCODE_PATCH |
220 | cpm_load_patch(cpmp); | |
f2a0bd37 VB |
221 | #endif |
222 | ||
223 | /* Set SDMA Bus Request priority 5. | |
224 | * On 860T, this also enables FEC priority 6. I am not sure | |
25985edc | 225 | * this is what we really want for some applications, but the |
f2a0bd37 VB |
226 | * manual recommends it. |
227 | * Bit 25, FAM can also be set to use FEC aggressive mode (860T). | |
228 | */ | |
fb533d0c | 229 | siu_conf = immr_map(im_siu_conf); |
f2a0bd37 VB |
230 | out_be32(&siu_conf->sc_sdcr, 1); |
231 | immr_unmap(siu_conf); | |
232 | ||
15f8c604 | 233 | cpm_muram_init(); |
f2a0bd37 VB |
234 | } |
235 | ||
362f9b6f JF |
236 | static DEFINE_SPINLOCK(cmd_lock); |
237 | ||
238 | #define MAX_CR_CMD_LOOPS 10000 | |
239 | ||
240 | int cpm_command(u32 command, u8 opcode) | |
241 | { | |
242 | int i, ret; | |
243 | unsigned long flags; | |
244 | ||
245 | if (command & 0xffffff0f) | |
246 | return -EINVAL; | |
247 | ||
248 | spin_lock_irqsave(&cmd_lock, flags); | |
249 | ||
250 | ret = 0; | |
251 | out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8)); | |
252 | for (i = 0; i < MAX_CR_CMD_LOOPS; i++) | |
253 | if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0) | |
254 | goto out; | |
255 | ||
e48b1b45 | 256 | printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__); |
362f9b6f JF |
257 | ret = -EIO; |
258 | out: | |
259 | spin_unlock_irqrestore(&cmd_lock, flags); | |
260 | return ret; | |
261 | } | |
262 | EXPORT_SYMBOL(cpm_command); | |
263 | ||
f2a0bd37 VB |
264 | /* Set a baud rate generator. This needs lots of work. There are |
265 | * four BRGs, any of which can be wired to any channel. | |
266 | * The internal baud rate clock is the system clock divided by 16. | |
267 | * This assumes the baudrate is 16x oversampled by the uart. | |
268 | */ | |
269 | #define BRG_INT_CLK (get_brgfreq()) | |
270 | #define BRG_UART_CLK (BRG_INT_CLK/16) | |
271 | #define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16) | |
272 | ||
273 | void | |
274 | cpm_setbrg(uint brg, uint rate) | |
275 | { | |
fb533d0c | 276 | u32 __iomem *bp; |
f2a0bd37 VB |
277 | |
278 | /* This is good enough to get SMCs running..... | |
279 | */ | |
fb533d0c | 280 | bp = &cpmp->cp_brgc1; |
f2a0bd37 VB |
281 | bp += brg; |
282 | /* The BRG has a 12-bit counter. For really slow baud rates (or | |
283 | * really fast processors), we may have to further divide by 16. | |
284 | */ | |
285 | if (((BRG_UART_CLK / rate) - 1) < 4096) | |
fb533d0c | 286 | out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN); |
f2a0bd37 | 287 | else |
fb533d0c | 288 | out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) | |
b5677d84 | 289 | CPM_BRG_EN | CPM_BRG_DIV16); |
f2a0bd37 VB |
290 | } |
291 | ||
663edbd2 | 292 | struct cpm_ioport16 { |
721c0c8a | 293 | __be16 dir, par, odr_sor, dat, intr; |
663edbd2 SW |
294 | __be16 res[3]; |
295 | }; | |
296 | ||
dc2380ec JF |
297 | struct cpm_ioport32b { |
298 | __be32 dir, par, odr, dat; | |
299 | }; | |
300 | ||
301 | struct cpm_ioport32e { | |
302 | __be32 dir, par, sor, odr, dat; | |
663edbd2 SW |
303 | }; |
304 | ||
305 | static void cpm1_set_pin32(int port, int pin, int flags) | |
306 | { | |
dc2380ec | 307 | struct cpm_ioport32e __iomem *iop; |
663edbd2 SW |
308 | pin = 1 << (31 - pin); |
309 | ||
310 | if (port == CPM_PORTB) | |
dc2380ec | 311 | iop = (struct cpm_ioport32e __iomem *) |
663edbd2 SW |
312 | &mpc8xx_immr->im_cpm.cp_pbdir; |
313 | else | |
dc2380ec | 314 | iop = (struct cpm_ioport32e __iomem *) |
663edbd2 SW |
315 | &mpc8xx_immr->im_cpm.cp_pedir; |
316 | ||
317 | if (flags & CPM_PIN_OUTPUT) | |
318 | setbits32(&iop->dir, pin); | |
319 | else | |
320 | clrbits32(&iop->dir, pin); | |
321 | ||
322 | if (!(flags & CPM_PIN_GPIO)) | |
323 | setbits32(&iop->par, pin); | |
324 | else | |
325 | clrbits32(&iop->par, pin); | |
326 | ||
721c0c8a JF |
327 | if (port == CPM_PORTB) { |
328 | if (flags & CPM_PIN_OPENDRAIN) | |
329 | setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin); | |
330 | else | |
331 | clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin); | |
332 | } | |
333 | ||
663edbd2 SW |
334 | if (port == CPM_PORTE) { |
335 | if (flags & CPM_PIN_SECONDARY) | |
336 | setbits32(&iop->sor, pin); | |
337 | else | |
338 | clrbits32(&iop->sor, pin); | |
339 | ||
340 | if (flags & CPM_PIN_OPENDRAIN) | |
341 | setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); | |
342 | else | |
343 | clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); | |
344 | } | |
345 | } | |
346 | ||
347 | static void cpm1_set_pin16(int port, int pin, int flags) | |
348 | { | |
349 | struct cpm_ioport16 __iomem *iop = | |
350 | (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport; | |
351 | ||
352 | pin = 1 << (15 - pin); | |
353 | ||
354 | if (port != 0) | |
355 | iop += port - 1; | |
356 | ||
357 | if (flags & CPM_PIN_OUTPUT) | |
358 | setbits16(&iop->dir, pin); | |
359 | else | |
360 | clrbits16(&iop->dir, pin); | |
361 | ||
362 | if (!(flags & CPM_PIN_GPIO)) | |
363 | setbits16(&iop->par, pin); | |
364 | else | |
365 | clrbits16(&iop->par, pin); | |
366 | ||
721c0c8a JF |
367 | if (port == CPM_PORTA) { |
368 | if (flags & CPM_PIN_OPENDRAIN) | |
369 | setbits16(&iop->odr_sor, pin); | |
370 | else | |
371 | clrbits16(&iop->odr_sor, pin); | |
372 | } | |
663edbd2 SW |
373 | if (port == CPM_PORTC) { |
374 | if (flags & CPM_PIN_SECONDARY) | |
721c0c8a | 375 | setbits16(&iop->odr_sor, pin); |
663edbd2 | 376 | else |
721c0c8a | 377 | clrbits16(&iop->odr_sor, pin); |
663edbd2 SW |
378 | } |
379 | } | |
380 | ||
381 | void cpm1_set_pin(enum cpm_port port, int pin, int flags) | |
382 | { | |
383 | if (port == CPM_PORTB || port == CPM_PORTE) | |
384 | cpm1_set_pin32(port, pin, flags); | |
385 | else | |
386 | cpm1_set_pin16(port, pin, flags); | |
387 | } | |
388 | ||
389 | int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode) | |
390 | { | |
391 | int shift; | |
392 | int i, bits = 0; | |
393 | u32 __iomem *reg; | |
394 | u32 mask = 7; | |
395 | ||
396 | u8 clk_map[][3] = { | |
397 | {CPM_CLK_SCC1, CPM_BRG1, 0}, | |
398 | {CPM_CLK_SCC1, CPM_BRG2, 1}, | |
399 | {CPM_CLK_SCC1, CPM_BRG3, 2}, | |
400 | {CPM_CLK_SCC1, CPM_BRG4, 3}, | |
401 | {CPM_CLK_SCC1, CPM_CLK1, 4}, | |
402 | {CPM_CLK_SCC1, CPM_CLK2, 5}, | |
403 | {CPM_CLK_SCC1, CPM_CLK3, 6}, | |
404 | {CPM_CLK_SCC1, CPM_CLK4, 7}, | |
405 | ||
406 | {CPM_CLK_SCC2, CPM_BRG1, 0}, | |
407 | {CPM_CLK_SCC2, CPM_BRG2, 1}, | |
408 | {CPM_CLK_SCC2, CPM_BRG3, 2}, | |
409 | {CPM_CLK_SCC2, CPM_BRG4, 3}, | |
410 | {CPM_CLK_SCC2, CPM_CLK1, 4}, | |
411 | {CPM_CLK_SCC2, CPM_CLK2, 5}, | |
412 | {CPM_CLK_SCC2, CPM_CLK3, 6}, | |
413 | {CPM_CLK_SCC2, CPM_CLK4, 7}, | |
414 | ||
415 | {CPM_CLK_SCC3, CPM_BRG1, 0}, | |
416 | {CPM_CLK_SCC3, CPM_BRG2, 1}, | |
417 | {CPM_CLK_SCC3, CPM_BRG3, 2}, | |
418 | {CPM_CLK_SCC3, CPM_BRG4, 3}, | |
419 | {CPM_CLK_SCC3, CPM_CLK5, 4}, | |
420 | {CPM_CLK_SCC3, CPM_CLK6, 5}, | |
421 | {CPM_CLK_SCC3, CPM_CLK7, 6}, | |
422 | {CPM_CLK_SCC3, CPM_CLK8, 7}, | |
423 | ||
424 | {CPM_CLK_SCC4, CPM_BRG1, 0}, | |
425 | {CPM_CLK_SCC4, CPM_BRG2, 1}, | |
426 | {CPM_CLK_SCC4, CPM_BRG3, 2}, | |
427 | {CPM_CLK_SCC4, CPM_BRG4, 3}, | |
428 | {CPM_CLK_SCC4, CPM_CLK5, 4}, | |
429 | {CPM_CLK_SCC4, CPM_CLK6, 5}, | |
430 | {CPM_CLK_SCC4, CPM_CLK7, 6}, | |
431 | {CPM_CLK_SCC4, CPM_CLK8, 7}, | |
432 | ||
433 | {CPM_CLK_SMC1, CPM_BRG1, 0}, | |
434 | {CPM_CLK_SMC1, CPM_BRG2, 1}, | |
435 | {CPM_CLK_SMC1, CPM_BRG3, 2}, | |
436 | {CPM_CLK_SMC1, CPM_BRG4, 3}, | |
437 | {CPM_CLK_SMC1, CPM_CLK1, 4}, | |
438 | {CPM_CLK_SMC1, CPM_CLK2, 5}, | |
439 | {CPM_CLK_SMC1, CPM_CLK3, 6}, | |
440 | {CPM_CLK_SMC1, CPM_CLK4, 7}, | |
441 | ||
442 | {CPM_CLK_SMC2, CPM_BRG1, 0}, | |
443 | {CPM_CLK_SMC2, CPM_BRG2, 1}, | |
444 | {CPM_CLK_SMC2, CPM_BRG3, 2}, | |
445 | {CPM_CLK_SMC2, CPM_BRG4, 3}, | |
446 | {CPM_CLK_SMC2, CPM_CLK5, 4}, | |
447 | {CPM_CLK_SMC2, CPM_CLK6, 5}, | |
448 | {CPM_CLK_SMC2, CPM_CLK7, 6}, | |
449 | {CPM_CLK_SMC2, CPM_CLK8, 7}, | |
450 | }; | |
451 | ||
452 | switch (target) { | |
453 | case CPM_CLK_SCC1: | |
454 | reg = &mpc8xx_immr->im_cpm.cp_sicr; | |
455 | shift = 0; | |
456 | break; | |
457 | ||
458 | case CPM_CLK_SCC2: | |
459 | reg = &mpc8xx_immr->im_cpm.cp_sicr; | |
460 | shift = 8; | |
461 | break; | |
462 | ||
463 | case CPM_CLK_SCC3: | |
464 | reg = &mpc8xx_immr->im_cpm.cp_sicr; | |
465 | shift = 16; | |
466 | break; | |
467 | ||
468 | case CPM_CLK_SCC4: | |
469 | reg = &mpc8xx_immr->im_cpm.cp_sicr; | |
470 | shift = 24; | |
471 | break; | |
472 | ||
473 | case CPM_CLK_SMC1: | |
474 | reg = &mpc8xx_immr->im_cpm.cp_simode; | |
475 | shift = 12; | |
476 | break; | |
477 | ||
478 | case CPM_CLK_SMC2: | |
479 | reg = &mpc8xx_immr->im_cpm.cp_simode; | |
480 | shift = 28; | |
481 | break; | |
482 | ||
483 | default: | |
484 | printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n"); | |
485 | return -EINVAL; | |
486 | } | |
487 | ||
663edbd2 SW |
488 | for (i = 0; i < ARRAY_SIZE(clk_map); i++) { |
489 | if (clk_map[i][0] == target && clk_map[i][1] == clock) { | |
490 | bits = clk_map[i][2]; | |
491 | break; | |
492 | } | |
493 | } | |
494 | ||
495 | if (i == ARRAY_SIZE(clk_map)) { | |
496 | printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n"); | |
497 | return -EINVAL; | |
498 | } | |
499 | ||
500 | bits <<= shift; | |
501 | mask <<= shift; | |
1cca2d2b WO |
502 | |
503 | if (reg == &mpc8xx_immr->im_cpm.cp_sicr) { | |
504 | if (mode == CPM_CLK_RTX) { | |
505 | bits |= bits << 3; | |
506 | mask |= mask << 3; | |
507 | } else if (mode == CPM_CLK_RX) { | |
508 | bits <<= 3; | |
509 | mask <<= 3; | |
510 | } | |
511 | } | |
512 | ||
663edbd2 SW |
513 | out_be32(reg, (in_be32(reg) & ~mask) | bits); |
514 | ||
515 | return 0; | |
516 | } | |
dc2380ec JF |
517 | |
518 | /* | |
519 | * GPIO LIB API implementation | |
520 | */ | |
521 | #ifdef CONFIG_8xx_GPIO | |
522 | ||
523 | struct cpm1_gpio16_chip { | |
524 | struct of_mm_gpio_chip mm_gc; | |
525 | spinlock_t lock; | |
526 | ||
527 | /* shadowed data register to clear/set bits safely */ | |
528 | u16 cpdata; | |
529 | }; | |
530 | ||
531 | static inline struct cpm1_gpio16_chip * | |
532 | to_cpm1_gpio16_chip(struct of_mm_gpio_chip *mm_gc) | |
533 | { | |
534 | return container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc); | |
535 | } | |
536 | ||
537 | static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc) | |
538 | { | |
539 | struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc); | |
540 | struct cpm_ioport16 __iomem *iop = mm_gc->regs; | |
541 | ||
542 | cpm1_gc->cpdata = in_be16(&iop->dat); | |
543 | } | |
544 | ||
545 | static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio) | |
546 | { | |
547 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
548 | struct cpm_ioport16 __iomem *iop = mm_gc->regs; | |
549 | u16 pin_mask; | |
550 | ||
551 | pin_mask = 1 << (15 - gpio); | |
552 | ||
553 | return !!(in_be16(&iop->dat) & pin_mask); | |
554 | } | |
555 | ||
f1eaf16a JF |
556 | static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask, |
557 | int value) | |
dc2380ec | 558 | { |
dc2380ec JF |
559 | struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc); |
560 | struct cpm_ioport16 __iomem *iop = mm_gc->regs; | |
dc2380ec JF |
561 | |
562 | if (value) | |
563 | cpm1_gc->cpdata |= pin_mask; | |
564 | else | |
565 | cpm1_gc->cpdata &= ~pin_mask; | |
566 | ||
567 | out_be16(&iop->dat, cpm1_gc->cpdata); | |
f1eaf16a JF |
568 | } |
569 | ||
570 | static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value) | |
571 | { | |
572 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
573 | struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc); | |
574 | unsigned long flags; | |
575 | u16 pin_mask = 1 << (15 - gpio); | |
576 | ||
577 | spin_lock_irqsave(&cpm1_gc->lock, flags); | |
578 | ||
579 | __cpm1_gpio16_set(mm_gc, pin_mask, value); | |
dc2380ec JF |
580 | |
581 | spin_unlock_irqrestore(&cpm1_gc->lock, flags); | |
582 | } | |
583 | ||
584 | static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) | |
585 | { | |
586 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
f1eaf16a | 587 | struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc); |
dc2380ec | 588 | struct cpm_ioport16 __iomem *iop = mm_gc->regs; |
f1eaf16a JF |
589 | unsigned long flags; |
590 | u16 pin_mask = 1 << (15 - gpio); | |
dc2380ec | 591 | |
f1eaf16a | 592 | spin_lock_irqsave(&cpm1_gc->lock, flags); |
dc2380ec JF |
593 | |
594 | setbits16(&iop->dir, pin_mask); | |
f1eaf16a | 595 | __cpm1_gpio16_set(mm_gc, pin_mask, val); |
dc2380ec | 596 | |
f1eaf16a | 597 | spin_unlock_irqrestore(&cpm1_gc->lock, flags); |
dc2380ec JF |
598 | |
599 | return 0; | |
600 | } | |
601 | ||
602 | static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio) | |
603 | { | |
604 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
f1eaf16a | 605 | struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc); |
dc2380ec | 606 | struct cpm_ioport16 __iomem *iop = mm_gc->regs; |
f1eaf16a JF |
607 | unsigned long flags; |
608 | u16 pin_mask = 1 << (15 - gpio); | |
dc2380ec | 609 | |
f1eaf16a | 610 | spin_lock_irqsave(&cpm1_gc->lock, flags); |
dc2380ec JF |
611 | |
612 | clrbits16(&iop->dir, pin_mask); | |
613 | ||
f1eaf16a JF |
614 | spin_unlock_irqrestore(&cpm1_gc->lock, flags); |
615 | ||
dc2380ec JF |
616 | return 0; |
617 | } | |
618 | ||
619 | int cpm1_gpiochip_add16(struct device_node *np) | |
620 | { | |
621 | struct cpm1_gpio16_chip *cpm1_gc; | |
622 | struct of_mm_gpio_chip *mm_gc; | |
dc2380ec JF |
623 | struct gpio_chip *gc; |
624 | ||
625 | cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL); | |
626 | if (!cpm1_gc) | |
627 | return -ENOMEM; | |
628 | ||
629 | spin_lock_init(&cpm1_gc->lock); | |
630 | ||
631 | mm_gc = &cpm1_gc->mm_gc; | |
a19e3da5 | 632 | gc = &mm_gc->gc; |
dc2380ec JF |
633 | |
634 | mm_gc->save_regs = cpm1_gpio16_save_regs; | |
dc2380ec JF |
635 | gc->ngpio = 16; |
636 | gc->direction_input = cpm1_gpio16_dir_in; | |
637 | gc->direction_output = cpm1_gpio16_dir_out; | |
638 | gc->get = cpm1_gpio16_get; | |
639 | gc->set = cpm1_gpio16_set; | |
640 | ||
641 | return of_mm_gpiochip_add(np, mm_gc); | |
642 | } | |
643 | ||
644 | struct cpm1_gpio32_chip { | |
645 | struct of_mm_gpio_chip mm_gc; | |
646 | spinlock_t lock; | |
647 | ||
648 | /* shadowed data register to clear/set bits safely */ | |
649 | u32 cpdata; | |
650 | }; | |
651 | ||
652 | static inline struct cpm1_gpio32_chip * | |
653 | to_cpm1_gpio32_chip(struct of_mm_gpio_chip *mm_gc) | |
654 | { | |
655 | return container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc); | |
656 | } | |
657 | ||
658 | static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc) | |
659 | { | |
660 | struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc); | |
661 | struct cpm_ioport32b __iomem *iop = mm_gc->regs; | |
662 | ||
663 | cpm1_gc->cpdata = in_be32(&iop->dat); | |
664 | } | |
665 | ||
666 | static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio) | |
667 | { | |
668 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
669 | struct cpm_ioport32b __iomem *iop = mm_gc->regs; | |
670 | u32 pin_mask; | |
671 | ||
672 | pin_mask = 1 << (31 - gpio); | |
673 | ||
674 | return !!(in_be32(&iop->dat) & pin_mask); | |
675 | } | |
676 | ||
f1eaf16a JF |
677 | static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, |
678 | int value) | |
dc2380ec | 679 | { |
dc2380ec JF |
680 | struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc); |
681 | struct cpm_ioport32b __iomem *iop = mm_gc->regs; | |
dc2380ec JF |
682 | |
683 | if (value) | |
684 | cpm1_gc->cpdata |= pin_mask; | |
685 | else | |
686 | cpm1_gc->cpdata &= ~pin_mask; | |
687 | ||
688 | out_be32(&iop->dat, cpm1_gc->cpdata); | |
f1eaf16a JF |
689 | } |
690 | ||
691 | static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) | |
692 | { | |
693 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
694 | struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc); | |
695 | unsigned long flags; | |
696 | u32 pin_mask = 1 << (31 - gpio); | |
697 | ||
698 | spin_lock_irqsave(&cpm1_gc->lock, flags); | |
699 | ||
700 | __cpm1_gpio32_set(mm_gc, pin_mask, value); | |
dc2380ec JF |
701 | |
702 | spin_unlock_irqrestore(&cpm1_gc->lock, flags); | |
703 | } | |
704 | ||
705 | static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) | |
706 | { | |
707 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
f1eaf16a | 708 | struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc); |
dc2380ec | 709 | struct cpm_ioport32b __iomem *iop = mm_gc->regs; |
f1eaf16a JF |
710 | unsigned long flags; |
711 | u32 pin_mask = 1 << (31 - gpio); | |
dc2380ec | 712 | |
f1eaf16a | 713 | spin_lock_irqsave(&cpm1_gc->lock, flags); |
dc2380ec JF |
714 | |
715 | setbits32(&iop->dir, pin_mask); | |
f1eaf16a | 716 | __cpm1_gpio32_set(mm_gc, pin_mask, val); |
dc2380ec | 717 | |
f1eaf16a | 718 | spin_unlock_irqrestore(&cpm1_gc->lock, flags); |
dc2380ec JF |
719 | |
720 | return 0; | |
721 | } | |
722 | ||
723 | static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) | |
724 | { | |
725 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
f1eaf16a | 726 | struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc); |
dc2380ec | 727 | struct cpm_ioport32b __iomem *iop = mm_gc->regs; |
f1eaf16a JF |
728 | unsigned long flags; |
729 | u32 pin_mask = 1 << (31 - gpio); | |
dc2380ec | 730 | |
f1eaf16a | 731 | spin_lock_irqsave(&cpm1_gc->lock, flags); |
dc2380ec JF |
732 | |
733 | clrbits32(&iop->dir, pin_mask); | |
734 | ||
f1eaf16a JF |
735 | spin_unlock_irqrestore(&cpm1_gc->lock, flags); |
736 | ||
dc2380ec JF |
737 | return 0; |
738 | } | |
739 | ||
740 | int cpm1_gpiochip_add32(struct device_node *np) | |
741 | { | |
742 | struct cpm1_gpio32_chip *cpm1_gc; | |
743 | struct of_mm_gpio_chip *mm_gc; | |
dc2380ec JF |
744 | struct gpio_chip *gc; |
745 | ||
746 | cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL); | |
747 | if (!cpm1_gc) | |
748 | return -ENOMEM; | |
749 | ||
750 | spin_lock_init(&cpm1_gc->lock); | |
751 | ||
752 | mm_gc = &cpm1_gc->mm_gc; | |
a19e3da5 | 753 | gc = &mm_gc->gc; |
dc2380ec JF |
754 | |
755 | mm_gc->save_regs = cpm1_gpio32_save_regs; | |
dc2380ec JF |
756 | gc->ngpio = 32; |
757 | gc->direction_input = cpm1_gpio32_dir_in; | |
758 | gc->direction_output = cpm1_gpio32_dir_out; | |
759 | gc->get = cpm1_gpio32_get; | |
760 | gc->set = cpm1_gpio32_set; | |
761 | ||
762 | return of_mm_gpiochip_add(np, mm_gc); | |
763 | } | |
764 | ||
765 | static int cpm_init_par_io(void) | |
766 | { | |
767 | struct device_node *np; | |
768 | ||
769 | for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-a") | |
770 | cpm1_gpiochip_add16(np); | |
771 | ||
772 | for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-b") | |
773 | cpm1_gpiochip_add32(np); | |
774 | ||
775 | for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-c") | |
776 | cpm1_gpiochip_add16(np); | |
777 | ||
778 | for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-d") | |
779 | cpm1_gpiochip_add16(np); | |
780 | ||
781 | /* Port E uses CPM2 layout */ | |
782 | for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-e") | |
783 | cpm2_gpiochip_add32(np); | |
784 | return 0; | |
785 | } | |
786 | arch_initcall(cpm_init_par_io); | |
787 | ||
788 | #endif /* CONFIG_8xx_GPIO */ |