[deliverable/linux.git] / arch / powerpc / sysdev / cpm2.c

/*
 * General Purpose functions for the global management of the
 * 8260 Communication Processor Module.
 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
 *	2.3.99 Updates
 *
 * 2006 (c) MontaVista Software, Inc.
 * Vitaly Bordug <vbordug@ru.mvista.com>
 * 	Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/*
 *
 * In addition to the individual control of the communication
 * channels, there are a few functions that globally affect the
 * communication processor.
 *
 * Buffer descriptors must be allocated from the dual ported memory
 * space.  The allocator for that is here.  When the communication
 * process is reset, we reclaim the memory available.  There is
 * currently no deallocator for this memory.
 */
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mpc8260.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/cpm2.h>
#include <asm/rheap.h>
#include <asm/fs_pd.h>

#include <sysdev/fsl_soc.h>

cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */

/* We allocate this here because it is used almost exclusively for
 * the communication processor devices.
 */
cpm2_map_t __iomem *cpm2_immr;

#define CPM_MAP_SIZE	(0x40000)	/* 256k - the PQ3 reserve this amount
					   of space for CPM as it is larger
					   than on PQ2 */

void __init cpm2_reset(void)
{
#ifdef CONFIG_PPC_85xx
	cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
#else
	cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
#endif

	/* Reclaim the DP memory for our use.
	 */
	cpm_muram_init();

	/* Tell everyone where the comm processor resides.
	 */
	cpmp = &cpm2_immr->im_cpm;

#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
	/* Reset the CPM.
	 */
	cpm_command(CPM_CR_RST, 0);
#endif
}

static DEFINE_SPINLOCK(cmd_lock);

#define MAX_CR_CMD_LOOPS        10000

int cpm_command(u32 command, u8 opcode)
{
	int i, ret;
	unsigned long flags;

	spin_lock_irqsave(&cmd_lock, flags);

	ret = 0;
	out_be32(&cpmp->cp_cpcr, command | opcode | CPM_CR_FLG);
	for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
		if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
			goto out;

	printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
	ret = -EIO;
out:
	spin_unlock_irqrestore(&cmd_lock, flags);
	return ret;
}
EXPORT_SYMBOL(cpm_command);

/* Set a baud rate generator.  This needs lots of work.  There are
 * eight BRGs, which can be connected to the CPM channels or output
 * as clocks.  The BRGs are in two different block of internal
 * memory mapped space.
 * The baud rate clock is the system clock divided by something.
 * It was set up long ago during the initial boot phase and is
 * is given to us.
 * Baud rate clocks are zero-based in the driver code (as that maps
 * to port numbers).  Documentation uses 1-based numbering.
 */
void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src)
{
	u32 __iomem *bp;
	u32 val;

	/* This is good enough to get SMCs running.....
	*/
	if (brg < 4) {
		bp = cpm2_map_size(im_brgc1, 16);
	} else {
		bp = cpm2_map_size(im_brgc5, 16);
		brg -= 4;
	}
	bp += brg;
	/* Round the clock divider to the nearest integer. */
	val = (((clk * 2 / rate) - 1) & ~1) | CPM_BRG_EN | src;
	if (div16)
		val |= CPM_BRG_DIV16;

	out_be32(bp, val);
	cpm2_unmap(bp);
}
EXPORT_SYMBOL(__cpm2_setbrg);

int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
{
	int ret = 0;
	int shift;
	int i, bits = 0;
	cpmux_t __iomem *im_cpmux;
	u32 __iomem *reg;
	u32 mask = 7;

	u8 clk_map[][3] = {
		{CPM_CLK_FCC1, CPM_BRG5, 0},
		{CPM_CLK_FCC1, CPM_BRG6, 1},
		{CPM_CLK_FCC1, CPM_BRG7, 2},
		{CPM_CLK_FCC1, CPM_BRG8, 3},
		{CPM_CLK_FCC1, CPM_CLK9, 4},
		{CPM_CLK_FCC1, CPM_CLK10, 5},
		{CPM_CLK_FCC1, CPM_CLK11, 6},
		{CPM_CLK_FCC1, CPM_CLK12, 7},
		{CPM_CLK_FCC2, CPM_BRG5, 0},
		{CPM_CLK_FCC2, CPM_BRG6, 1},
		{CPM_CLK_FCC2, CPM_BRG7, 2},
		{CPM_CLK_FCC2, CPM_BRG8, 3},
		{CPM_CLK_FCC2, CPM_CLK13, 4},
		{CPM_CLK_FCC2, CPM_CLK14, 5},
		{CPM_CLK_FCC2, CPM_CLK15, 6},
		{CPM_CLK_FCC2, CPM_CLK16, 7},
		{CPM_CLK_FCC3, CPM_BRG5, 0},
		{CPM_CLK_FCC3, CPM_BRG6, 1},
		{CPM_CLK_FCC3, CPM_BRG7, 2},
		{CPM_CLK_FCC3, CPM_BRG8, 3},
		{CPM_CLK_FCC3, CPM_CLK13, 4},
		{CPM_CLK_FCC3, CPM_CLK14, 5},
		{CPM_CLK_FCC3, CPM_CLK15, 6},
		{CPM_CLK_FCC3, CPM_CLK16, 7},
		{CPM_CLK_SCC1, CPM_BRG1, 0},
		{CPM_CLK_SCC1, CPM_BRG2, 1},
		{CPM_CLK_SCC1, CPM_BRG3, 2},
		{CPM_CLK_SCC1, CPM_BRG4, 3},
		{CPM_CLK_SCC1, CPM_CLK11, 4},
		{CPM_CLK_SCC1, CPM_CLK12, 5},
		{CPM_CLK_SCC1, CPM_CLK3, 6},
		{CPM_CLK_SCC1, CPM_CLK4, 7},
		{CPM_CLK_SCC2, CPM_BRG1, 0},
		{CPM_CLK_SCC2, CPM_BRG2, 1},
		{CPM_CLK_SCC2, CPM_BRG3, 2},
		{CPM_CLK_SCC2, CPM_BRG4, 3},
		{CPM_CLK_SCC2, CPM_CLK11, 4},
		{CPM_CLK_SCC2, CPM_CLK12, 5},
		{CPM_CLK_SCC2, CPM_CLK3, 6},
		{CPM_CLK_SCC2, CPM_CLK4, 7},
		{CPM_CLK_SCC3, CPM_BRG1, 0},
		{CPM_CLK_SCC3, CPM_BRG2, 1},
		{CPM_CLK_SCC3, CPM_BRG3, 2},
		{CPM_CLK_SCC3, CPM_BRG4, 3},
		{CPM_CLK_SCC3, CPM_CLK5, 4},
		{CPM_CLK_SCC3, CPM_CLK6, 5},
		{CPM_CLK_SCC3, CPM_CLK7, 6},
		{CPM_CLK_SCC3, CPM_CLK8, 7},
		{CPM_CLK_SCC4, CPM_BRG1, 0},
		{CPM_CLK_SCC4, CPM_BRG2, 1},
		{CPM_CLK_SCC4, CPM_BRG3, 2},
		{CPM_CLK_SCC4, CPM_BRG4, 3},
		{CPM_CLK_SCC4, CPM_CLK5, 4},
		{CPM_CLK_SCC4, CPM_CLK6, 5},
		{CPM_CLK_SCC4, CPM_CLK7, 6},
		{CPM_CLK_SCC4, CPM_CLK8, 7},
	};

	im_cpmux = cpm2_map(im_cpmux);

	switch (target) {
	case CPM_CLK_SCC1:
		reg = &im_cpmux->cmx_scr;
		shift = 24;
		break;
	case CPM_CLK_SCC2:
		reg = &im_cpmux->cmx_scr;
		shift = 16;
		break;
	case CPM_CLK_SCC3:
		reg = &im_cpmux->cmx_scr;
		shift = 8;
		break;
	case CPM_CLK_SCC4:
		reg = &im_cpmux->cmx_scr;
		shift = 0;
		break;
	case CPM_CLK_FCC1:
		reg = &im_cpmux->cmx_fcr;
		shift = 24;
		break;
	case CPM_CLK_FCC2:
		reg = &im_cpmux->cmx_fcr;
		shift = 16;
		break;
	case CPM_CLK_FCC3:
		reg = &im_cpmux->cmx_fcr;
		shift = 8;
		break;
	default:
		printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
		return -EINVAL;
	}

	if (mode == CPM_CLK_RX)
		shift += 3;

	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
		if (clk_map[i][0] == target && clk_map[i][1] == clock) {
			bits = clk_map[i][2];
			break;
		}
	}
	if (i == ARRAY_SIZE(clk_map))
	    ret = -EINVAL;

	bits <<= shift;
	mask <<= shift;

	out_be32(reg, (in_be32(reg) & ~mask) | bits);

	cpm2_unmap(im_cpmux);
	return ret;
}

int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
{
	int ret = 0;
	int shift;
	int i, bits = 0;
	cpmux_t __iomem *im_cpmux;
	u8 __iomem *reg;
	u8 mask = 3;

	u8 clk_map[][3] = {
		{CPM_CLK_SMC1, CPM_BRG1, 0},
		{CPM_CLK_SMC1, CPM_BRG7, 1},
		{CPM_CLK_SMC1, CPM_CLK7, 2},
		{CPM_CLK_SMC1, CPM_CLK9, 3},
		{CPM_CLK_SMC2, CPM_BRG2, 0},
		{CPM_CLK_SMC2, CPM_BRG8, 1},
		{CPM_CLK_SMC2, CPM_CLK4, 2},
		{CPM_CLK_SMC2, CPM_CLK15, 3},
	};

	im_cpmux = cpm2_map(im_cpmux);

	switch (target) {
	case CPM_CLK_SMC1:
		reg = &im_cpmux->cmx_smr;
		mask = 3;
		shift = 4;
		break;
	case CPM_CLK_SMC2:
		reg = &im_cpmux->cmx_smr;
		mask = 3;
		shift = 0;
		break;
	default:
		printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n");
		return -EINVAL;
	}

	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
		if (clk_map[i][0] == target && clk_map[i][1] == clock) {
			bits = clk_map[i][2];
			break;
		}
	}
	if (i == ARRAY_SIZE(clk_map))
	    ret = -EINVAL;

	bits <<= shift;
	mask <<= shift;

	out_8(reg, (in_8(reg) & ~mask) | bits);

	cpm2_unmap(im_cpmux);
	return ret;
}

struct cpm2_ioports {
	u32 dir, par, sor, odr, dat;
	u32 res[3];
};

void cpm2_set_pin(int port, int pin, int flags)
{
	struct cpm2_ioports __iomem *iop =
		(struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;

	pin = 1 << (31 - pin);

	if (flags & CPM_PIN_OUTPUT)
		setbits32(&iop[port].dir, pin);
	else
		clrbits32(&iop[port].dir, pin);

	if (!(flags & CPM_PIN_GPIO))
		setbits32(&iop[port].par, pin);
	else
		clrbits32(&iop[port].par, pin);

	if (flags & CPM_PIN_SECONDARY)
		setbits32(&iop[port].sor, pin);
	else
		clrbits32(&iop[port].sor, pin);

	if (flags & CPM_PIN_OPENDRAIN)
		setbits32(&iop[port].odr, pin);
	else
		clrbits32(&iop[port].odr, pin);
}

static int cpm_init_par_io(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "fsl,cpm2-pario-bank")
		cpm2_gpiochip_add32(np);
	return 0;
}
arch_initcall(cpm_init_par_io);
Commit	Line	Data
b0c110b4 VB	1	/*
	2	* General Purpose functions for the global management of the
	3	* 8260 Communication Processor Module.
	4	* Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
	5	* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
	6	* 2.3.99 Updates
	7	*
	8	* 2006 (c) MontaVista Software, Inc.
	9	* Vitaly Bordug <vbordug@ru.mvista.com>
	10	* Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
	11	*
	12	* This file is licensed under the terms of the GNU General Public License
	13	* version 2. This program is licensed "as is" without any warranty of any
	14	* kind, whether express or implied.
	15	*/
	16
	17	/*
	18	*
	19	* In addition to the individual control of the communication
	20	* channels, there are a few functions that globally affect the
	21	* communication processor.
	22	*
	23	* Buffer descriptors must be allocated from the dual ported memory
	24	* space. The allocator for that is here. When the communication
	25	* process is reset, we reclaim the memory available. There is
	26	* currently no deallocator for this memory.
	27	*/
	28	#include <linux/errno.h>
	29	#include <linux/sched.h>
	30	#include <linux/kernel.h>
	31	#include <linux/param.h>
	32	#include <linux/string.h>
	33	#include <linux/mm.h>
	34	#include <linux/interrupt.h>
	35	#include <linux/module.h>
449012da SW	36	#include <linux/of.h>
449012da SW	37
b0c110b4 VB	38	#include <asm/io.h>
	39	#include <asm/irq.h>
	40	#include <asm/mpc8260.h>
	41	#include <asm/page.h>
	42	#include <asm/pgtable.h>
	43	#include <asm/cpm2.h>
	44	#include <asm/rheap.h>
	45	#include <asm/fs_pd.h>
	46
	47	#include <sysdev/fsl_soc.h>
	48
449012da	49	cpm_cpm2_t __iomem cpmp; / Pointer to comm processor space */
b0c110b4 VB	50
	51	/* We allocate this here because it is used almost exclusively for
	52	* the communication processor devices.
	53	*/
449012da	54	cpm2_map_t __iomem *cpm2_immr;
b0c110b4 VB	55
	56	#define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
	57	of space for CPM as it is larger
	58	than on PQ2 */
	59
cd2150bc	60	void __init cpm2_reset(void)
b0c110b4	61	{
449012da SW	62	#ifdef CONFIG_PPC_85xx
	63	cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
	64	#else
	65	cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
	66	#endif
b0c110b4 VB	67
	68	/* Reclaim the DP memory for our use.
	69	*/
15f8c604	70	cpm_muram_init();
b0c110b4 VB	71
	72	/* Tell everyone where the comm processor resides.
	73	*/
	74	cpmp = &cpm2_immr->im_cpm;
872a15de LP	75
	76	#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
	77	/* Reset the CPM.
	78	*/
	79	cpm_command(CPM_CR_RST, 0);
	80	#endif
b0c110b4 VB	81	}
b0c110b4 VB	82
362f9b6f JF	83	static DEFINE_SPINLOCK(cmd_lock);
	84
	85	#define MAX_CR_CMD_LOOPS 10000
	86
	87	int cpm_command(u32 command, u8 opcode)
	88	{
	89	int i, ret;
	90	unsigned long flags;
	91
	92	spin_lock_irqsave(&cmd_lock, flags);
	93
	94	ret = 0;
	95	out_be32(&cpmp->cp_cpcr, command \| opcode \| CPM_CR_FLG);
	96	for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
	97	if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
	98	goto out;
	99
e48b1b45	100	printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
362f9b6f JF	101	ret = -EIO;
	102	out:
	103	spin_unlock_irqrestore(&cmd_lock, flags);
	104	return ret;
	105	}
	106	EXPORT_SYMBOL(cpm_command);
	107
b0c110b4 VB	108	/* Set a baud rate generator. This needs lots of work. There are
	109	* eight BRGs, which can be connected to the CPM channels or output
	110	* as clocks. The BRGs are in two different block of internal
	111	* memory mapped space.
	112	* The baud rate clock is the system clock divided by something.
	113	* It was set up long ago during the initial boot phase and is
	114	* is given to us.
	115	* Baud rate clocks are zero-based in the driver code (as that maps
	116	* to port numbers). Documentation uses 1-based numbering.
	117	*/
dddb8d31	118	void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src)
b0c110b4	119	{
449012da	120	u32 __iomem *bp;
dddb8d31	121	u32 val;
b0c110b4 VB	122
	123	/* This is good enough to get SMCs running.....
	124	*/
	125	if (brg < 4) {
fc8e50e3	126	bp = cpm2_map_size(im_brgc1, 16);
b0c110b4	127	} else {
fc8e50e3	128	bp = cpm2_map_size(im_brgc5, 16);
b0c110b4 VB	129	brg -= 4;
	130	}
	131	bp += brg;
7b890994 LP	132	/* Round the clock divider to the nearest integer. */
7b890994 LP	133	val = (((clk * 2 / rate) - 1) & ~1) \| CPM_BRG_EN \| src;
b0c110b4	134	if (div16)
449012da	135	val \|= CPM_BRG_DIV16;
fc8e50e3	136
449012da	137	out_be32(bp, val);
fc8e50e3	138	cpm2_unmap(bp);
b0c110b4	139	}
dddb8d31	140	EXPORT_SYMBOL(__cpm2_setbrg);
b0c110b4	141
d3465c92 VB	142	int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
	143	{
	144	int ret = 0;
	145	int shift;
	146	int i, bits = 0;
449012da SW	147	cpmux_t __iomem *im_cpmux;
449012da SW	148	u32 __iomem *reg;
d3465c92	149	u32 mask = 7;
2652d4ec SW	150
2652d4ec SW	151	u8 clk_map[][3] = {
d3465c92 VB	152	{CPM_CLK_FCC1, CPM_BRG5, 0},
	153	{CPM_CLK_FCC1, CPM_BRG6, 1},
	154	{CPM_CLK_FCC1, CPM_BRG7, 2},
	155	{CPM_CLK_FCC1, CPM_BRG8, 3},
	156	{CPM_CLK_FCC1, CPM_CLK9, 4},
	157	{CPM_CLK_FCC1, CPM_CLK10, 5},
	158	{CPM_CLK_FCC1, CPM_CLK11, 6},
	159	{CPM_CLK_FCC1, CPM_CLK12, 7},
	160	{CPM_CLK_FCC2, CPM_BRG5, 0},
	161	{CPM_CLK_FCC2, CPM_BRG6, 1},
	162	{CPM_CLK_FCC2, CPM_BRG7, 2},
	163	{CPM_CLK_FCC2, CPM_BRG8, 3},
	164	{CPM_CLK_FCC2, CPM_CLK13, 4},
	165	{CPM_CLK_FCC2, CPM_CLK14, 5},
	166	{CPM_CLK_FCC2, CPM_CLK15, 6},
	167	{CPM_CLK_FCC2, CPM_CLK16, 7},
	168	{CPM_CLK_FCC3, CPM_BRG5, 0},
	169	{CPM_CLK_FCC3, CPM_BRG6, 1},
	170	{CPM_CLK_FCC3, CPM_BRG7, 2},
	171	{CPM_CLK_FCC3, CPM_BRG8, 3},
	172	{CPM_CLK_FCC3, CPM_CLK13, 4},
	173	{CPM_CLK_FCC3, CPM_CLK14, 5},
	174	{CPM_CLK_FCC3, CPM_CLK15, 6},
2652d4ec SW	175	{CPM_CLK_FCC3, CPM_CLK16, 7},
	176	{CPM_CLK_SCC1, CPM_BRG1, 0},
	177	{CPM_CLK_SCC1, CPM_BRG2, 1},
	178	{CPM_CLK_SCC1, CPM_BRG3, 2},
	179	{CPM_CLK_SCC1, CPM_BRG4, 3},
	180	{CPM_CLK_SCC1, CPM_CLK11, 4},
	181	{CPM_CLK_SCC1, CPM_CLK12, 5},
	182	{CPM_CLK_SCC1, CPM_CLK3, 6},
	183	{CPM_CLK_SCC1, CPM_CLK4, 7},
	184	{CPM_CLK_SCC2, CPM_BRG1, 0},
	185	{CPM_CLK_SCC2, CPM_BRG2, 1},
	186	{CPM_CLK_SCC2, CPM_BRG3, 2},
	187	{CPM_CLK_SCC2, CPM_BRG4, 3},
	188	{CPM_CLK_SCC2, CPM_CLK11, 4},
	189	{CPM_CLK_SCC2, CPM_CLK12, 5},
	190	{CPM_CLK_SCC2, CPM_CLK3, 6},
	191	{CPM_CLK_SCC2, CPM_CLK4, 7},
	192	{CPM_CLK_SCC3, CPM_BRG1, 0},
	193	{CPM_CLK_SCC3, CPM_BRG2, 1},
	194	{CPM_CLK_SCC3, CPM_BRG3, 2},
	195	{CPM_CLK_SCC3, CPM_BRG4, 3},
	196	{CPM_CLK_SCC3, CPM_CLK5, 4},
	197	{CPM_CLK_SCC3, CPM_CLK6, 5},
	198	{CPM_CLK_SCC3, CPM_CLK7, 6},
	199	{CPM_CLK_SCC3, CPM_CLK8, 7},
	200	{CPM_CLK_SCC4, CPM_BRG1, 0},
	201	{CPM_CLK_SCC4, CPM_BRG2, 1},
	202	{CPM_CLK_SCC4, CPM_BRG3, 2},
	203	{CPM_CLK_SCC4, CPM_BRG4, 3},
	204	{CPM_CLK_SCC4, CPM_CLK5, 4},
	205	{CPM_CLK_SCC4, CPM_CLK6, 5},
	206	{CPM_CLK_SCC4, CPM_CLK7, 6},
	207	{CPM_CLK_SCC4, CPM_CLK8, 7},
	208	};
d3465c92 VB	209
	210	im_cpmux = cpm2_map(im_cpmux);
	211
	212	switch (target) {
	213	case CPM_CLK_SCC1:
	214	reg = &im_cpmux->cmx_scr;
	215	shift = 24;
025306f3	216	break;
d3465c92 VB	217	case CPM_CLK_SCC2:
	218	reg = &im_cpmux->cmx_scr;
	219	shift = 16;
	220	break;
	221	case CPM_CLK_SCC3:
	222	reg = &im_cpmux->cmx_scr;
	223	shift = 8;
	224	break;
	225	case CPM_CLK_SCC4:
	226	reg = &im_cpmux->cmx_scr;
	227	shift = 0;
	228	break;
	229	case CPM_CLK_FCC1:
	230	reg = &im_cpmux->cmx_fcr;
	231	shift = 24;
	232	break;
	233	case CPM_CLK_FCC2:
	234	reg = &im_cpmux->cmx_fcr;
	235	shift = 16;
	236	break;
	237	case CPM_CLK_FCC3:
	238	reg = &im_cpmux->cmx_fcr;
	239	shift = 8;
	240	break;
	241	default:
	242	printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
	243	return -EINVAL;
	244	}
	245
	246	if (mode == CPM_CLK_RX)
4b218e9b	247	shift += 3;
d3465c92	248
2652d4ec	249	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
d3465c92 VB	250	if (clk_map[i][0] == target && clk_map[i][1] == clock) {
	251	bits = clk_map[i][2];
	252	break;
	253	}
	254	}
2652d4ec	255	if (i == ARRAY_SIZE(clk_map))
d3465c92 VB	256	ret = -EINVAL;
	257
	258	bits <<= shift;
	259	mask <<= shift;
2652d4ec	260
d3465c92 VB	261	out_be32(reg, (in_be32(reg) & ~mask) \| bits);
	262
	263	cpm2_unmap(im_cpmux);
	264	return ret;
	265	}
	266
2652d4ec SW	267	int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
	268	{
	269	int ret = 0;
	270	int shift;
	271	int i, bits = 0;
	272	cpmux_t __iomem *im_cpmux;
	273	u8 __iomem *reg;
	274	u8 mask = 3;
	275
	276	u8 clk_map[][3] = {
	277	{CPM_CLK_SMC1, CPM_BRG1, 0},
	278	{CPM_CLK_SMC1, CPM_BRG7, 1},
	279	{CPM_CLK_SMC1, CPM_CLK7, 2},
	280	{CPM_CLK_SMC1, CPM_CLK9, 3},
	281	{CPM_CLK_SMC2, CPM_BRG2, 0},
	282	{CPM_CLK_SMC2, CPM_BRG8, 1},
	283	{CPM_CLK_SMC2, CPM_CLK4, 2},
	284	{CPM_CLK_SMC2, CPM_CLK15, 3},
	285	};
	286
	287	im_cpmux = cpm2_map(im_cpmux);
	288
	289	switch (target) {
	290	case CPM_CLK_SMC1:
	291	reg = &im_cpmux->cmx_smr;
	292	mask = 3;
	293	shift = 4;
	294	break;
	295	case CPM_CLK_SMC2:
	296	reg = &im_cpmux->cmx_smr;
	297	mask = 3;
	298	shift = 0;
	299	break;
	300	default:
	301	printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n");
	302	return -EINVAL;
	303	}
	304
	305	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
	306	if (clk_map[i][0] == target && clk_map[i][1] == clock) {
	307	bits = clk_map[i][2];
	308	break;
	309	}
	310	}
	311	if (i == ARRAY_SIZE(clk_map))
	312	ret = -EINVAL;
	313
	314	bits <<= shift;
	315	mask <<= shift;
	316
	317	out_8(reg, (in_8(reg) & ~mask) \| bits);
	318
	319	cpm2_unmap(im_cpmux);
	320	return ret;
	321	}
	322
7f21f529 SW	323	struct cpm2_ioports {
	324	u32 dir, par, sor, odr, dat;
	325	u32 res[3];
	326	};
	327
	328	void cpm2_set_pin(int port, int pin, int flags)
	329	{
	330	struct cpm2_ioports __iomem *iop =
	331	(struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
	332
	333	pin = 1 << (31 - pin);
	334
	335	if (flags & CPM_PIN_OUTPUT)
	336	setbits32(&iop[port].dir, pin);
	337	else
	338	clrbits32(&iop[port].dir, pin);
	339
	340	if (!(flags & CPM_PIN_GPIO))
	341	setbits32(&iop[port].par, pin);
	342	else
	343	clrbits32(&iop[port].par, pin);
	344
	345	if (flags & CPM_PIN_SECONDARY)
	346	setbits32(&iop[port].sor, pin);
	347	else
	348	clrbits32(&iop[port].sor, pin);
	349
	350	if (flags & CPM_PIN_OPENDRAIN)
	351	setbits32(&iop[port].odr, pin);
	352	else
	353	clrbits32(&iop[port].odr, pin);
	354	}
e193325e LP	355
	356	static int cpm_init_par_io(void)
	357	{
	358	struct device_node *np;
	359
	360	for_each_compatible_node(np, NULL, "fsl,cpm2-pario-bank")
	361	cpm2_gpiochip_add32(np);
	362	return 0;
	363	}
	364	arch_initcall(cpm_init_par_io);
	365