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b0c110b4 VB |
1 | /* |
2 | * General Purpose functions for the global management of the | |
3 | * 8260 Communication Processor Module. | |
4 | * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com> | |
5 | * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) | |
6 | * 2.3.99 Updates | |
7 | * | |
8 | * 2006 (c) MontaVista Software, Inc. | |
9 | * Vitaly Bordug <vbordug@ru.mvista.com> | |
10 | * Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c | |
11 | * | |
12 | * This file is licensed under the terms of the GNU General Public License | |
13 | * version 2. This program is licensed "as is" without any warranty of any | |
14 | * kind, whether express or implied. | |
15 | */ | |
16 | ||
17 | /* | |
18 | * | |
19 | * In addition to the individual control of the communication | |
20 | * channels, there are a few functions that globally affect the | |
21 | * communication processor. | |
22 | * | |
23 | * Buffer descriptors must be allocated from the dual ported memory | |
24 | * space. The allocator for that is here. When the communication | |
25 | * process is reset, we reclaim the memory available. There is | |
26 | * currently no deallocator for this memory. | |
27 | */ | |
28 | #include <linux/errno.h> | |
29 | #include <linux/sched.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/param.h> | |
32 | #include <linux/string.h> | |
33 | #include <linux/mm.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/module.h> | |
449012da SW |
36 | #include <linux/of.h> |
37 | ||
b0c110b4 VB |
38 | #include <asm/io.h> |
39 | #include <asm/irq.h> | |
40 | #include <asm/mpc8260.h> | |
41 | #include <asm/page.h> | |
42 | #include <asm/pgtable.h> | |
43 | #include <asm/cpm2.h> | |
44 | #include <asm/rheap.h> | |
45 | #include <asm/fs_pd.h> | |
46 | ||
47 | #include <sysdev/fsl_soc.h> | |
48 | ||
49 | static void cpm2_dpinit(void); | |
449012da | 50 | cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */ |
b0c110b4 VB |
51 | |
52 | /* We allocate this here because it is used almost exclusively for | |
53 | * the communication processor devices. | |
54 | */ | |
449012da | 55 | cpm2_map_t __iomem *cpm2_immr; |
b0c110b4 VB |
56 | |
57 | #define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount | |
58 | of space for CPM as it is larger | |
59 | than on PQ2 */ | |
60 | ||
61 | void | |
62 | cpm2_reset(void) | |
63 | { | |
449012da SW |
64 | #ifdef CONFIG_PPC_85xx |
65 | cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE); | |
66 | #else | |
67 | cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE); | |
68 | #endif | |
b0c110b4 VB |
69 | |
70 | /* Reclaim the DP memory for our use. | |
71 | */ | |
72 | cpm2_dpinit(); | |
73 | ||
74 | /* Tell everyone where the comm processor resides. | |
75 | */ | |
76 | cpmp = &cpm2_immr->im_cpm; | |
77 | } | |
78 | ||
79 | /* Set a baud rate generator. This needs lots of work. There are | |
80 | * eight BRGs, which can be connected to the CPM channels or output | |
81 | * as clocks. The BRGs are in two different block of internal | |
82 | * memory mapped space. | |
83 | * The baud rate clock is the system clock divided by something. | |
84 | * It was set up long ago during the initial boot phase and is | |
85 | * is given to us. | |
86 | * Baud rate clocks are zero-based in the driver code (as that maps | |
87 | * to port numbers). Documentation uses 1-based numbering. | |
88 | */ | |
89 | #define BRG_INT_CLK (get_brgfreq()) | |
90 | #define BRG_UART_CLK (BRG_INT_CLK/16) | |
91 | ||
92 | /* This function is used by UARTS, or anything else that uses a 16x | |
93 | * oversampled clock. | |
94 | */ | |
95 | void | |
96 | cpm_setbrg(uint brg, uint rate) | |
97 | { | |
449012da | 98 | u32 __iomem *bp; |
b0c110b4 VB |
99 | |
100 | /* This is good enough to get SMCs running..... | |
101 | */ | |
102 | if (brg < 4) { | |
fc8e50e3 | 103 | bp = cpm2_map_size(im_brgc1, 16); |
b0c110b4 | 104 | } else { |
fc8e50e3 | 105 | bp = cpm2_map_size(im_brgc5, 16); |
b0c110b4 VB |
106 | brg -= 4; |
107 | } | |
108 | bp += brg; | |
83fcdb4b | 109 | out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN); |
fc8e50e3 VB |
110 | |
111 | cpm2_unmap(bp); | |
b0c110b4 VB |
112 | } |
113 | ||
114 | /* This function is used to set high speed synchronous baud rate | |
115 | * clocks. | |
116 | */ | |
117 | void | |
118 | cpm2_fastbrg(uint brg, uint rate, int div16) | |
119 | { | |
449012da SW |
120 | u32 __iomem *bp; |
121 | u32 val; | |
b0c110b4 VB |
122 | |
123 | if (brg < 4) { | |
fc8e50e3 | 124 | bp = cpm2_map_size(im_brgc1, 16); |
b0c110b4 VB |
125 | } |
126 | else { | |
fc8e50e3 | 127 | bp = cpm2_map_size(im_brgc5, 16); |
b0c110b4 VB |
128 | brg -= 4; |
129 | } | |
130 | bp += brg; | |
449012da | 131 | val = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN; |
b0c110b4 | 132 | if (div16) |
449012da | 133 | val |= CPM_BRG_DIV16; |
fc8e50e3 | 134 | |
449012da | 135 | out_be32(bp, val); |
fc8e50e3 | 136 | cpm2_unmap(bp); |
b0c110b4 VB |
137 | } |
138 | ||
d3465c92 VB |
139 | int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode) |
140 | { | |
141 | int ret = 0; | |
142 | int shift; | |
143 | int i, bits = 0; | |
449012da SW |
144 | cpmux_t __iomem *im_cpmux; |
145 | u32 __iomem *reg; | |
d3465c92 VB |
146 | u32 mask = 7; |
147 | u8 clk_map [24][3] = { | |
148 | {CPM_CLK_FCC1, CPM_BRG5, 0}, | |
149 | {CPM_CLK_FCC1, CPM_BRG6, 1}, | |
150 | {CPM_CLK_FCC1, CPM_BRG7, 2}, | |
151 | {CPM_CLK_FCC1, CPM_BRG8, 3}, | |
152 | {CPM_CLK_FCC1, CPM_CLK9, 4}, | |
153 | {CPM_CLK_FCC1, CPM_CLK10, 5}, | |
154 | {CPM_CLK_FCC1, CPM_CLK11, 6}, | |
155 | {CPM_CLK_FCC1, CPM_CLK12, 7}, | |
156 | {CPM_CLK_FCC2, CPM_BRG5, 0}, | |
157 | {CPM_CLK_FCC2, CPM_BRG6, 1}, | |
158 | {CPM_CLK_FCC2, CPM_BRG7, 2}, | |
159 | {CPM_CLK_FCC2, CPM_BRG8, 3}, | |
160 | {CPM_CLK_FCC2, CPM_CLK13, 4}, | |
161 | {CPM_CLK_FCC2, CPM_CLK14, 5}, | |
162 | {CPM_CLK_FCC2, CPM_CLK15, 6}, | |
163 | {CPM_CLK_FCC2, CPM_CLK16, 7}, | |
164 | {CPM_CLK_FCC3, CPM_BRG5, 0}, | |
165 | {CPM_CLK_FCC3, CPM_BRG6, 1}, | |
166 | {CPM_CLK_FCC3, CPM_BRG7, 2}, | |
167 | {CPM_CLK_FCC3, CPM_BRG8, 3}, | |
168 | {CPM_CLK_FCC3, CPM_CLK13, 4}, | |
169 | {CPM_CLK_FCC3, CPM_CLK14, 5}, | |
170 | {CPM_CLK_FCC3, CPM_CLK15, 6}, | |
171 | {CPM_CLK_FCC3, CPM_CLK16, 7} | |
172 | }; | |
173 | ||
174 | im_cpmux = cpm2_map(im_cpmux); | |
175 | ||
176 | switch (target) { | |
177 | case CPM_CLK_SCC1: | |
178 | reg = &im_cpmux->cmx_scr; | |
179 | shift = 24; | |
180 | case CPM_CLK_SCC2: | |
181 | reg = &im_cpmux->cmx_scr; | |
182 | shift = 16; | |
183 | break; | |
184 | case CPM_CLK_SCC3: | |
185 | reg = &im_cpmux->cmx_scr; | |
186 | shift = 8; | |
187 | break; | |
188 | case CPM_CLK_SCC4: | |
189 | reg = &im_cpmux->cmx_scr; | |
190 | shift = 0; | |
191 | break; | |
192 | case CPM_CLK_FCC1: | |
193 | reg = &im_cpmux->cmx_fcr; | |
194 | shift = 24; | |
195 | break; | |
196 | case CPM_CLK_FCC2: | |
197 | reg = &im_cpmux->cmx_fcr; | |
198 | shift = 16; | |
199 | break; | |
200 | case CPM_CLK_FCC3: | |
201 | reg = &im_cpmux->cmx_fcr; | |
202 | shift = 8; | |
203 | break; | |
204 | default: | |
205 | printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n"); | |
206 | return -EINVAL; | |
207 | } | |
208 | ||
209 | if (mode == CPM_CLK_RX) | |
4b218e9b | 210 | shift += 3; |
d3465c92 VB |
211 | |
212 | for (i=0; i<24; i++) { | |
213 | if (clk_map[i][0] == target && clk_map[i][1] == clock) { | |
214 | bits = clk_map[i][2]; | |
215 | break; | |
216 | } | |
217 | } | |
218 | if (i == sizeof(clk_map)/3) | |
219 | ret = -EINVAL; | |
220 | ||
221 | bits <<= shift; | |
222 | mask <<= shift; | |
223 | out_be32(reg, (in_be32(reg) & ~mask) | bits); | |
224 | ||
225 | cpm2_unmap(im_cpmux); | |
226 | return ret; | |
227 | } | |
228 | ||
b0c110b4 VB |
229 | /* |
230 | * dpalloc / dpfree bits. | |
231 | */ | |
232 | static spinlock_t cpm_dpmem_lock; | |
233 | /* 16 blocks should be enough to satisfy all requests | |
234 | * until the memory subsystem goes up... */ | |
235 | static rh_block_t cpm_boot_dpmem_rh_block[16]; | |
236 | static rh_info_t cpm_dpmem_info; | |
449012da | 237 | static u8 __iomem *im_dprambase; |
b0c110b4 VB |
238 | |
239 | static void cpm2_dpinit(void) | |
240 | { | |
449012da SW |
241 | struct resource r; |
242 | ||
243 | #ifdef CONFIG_PPC_CPM_NEW_BINDING | |
244 | struct device_node *np; | |
245 | ||
246 | np = of_find_compatible_node(NULL, NULL, "fsl,cpm2"); | |
247 | if (!np) | |
248 | panic("Cannot find CPM2 node"); | |
b0c110b4 | 249 | |
449012da SW |
250 | if (of_address_to_resource(np, 1, &r)) |
251 | panic("Cannot get CPM2 resource 1"); | |
252 | ||
253 | of_node_put(np); | |
254 | #else | |
255 | r.start = CPM_MAP_ADDR; | |
256 | r.end = r.start + CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE - 1; | |
257 | #endif | |
258 | ||
259 | im_dprambase = ioremap(r.start, r.end - r.start + 1); | |
260 | if (!im_dprambase) | |
261 | panic("Cannot map DPRAM"); | |
262 | ||
263 | spin_lock_init(&cpm_dpmem_lock); | |
fc8e50e3 | 264 | |
b0c110b4 VB |
265 | /* initialize the info header */ |
266 | rh_init(&cpm_dpmem_info, 1, | |
267 | sizeof(cpm_boot_dpmem_rh_block) / | |
268 | sizeof(cpm_boot_dpmem_rh_block[0]), | |
269 | cpm_boot_dpmem_rh_block); | |
270 | ||
271 | /* Attach the usable dpmem area */ | |
272 | /* XXX: This is actually crap. CPM_DATAONLY_BASE and | |
273 | * CPM_DATAONLY_SIZE is only a subset of the available dpram. It | |
274 | * varies with the processor and the microcode patches activated. | |
275 | * But the following should be at least safe. | |
276 | */ | |
449012da | 277 | rh_attach_region(&cpm_dpmem_info, 0, r.end - r.start + 1); |
b0c110b4 VB |
278 | } |
279 | ||
280 | /* This function returns an index into the DPRAM area. | |
281 | */ | |
4c35630c | 282 | unsigned long cpm_dpalloc(uint size, uint align) |
b0c110b4 | 283 | { |
4c35630c | 284 | unsigned long start; |
b0c110b4 VB |
285 | unsigned long flags; |
286 | ||
287 | spin_lock_irqsave(&cpm_dpmem_lock, flags); | |
288 | cpm_dpmem_info.alignment = align; | |
289 | start = rh_alloc(&cpm_dpmem_info, size, "commproc"); | |
290 | spin_unlock_irqrestore(&cpm_dpmem_lock, flags); | |
291 | ||
292 | return (uint)start; | |
293 | } | |
294 | EXPORT_SYMBOL(cpm_dpalloc); | |
295 | ||
4c35630c | 296 | int cpm_dpfree(unsigned long offset) |
b0c110b4 VB |
297 | { |
298 | int ret; | |
299 | unsigned long flags; | |
300 | ||
301 | spin_lock_irqsave(&cpm_dpmem_lock, flags); | |
4c35630c | 302 | ret = rh_free(&cpm_dpmem_info, offset); |
b0c110b4 VB |
303 | spin_unlock_irqrestore(&cpm_dpmem_lock, flags); |
304 | ||
305 | return ret; | |
306 | } | |
307 | EXPORT_SYMBOL(cpm_dpfree); | |
308 | ||
309 | /* not sure if this is ever needed */ | |
4c35630c | 310 | unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align) |
b0c110b4 | 311 | { |
4c35630c | 312 | unsigned long start; |
b0c110b4 VB |
313 | unsigned long flags; |
314 | ||
315 | spin_lock_irqsave(&cpm_dpmem_lock, flags); | |
316 | cpm_dpmem_info.alignment = align; | |
4c35630c | 317 | start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc"); |
b0c110b4 VB |
318 | spin_unlock_irqrestore(&cpm_dpmem_lock, flags); |
319 | ||
4c35630c | 320 | return start; |
b0c110b4 VB |
321 | } |
322 | EXPORT_SYMBOL(cpm_dpalloc_fixed); | |
323 | ||
324 | void cpm_dpdump(void) | |
325 | { | |
326 | rh_dump(&cpm_dpmem_info); | |
327 | } | |
328 | EXPORT_SYMBOL(cpm_dpdump); | |
329 | ||
4c35630c | 330 | void *cpm_dpram_addr(unsigned long offset) |
b0c110b4 | 331 | { |
fc8e50e3 | 332 | return (void *)(im_dprambase + offset); |
b0c110b4 VB |
333 | } |
334 | EXPORT_SYMBOL(cpm_dpram_addr); |