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b0c110b4 VB |
1 | /* |
2 | * General Purpose functions for the global management of the | |
3 | * 8260 Communication Processor Module. | |
4 | * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com> | |
5 | * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) | |
6 | * 2.3.99 Updates | |
7 | * | |
8 | * 2006 (c) MontaVista Software, Inc. | |
9 | * Vitaly Bordug <vbordug@ru.mvista.com> | |
10 | * Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c | |
11 | * | |
12 | * This file is licensed under the terms of the GNU General Public License | |
13 | * version 2. This program is licensed "as is" without any warranty of any | |
14 | * kind, whether express or implied. | |
15 | */ | |
16 | ||
17 | /* | |
18 | * | |
19 | * In addition to the individual control of the communication | |
20 | * channels, there are a few functions that globally affect the | |
21 | * communication processor. | |
22 | * | |
23 | * Buffer descriptors must be allocated from the dual ported memory | |
24 | * space. The allocator for that is here. When the communication | |
25 | * process is reset, we reclaim the memory available. There is | |
26 | * currently no deallocator for this memory. | |
27 | */ | |
28 | #include <linux/errno.h> | |
29 | #include <linux/sched.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/param.h> | |
32 | #include <linux/string.h> | |
33 | #include <linux/mm.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/module.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/irq.h> | |
38 | #include <asm/mpc8260.h> | |
39 | #include <asm/page.h> | |
40 | #include <asm/pgtable.h> | |
41 | #include <asm/cpm2.h> | |
42 | #include <asm/rheap.h> | |
43 | #include <asm/fs_pd.h> | |
44 | ||
45 | #include <sysdev/fsl_soc.h> | |
46 | ||
47 | static void cpm2_dpinit(void); | |
48 | cpm_cpm2_t *cpmp; /* Pointer to comm processor space */ | |
49 | ||
50 | /* We allocate this here because it is used almost exclusively for | |
51 | * the communication processor devices. | |
52 | */ | |
53 | cpm2_map_t *cpm2_immr; | |
fc8e50e3 | 54 | intctl_cpm2_t *cpm2_intctl; |
b0c110b4 VB |
55 | |
56 | #define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount | |
57 | of space for CPM as it is larger | |
58 | than on PQ2 */ | |
59 | ||
60 | void | |
61 | cpm2_reset(void) | |
62 | { | |
63 | cpm2_immr = (cpm2_map_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE); | |
fc8e50e3 | 64 | cpm2_intctl = cpm2_map(im_intctl); |
b0c110b4 VB |
65 | |
66 | /* Reclaim the DP memory for our use. | |
67 | */ | |
68 | cpm2_dpinit(); | |
69 | ||
70 | /* Tell everyone where the comm processor resides. | |
71 | */ | |
72 | cpmp = &cpm2_immr->im_cpm; | |
73 | } | |
74 | ||
75 | /* Set a baud rate generator. This needs lots of work. There are | |
76 | * eight BRGs, which can be connected to the CPM channels or output | |
77 | * as clocks. The BRGs are in two different block of internal | |
78 | * memory mapped space. | |
79 | * The baud rate clock is the system clock divided by something. | |
80 | * It was set up long ago during the initial boot phase and is | |
81 | * is given to us. | |
82 | * Baud rate clocks are zero-based in the driver code (as that maps | |
83 | * to port numbers). Documentation uses 1-based numbering. | |
84 | */ | |
85 | #define BRG_INT_CLK (get_brgfreq()) | |
86 | #define BRG_UART_CLK (BRG_INT_CLK/16) | |
87 | ||
88 | /* This function is used by UARTS, or anything else that uses a 16x | |
89 | * oversampled clock. | |
90 | */ | |
91 | void | |
92 | cpm_setbrg(uint brg, uint rate) | |
93 | { | |
94 | volatile uint *bp; | |
95 | ||
96 | /* This is good enough to get SMCs running..... | |
97 | */ | |
98 | if (brg < 4) { | |
fc8e50e3 | 99 | bp = cpm2_map_size(im_brgc1, 16); |
b0c110b4 | 100 | } else { |
fc8e50e3 | 101 | bp = cpm2_map_size(im_brgc5, 16); |
b0c110b4 VB |
102 | brg -= 4; |
103 | } | |
104 | bp += brg; | |
105 | *bp = ((BRG_UART_CLK / rate) << 1) | CPM_BRG_EN; | |
fc8e50e3 VB |
106 | |
107 | cpm2_unmap(bp); | |
b0c110b4 VB |
108 | } |
109 | ||
110 | /* This function is used to set high speed synchronous baud rate | |
111 | * clocks. | |
112 | */ | |
113 | void | |
114 | cpm2_fastbrg(uint brg, uint rate, int div16) | |
115 | { | |
116 | volatile uint *bp; | |
117 | ||
118 | if (brg < 4) { | |
fc8e50e3 | 119 | bp = cpm2_map_size(im_brgc1, 16); |
b0c110b4 VB |
120 | } |
121 | else { | |
fc8e50e3 | 122 | bp = cpm2_map_size(im_brgc5, 16); |
b0c110b4 VB |
123 | brg -= 4; |
124 | } | |
125 | bp += brg; | |
126 | *bp = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN; | |
127 | if (div16) | |
128 | *bp |= CPM_BRG_DIV16; | |
fc8e50e3 VB |
129 | |
130 | cpm2_unmap(bp); | |
b0c110b4 VB |
131 | } |
132 | ||
133 | /* | |
134 | * dpalloc / dpfree bits. | |
135 | */ | |
136 | static spinlock_t cpm_dpmem_lock; | |
137 | /* 16 blocks should be enough to satisfy all requests | |
138 | * until the memory subsystem goes up... */ | |
139 | static rh_block_t cpm_boot_dpmem_rh_block[16]; | |
140 | static rh_info_t cpm_dpmem_info; | |
fc8e50e3 | 141 | static u8* im_dprambase; |
b0c110b4 VB |
142 | |
143 | static void cpm2_dpinit(void) | |
144 | { | |
145 | spin_lock_init(&cpm_dpmem_lock); | |
146 | ||
fc8e50e3 VB |
147 | im_dprambase = ioremap(CPM_MAP_ADDR, CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE); |
148 | ||
b0c110b4 VB |
149 | /* initialize the info header */ |
150 | rh_init(&cpm_dpmem_info, 1, | |
151 | sizeof(cpm_boot_dpmem_rh_block) / | |
152 | sizeof(cpm_boot_dpmem_rh_block[0]), | |
153 | cpm_boot_dpmem_rh_block); | |
154 | ||
155 | /* Attach the usable dpmem area */ | |
156 | /* XXX: This is actually crap. CPM_DATAONLY_BASE and | |
157 | * CPM_DATAONLY_SIZE is only a subset of the available dpram. It | |
158 | * varies with the processor and the microcode patches activated. | |
159 | * But the following should be at least safe. | |
160 | */ | |
161 | rh_attach_region(&cpm_dpmem_info, (void *)CPM_DATAONLY_BASE, | |
162 | CPM_DATAONLY_SIZE); | |
163 | } | |
164 | ||
165 | /* This function returns an index into the DPRAM area. | |
166 | */ | |
167 | uint cpm_dpalloc(uint size, uint align) | |
168 | { | |
169 | void *start; | |
170 | unsigned long flags; | |
171 | ||
172 | spin_lock_irqsave(&cpm_dpmem_lock, flags); | |
173 | cpm_dpmem_info.alignment = align; | |
174 | start = rh_alloc(&cpm_dpmem_info, size, "commproc"); | |
175 | spin_unlock_irqrestore(&cpm_dpmem_lock, flags); | |
176 | ||
177 | return (uint)start; | |
178 | } | |
179 | EXPORT_SYMBOL(cpm_dpalloc); | |
180 | ||
181 | int cpm_dpfree(uint offset) | |
182 | { | |
183 | int ret; | |
184 | unsigned long flags; | |
185 | ||
186 | spin_lock_irqsave(&cpm_dpmem_lock, flags); | |
187 | ret = rh_free(&cpm_dpmem_info, (void *)offset); | |
188 | spin_unlock_irqrestore(&cpm_dpmem_lock, flags); | |
189 | ||
190 | return ret; | |
191 | } | |
192 | EXPORT_SYMBOL(cpm_dpfree); | |
193 | ||
194 | /* not sure if this is ever needed */ | |
195 | uint cpm_dpalloc_fixed(uint offset, uint size, uint align) | |
196 | { | |
197 | void *start; | |
198 | unsigned long flags; | |
199 | ||
200 | spin_lock_irqsave(&cpm_dpmem_lock, flags); | |
201 | cpm_dpmem_info.alignment = align; | |
202 | start = rh_alloc_fixed(&cpm_dpmem_info, (void *)offset, size, "commproc"); | |
203 | spin_unlock_irqrestore(&cpm_dpmem_lock, flags); | |
204 | ||
205 | return (uint)start; | |
206 | } | |
207 | EXPORT_SYMBOL(cpm_dpalloc_fixed); | |
208 | ||
209 | void cpm_dpdump(void) | |
210 | { | |
211 | rh_dump(&cpm_dpmem_info); | |
212 | } | |
213 | EXPORT_SYMBOL(cpm_dpdump); | |
214 | ||
215 | void *cpm_dpram_addr(uint offset) | |
216 | { | |
fc8e50e3 | 217 | return (void *)(im_dprambase + offset); |
b0c110b4 VB |
218 | } |
219 | EXPORT_SYMBOL(cpm_dpram_addr); |