[deliverable/linux.git] / arch / powerpc / sysdev / cpm2_pic.c

/*
 * Platform information definitions.
 *
 * Copied from arch/ppc/syslib/cpm2_pic.c with minor subsequent updates
 * to make in work in arch/powerpc/. Original (c) belongs to Dan Malek.
 *
 * Author:  Vitaly Bordug <vbordug@ru.mvista.com>
 *
 * 1999-2001 (c) Dan Malek <dan@embeddedalley.com>
 * 2006 (c) MontaVista Software, Inc.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/* The CPM2 internal interrupt controller.  It is usually
 * the only interrupt controller.
 * There are two 32-bit registers (high/low) for up to 64
 * possible interrupts.
 *
 * Now, the fun starts.....Interrupt Numbers DO NOT MAP
 * in a simple arithmetic fashion to mask or pending registers.
 * That is, interrupt 4 does not map to bit position 4.
 * We create two tables, indexed by vector number, to indicate
 * which register to use and which bit in the register to use.
 */

#include <linux/stddef.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/signal.h>
#include <linux/irq.h>

#include <asm/immap_cpm2.h>
#include <asm/mpc8260.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/fs_pd.h>

#include "cpm2_pic.h"

/* External IRQS */
#define CPM2_IRQ_EXT1		19
#define CPM2_IRQ_EXT7		25

/* Port C IRQS */
#define CPM2_IRQ_PORTC15	48
#define CPM2_IRQ_PORTC0		63

static intctl_cpm2_t __iomem *cpm2_intctl;

static struct irq_domain *cpm2_pic_host;
static unsigned long ppc_cached_irq_mask[2]; /* 2 32-bit registers */

static const u_char irq_to_siureg[] = {
	1, 1, 1, 1, 1, 1, 1, 1,
	1, 1, 1, 1, 1, 1, 1, 1,
	0, 0, 0, 0, 0, 0, 0, 0,
	0, 0, 0, 0, 0, 0, 0, 0,
	1, 1, 1, 1, 1, 1, 1, 1,
	1, 1, 1, 1, 1, 1, 1, 1,
	0, 0, 0, 0, 0, 0, 0, 0,
	0, 0, 0, 0, 0, 0, 0, 0
};

/* bit numbers do not match the docs, these are precomputed so the bit for
 * a given irq is (1 << irq_to_siubit[irq]) */
static const u_char irq_to_siubit[] = {
	 0, 15, 14, 13, 12, 11, 10,  9,
	 8,  7,  6,  5,  4,  3,  2,  1,
	 2,  1,  0, 14, 13, 12, 11, 10,
	 9,  8,  7,  6,  5,  4,  3,  0,
	31, 30, 29, 28, 27, 26, 25, 24,
	23, 22, 21, 20, 19, 18, 17, 16,
	16, 17, 18, 19, 20, 21, 22, 23,
	24, 25, 26, 27, 28, 29, 30, 31,
};

static void cpm2_mask_irq(struct irq_data *d)
{
	int	bit, word;
	unsigned int irq_nr = irqd_to_hwirq(d);

	bit = irq_to_siubit[irq_nr];
	word = irq_to_siureg[irq_nr];

	ppc_cached_irq_mask[word] &= ~(1 << bit);
	out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
}

static void cpm2_unmask_irq(struct irq_data *d)
{
	int	bit, word;
	unsigned int irq_nr = irqd_to_hwirq(d);

	bit = irq_to_siubit[irq_nr];
	word = irq_to_siureg[irq_nr];

	ppc_cached_irq_mask[word] |= 1 << bit;
	out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
}

static void cpm2_ack(struct irq_data *d)
{
	int	bit, word;
	unsigned int irq_nr = irqd_to_hwirq(d);

	bit = irq_to_siubit[irq_nr];
	word = irq_to_siureg[irq_nr];

	out_be32(&cpm2_intctl->ic_sipnrh + word, 1 << bit);
}

static void cpm2_end_irq(struct irq_data *d)
{
	int	bit, word;
	unsigned int irq_nr = irqd_to_hwirq(d);

	bit = irq_to_siubit[irq_nr];
	word = irq_to_siureg[irq_nr];

	ppc_cached_irq_mask[word] |= 1 << bit;
	out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);

	/*
	 * Work around large numbers of spurious IRQs on PowerPC 82xx
	 * systems.
	 */
	mb();
}

static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
{
	unsigned int src = irqd_to_hwirq(d);
	unsigned int vold, vnew, edibit;

	/* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or
	 * IRQ_TYPE_EDGE_BOTH (default).  All others are IRQ_TYPE_EDGE_FALLING
	 * or IRQ_TYPE_LEVEL_LOW (default)
	 */
	if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) {
		if (flow_type == IRQ_TYPE_NONE)
			flow_type = IRQ_TYPE_EDGE_BOTH;

		if (flow_type != IRQ_TYPE_EDGE_BOTH &&
		    flow_type != IRQ_TYPE_EDGE_FALLING)
			goto err_sense;
	} else {
		if (flow_type == IRQ_TYPE_NONE)
			flow_type = IRQ_TYPE_LEVEL_LOW;

		if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
			goto err_sense;
	}

	irqd_set_trigger_type(d, flow_type);
	if (flow_type & IRQ_TYPE_LEVEL_LOW)
		__irq_set_handler_locked(d->irq, handle_level_irq);
	else
		__irq_set_handler_locked(d->irq, handle_edge_irq);

	/* internal IRQ senses are LEVEL_LOW
	 * EXT IRQ and Port C IRQ senses are programmable
	 */
	if (src >= CPM2_IRQ_EXT1 && src <= CPM2_IRQ_EXT7)
			edibit = (14 - (src - CPM2_IRQ_EXT1));
	else
		if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0)
			edibit = (31 - (CPM2_IRQ_PORTC0 - src));
		else
			return (flow_type & IRQ_TYPE_LEVEL_LOW) ?
				IRQ_SET_MASK_OK_NOCOPY : -EINVAL;

	vold = in_be32(&cpm2_intctl->ic_siexr);

	if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING)
		vnew = vold | (1 << edibit);
	else
		vnew = vold & ~(1 << edibit);

	if (vold != vnew)
		out_be32(&cpm2_intctl->ic_siexr, vnew);
	return IRQ_SET_MASK_OK_NOCOPY;

err_sense:
	pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type);
	return -EINVAL;
}

static struct irq_chip cpm2_pic = {
	.name = "CPM2 SIU",
	.irq_mask = cpm2_mask_irq,
	.irq_unmask = cpm2_unmask_irq,
	.irq_ack = cpm2_ack,
	.irq_eoi = cpm2_end_irq,
	.irq_set_type = cpm2_set_irq_type,
	.flags = IRQCHIP_EOI_IF_HANDLED,
};

unsigned int cpm2_get_irq(void)
{
	int irq;
	unsigned long bits;

       /* For CPM2, read the SIVEC register and shift the bits down
         * to get the irq number.         */
        bits = in_be32(&cpm2_intctl->ic_sivec);
        irq = bits >> 26;

	if (irq == 0)
		return(-1);
	return irq_linear_revmap(cpm2_pic_host, irq);
}

static int cpm2_pic_host_map(struct irq_domain *h, unsigned int virq,
			  irq_hw_number_t hw)
{
	pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);

	irq_set_status_flags(virq, IRQ_LEVEL);
	irq_set_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
	return 0;
}

static const struct irq_domain_ops cpm2_pic_host_ops = {
	.map = cpm2_pic_host_map,
	.xlate = irq_domain_xlate_onetwocell,
};

void cpm2_pic_init(struct device_node *node)
{
	int i;

	cpm2_intctl = cpm2_map(im_intctl);

	/* Clear the CPM IRQ controller, in case it has any bits set
	 * from the bootloader
	 */

	/* Mask out everything */

	out_be32(&cpm2_intctl->ic_simrh, 0x00000000);
	out_be32(&cpm2_intctl->ic_simrl, 0x00000000);

	wmb();

	/* Ack everything */
	out_be32(&cpm2_intctl->ic_sipnrh, 0xffffffff);
	out_be32(&cpm2_intctl->ic_sipnrl, 0xffffffff);
	wmb();

	/* Dummy read of the vector */
	i = in_be32(&cpm2_intctl->ic_sivec);
	rmb();

	/* Initialize the default interrupt mapping priorities,
	 * in case the boot rom changed something on us.
	 */
	out_be16(&cpm2_intctl->ic_sicr, 0);
	out_be32(&cpm2_intctl->ic_scprrh, 0x05309770);
	out_be32(&cpm2_intctl->ic_scprrl, 0x05309770);

	/* create a legacy host */
	cpm2_pic_host = irq_domain_add_linear(node, 64, &cpm2_pic_host_ops, NULL);
	if (cpm2_pic_host == NULL) {
		printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
		return;
	}
}
Commit	Line	Data
b0c110b4 VB	1	/*
	2	* Platform information definitions.
	3	*
	4	* Copied from arch/ppc/syslib/cpm2_pic.c with minor subsequent updates
	5	* to make in work in arch/powerpc/. Original (c) belongs to Dan Malek.
	6	*
	7	* Author: Vitaly Bordug <vbordug@ru.mvista.com>
	8	*
	9	* 1999-2001 (c) Dan Malek <dan@embeddedalley.com>
	10	* 2006 (c) MontaVista Software, Inc.
	11	*
	12	* This file is licensed under the terms of the GNU General Public License
	13	* version 2. This program is licensed "as is" without any warranty of any
	14	* kind, whether express or implied.
	15	*/
	16
	17	/* The CPM2 internal interrupt controller. It is usually
	18	* the only interrupt controller.
	19	* There are two 32-bit registers (high/low) for up to 64
	20	* possible interrupts.
	21	*
	22	* Now, the fun starts.....Interrupt Numbers DO NOT MAP
	23	* in a simple arithmetic fashion to mask or pending registers.
	24	* That is, interrupt 4 does not map to bit position 4.
	25	* We create two tables, indexed by vector number, to indicate
	26	* which register to use and which bit in the register to use.
	27	*/
	28
	29	#include <linux/stddef.h>
	30	#include <linux/init.h>
	31	#include <linux/sched.h>
	32	#include <linux/signal.h>
	33	#include <linux/irq.h>
	34
	35	#include <asm/immap_cpm2.h>
	36	#include <asm/mpc8260.h>
	37	#include <asm/io.h>
	38	#include <asm/prom.h>
73844ecb	39	#include <asm/fs_pd.h>
b0c110b4 VB	40
	41	#include "cpm2_pic.h"
	42
73844ecb VB	43	/* External IRQS */
	44	#define CPM2_IRQ_EXT1 19
	45	#define CPM2_IRQ_EXT7 25
	46
	47	/* Port C IRQS */
	48	#define CPM2_IRQ_PORTC15 48
	49	#define CPM2_IRQ_PORTC0 63
	50
449012da	51	static intctl_cpm2_t __iomem *cpm2_intctl;
73844ecb	52
bae1d8f1	53	static struct irq_domain *cpm2_pic_host;
4013369f	54	static unsigned long ppc_cached_irq_mask[2]; /* 2 32-bit registers */
b0c110b4 VB	55
	56	static const u_char irq_to_siureg[] = {
	57	1, 1, 1, 1, 1, 1, 1, 1,
	58	1, 1, 1, 1, 1, 1, 1, 1,
	59	0, 0, 0, 0, 0, 0, 0, 0,
	60	0, 0, 0, 0, 0, 0, 0, 0,
	61	1, 1, 1, 1, 1, 1, 1, 1,
	62	1, 1, 1, 1, 1, 1, 1, 1,
	63	0, 0, 0, 0, 0, 0, 0, 0,
	64	0, 0, 0, 0, 0, 0, 0, 0
	65	};
	66
	67	/* bit numbers do not match the docs, these are precomputed so the bit for
	68	* a given irq is (1 << irq_to_siubit[irq]) */
	69	static const u_char irq_to_siubit[] = {
	70	0, 15, 14, 13, 12, 11, 10, 9,
	71	8, 7, 6, 5, 4, 3, 2, 1,
	72	2, 1, 0, 14, 13, 12, 11, 10,
	73	9, 8, 7, 6, 5, 4, 3, 0,
	74	31, 30, 29, 28, 27, 26, 25, 24,
	75	23, 22, 21, 20, 19, 18, 17, 16,
	76	16, 17, 18, 19, 20, 21, 22, 23,
	77	24, 25, 26, 27, 28, 29, 30, 31,
	78	};
	79
c47eefa6	80	static void cpm2_mask_irq(struct irq_data *d)
b0c110b4 VB	81	{
b0c110b4 VB	82	int bit, word;
476eb491	83	unsigned int irq_nr = irqd_to_hwirq(d);
b0c110b4 VB	84
	85	bit = irq_to_siubit[irq_nr];
	86	word = irq_to_siureg[irq_nr];
	87
b0c110b4	88	ppc_cached_irq_mask[word] &= ~(1 << bit);
73844ecb	89	out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
b0c110b4 VB	90	}
b0c110b4 VB	91
c47eefa6	92	static void cpm2_unmask_irq(struct irq_data *d)
b0c110b4 VB	93	{
b0c110b4 VB	94	int bit, word;
476eb491	95	unsigned int irq_nr = irqd_to_hwirq(d);
b0c110b4 VB	96
	97	bit = irq_to_siubit[irq_nr];
	98	word = irq_to_siureg[irq_nr];
	99
b0c110b4	100	ppc_cached_irq_mask[word] \|= 1 << bit;
73844ecb	101	out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
b0c110b4 VB	102	}
b0c110b4 VB	103
c47eefa6	104	static void cpm2_ack(struct irq_data *d)
b0c110b4 VB	105	{
b0c110b4 VB	106	int bit, word;
476eb491	107	unsigned int irq_nr = irqd_to_hwirq(d);
b0c110b4 VB	108
	109	bit = irq_to_siubit[irq_nr];
	110	word = irq_to_siureg[irq_nr];
	111
73844ecb	112	out_be32(&cpm2_intctl->ic_sipnrh + word, 1 << bit);
b0c110b4 VB	113	}
b0c110b4 VB	114
c47eefa6	115	static void cpm2_end_irq(struct irq_data *d)
b0c110b4 VB	116	{
b0c110b4 VB	117	int bit, word;
476eb491	118	unsigned int irq_nr = irqd_to_hwirq(d);
b0c110b4	119
7bf811a8 TG	120	bit = irq_to_siubit[irq_nr];
7bf811a8 TG	121	word = irq_to_siureg[irq_nr];
b0c110b4	122
7bf811a8 TG	123	ppc_cached_irq_mask[word] \|= 1 << bit;
7bf811a8 TG	124	out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
73844ecb	125
7bf811a8 TG	126	/*
	127	* Work around large numbers of spurious IRQs on PowerPC 82xx
	128	* systems.
	129	*/
	130	mb();
b0c110b4 VB	131	}
b0c110b4 VB	132
c47eefa6	133	static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
73844ecb	134	{
476eb491	135	unsigned int src = irqd_to_hwirq(d);
73844ecb VB	136	unsigned int vold, vnew, edibit;
73844ecb VB	137
b22b97c1 MW	138	/* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or
	139	* IRQ_TYPE_EDGE_BOTH (default). All others are IRQ_TYPE_EDGE_FALLING
	140	* or IRQ_TYPE_LEVEL_LOW (default)
	141	*/
	142	if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) {
	143	if (flow_type == IRQ_TYPE_NONE)
	144	flow_type = IRQ_TYPE_EDGE_BOTH;
	145
	146	if (flow_type != IRQ_TYPE_EDGE_BOTH &&
	147	flow_type != IRQ_TYPE_EDGE_FALLING)
	148	goto err_sense;
	149	} else {
	150	if (flow_type == IRQ_TYPE_NONE)
	151	flow_type = IRQ_TYPE_LEVEL_LOW;
	152
	153	if (flow_type & (IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_LEVEL_HIGH))
	154	goto err_sense;
73844ecb VB	155	}
73844ecb VB	156
a28ab38c TG	157	irqd_set_trigger_type(d, flow_type);
a28ab38c TG	158	if (flow_type & IRQ_TYPE_LEVEL_LOW)
ec775d0e	159	__irq_set_handler_locked(d->irq, handle_level_irq);
a28ab38c	160	else
ec775d0e	161	__irq_set_handler_locked(d->irq, handle_edge_irq);
73844ecb VB	162
	163	/* internal IRQ senses are LEVEL_LOW
	164	* EXT IRQ and Port C IRQ senses are programmable
	165	*/
	166	if (src >= CPM2_IRQ_EXT1 && src <= CPM2_IRQ_EXT7)
	167	edibit = (14 - (src - CPM2_IRQ_EXT1));
	168	else
	169	if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0)
7f3ea17f	170	edibit = (31 - (CPM2_IRQ_PORTC0 - src));
73844ecb	171	else
a28ab38c TG	172	return (flow_type & IRQ_TYPE_LEVEL_LOW) ?
a28ab38c TG	173	IRQ_SET_MASK_OK_NOCOPY : -EINVAL;
73844ecb VB	174
	175	vold = in_be32(&cpm2_intctl->ic_siexr);
	176
	177	if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING)
	178	vnew = vold \| (1 << edibit);
	179	else
	180	vnew = vold & ~(1 << edibit);
	181
	182	if (vold != vnew)
	183	out_be32(&cpm2_intctl->ic_siexr, vnew);
a28ab38c	184	return IRQ_SET_MASK_OK_NOCOPY;
b22b97c1 MW	185
	186	err_sense:
	187	pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type);
	188	return -EINVAL;
73844ecb VB	189	}
73844ecb VB	190
b0c110b4	191	static struct irq_chip cpm2_pic = {
fc380c0c	192	.name = "CPM2 SIU",
c47eefa6 LB	193	.irq_mask = cpm2_mask_irq,
	194	.irq_unmask = cpm2_unmask_irq,
	195	.irq_ack = cpm2_ack,
	196	.irq_eoi = cpm2_end_irq,
	197	.irq_set_type = cpm2_set_irq_type,
7bf811a8	198	.flags = IRQCHIP_EOI_IF_HANDLED,
b0c110b4 VB	199	};
b0c110b4 VB	200
35a84c2f	201	unsigned int cpm2_get_irq(void)
b0c110b4 VB	202	{
	203	int irq;
	204	unsigned long bits;
	205
fc8e50e3 VB	206	/* For CPM2, read the SIVEC register and shift the bits down
fc8e50e3 VB	207	* to get the irq number. */
73844ecb	208	bits = in_be32(&cpm2_intctl->ic_sivec);
fc8e50e3	209	irq = bits >> 26;
b0c110b4 VB	210
	211	if (irq == 0)
	212	return(-1);
73844ecb	213	return irq_linear_revmap(cpm2_pic_host, irq);
b0c110b4 VB	214	}
b0c110b4 VB	215
bae1d8f1	216	static int cpm2_pic_host_map(struct irq_domain *h, unsigned int virq,
b0c110b4 VB	217	irq_hw_number_t hw)
	218	{
	219	pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
	220
98488db9	221	irq_set_status_flags(virq, IRQ_LEVEL);
ec775d0e	222	irq_set_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
b0c110b4 VB	223	return 0;
	224	}
	225
9f70b8eb	226	static const struct irq_domain_ops cpm2_pic_host_ops = {
b0c110b4	227	.map = cpm2_pic_host_map,
ff8c3ab8	228	.xlate = irq_domain_xlate_onetwocell,
b0c110b4 VB	229	};
	230
	231	void cpm2_pic_init(struct device_node *node)
	232	{
	233	int i;
	234
73844ecb VB	235	cpm2_intctl = cpm2_map(im_intctl);
73844ecb VB	236
b0c110b4 VB	237	/* Clear the CPM IRQ controller, in case it has any bits set
	238	* from the bootloader
	239	*/
	240
	241	/* Mask out everything */
	242
73844ecb VB	243	out_be32(&cpm2_intctl->ic_simrh, 0x00000000);
73844ecb VB	244	out_be32(&cpm2_intctl->ic_simrl, 0x00000000);
b0c110b4 VB	245
	246	wmb();
	247
	248	/* Ack everything */
73844ecb VB	249	out_be32(&cpm2_intctl->ic_sipnrh, 0xffffffff);
73844ecb VB	250	out_be32(&cpm2_intctl->ic_sipnrl, 0xffffffff);
b0c110b4 VB	251	wmb();
	252
	253	/* Dummy read of the vector */
73844ecb	254	i = in_be32(&cpm2_intctl->ic_sivec);
b0c110b4 VB	255	rmb();
	256
	257	/* Initialize the default interrupt mapping priorities,
	258	* in case the boot rom changed something on us.
	259	*/
73844ecb VB	260	out_be16(&cpm2_intctl->ic_sicr, 0);
	261	out_be32(&cpm2_intctl->ic_scprrh, 0x05309770);
	262	out_be32(&cpm2_intctl->ic_scprrl, 0x05309770);
b0c110b4 VB	263
b0c110b4 VB	264	/* create a legacy host */
a8db8cf0	265	cpm2_pic_host = irq_domain_add_linear(node, 64, &cpm2_pic_host_ops, NULL);
b0c110b4 VB	266	if (cpm2_pic_host == NULL) {
	267	printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
	268	return;
	269	}
	270	}