[deliverable/linux.git] / arch / powerpc / sysdev / cpm_common.c

/*
 * Common CPM code
 *
 * Author: Scott Wood <scottwood@freescale.com>
 *
 * Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
 *
 * Some parts derived from commproc.c/cpm2_common.c, which is:
 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
 * 2006 (c) MontaVista Software, Inc.
 * Vitaly Bordug <vbordug@ru.mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/spinlock.h>
#include <linux/export.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>

#include <asm/udbg.h>
#include <asm/io.h>
#include <asm/cpm.h>
#include <soc/fsl/qe/qe.h>

#include <mm/mmu_decl.h>

#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
#include <linux/of_gpio.h>
#endif

#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
static u32 __iomem *cpm_udbg_txdesc =
	(u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;

static void udbg_putc_cpm(char c)
{
	u8 __iomem *txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]);

	if (c == '\n')
		udbg_putc_cpm('\r');

	while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
		;

	out_8(txbuf, c);
	out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
}

void __init udbg_init_cpm(void)
{
	if (cpm_udbg_txdesc) {
#ifdef CONFIG_CPM2
		setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
#endif
		udbg_putc = udbg_putc_cpm;
	}
}
#endif

#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)

struct cpm2_ioports {
	u32 dir, par, sor, odr, dat;
	u32 res[3];
};

struct cpm2_gpio32_chip {
	struct of_mm_gpio_chip mm_gc;
	spinlock_t lock;

	/* shadowed data register to clear/set bits safely */
	u32 cpdata;
};

static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
{
	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;

	cpm2_gc->cpdata = in_be32(&iop->dat);
}

static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	u32 pin_mask;

	pin_mask = 1 << (31 - gpio);

	return !!(in_be32(&iop->dat) & pin_mask);
}

static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
	int value)
{
	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;

	if (value)
		cpm2_gc->cpdata |= pin_mask;
	else
		cpm2_gc->cpdata &= ~pin_mask;

	out_be32(&iop->dat, cpm2_gc->cpdata);
}

static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
	unsigned long flags;
	u32 pin_mask = 1 << (31 - gpio);

	spin_lock_irqsave(&cpm2_gc->lock, flags);

	__cpm2_gpio32_set(mm_gc, pin_mask, value);

	spin_unlock_irqrestore(&cpm2_gc->lock, flags);
}

static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	unsigned long flags;
	u32 pin_mask = 1 << (31 - gpio);

	spin_lock_irqsave(&cpm2_gc->lock, flags);

	setbits32(&iop->dir, pin_mask);
	__cpm2_gpio32_set(mm_gc, pin_mask, val);

	spin_unlock_irqrestore(&cpm2_gc->lock, flags);

	return 0;
}

static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	unsigned long flags;
	u32 pin_mask = 1 << (31 - gpio);

	spin_lock_irqsave(&cpm2_gc->lock, flags);

	clrbits32(&iop->dir, pin_mask);

	spin_unlock_irqrestore(&cpm2_gc->lock, flags);

	return 0;
}

int cpm2_gpiochip_add32(struct device_node *np)
{
	struct cpm2_gpio32_chip *cpm2_gc;
	struct of_mm_gpio_chip *mm_gc;
	struct gpio_chip *gc;

	cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
	if (!cpm2_gc)
		return -ENOMEM;

	spin_lock_init(&cpm2_gc->lock);

	mm_gc = &cpm2_gc->mm_gc;
	gc = &mm_gc->gc;

	mm_gc->save_regs = cpm2_gpio32_save_regs;
	gc->ngpio = 32;
	gc->direction_input = cpm2_gpio32_dir_in;
	gc->direction_output = cpm2_gpio32_dir_out;
	gc->get = cpm2_gpio32_get;
	gc->set = cpm2_gpio32_set;

	return of_mm_gpiochip_add_data(np, mm_gc, cpm2_gc);
}
#endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */
Commit	Line	Data
c374e00e SW	1	/*
	2	* Common CPM code
	3	*
	4	* Author: Scott Wood <scottwood@freescale.com>
	5	*
1661e5bd	6	* Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
c374e00e	7	*
15f8c604 SW	8	* Some parts derived from commproc.c/cpm2_common.c, which is:
	9	* Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
	10	* Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
	11	* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
	12	* 2006 (c) MontaVista Software, Inc.
	13	* Vitaly Bordug <vbordug@ru.mvista.com>
	14	*
c374e00e SW	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of version 2 of the GNU General Public License as
	17	* published by the Free Software Foundation.
	18	*/
	19
	20	#include <linux/init.h>
15f8c604	21	#include <linux/of_device.h>
e193325e	22	#include <linux/spinlock.h>
66b15db6	23	#include <linux/export.h>
e193325e	24	#include <linux/of.h>
26a2056e	25	#include <linux/of_address.h>
5a0e3ad6	26	#include <linux/slab.h>
15f8c604	27
c374e00e SW	28	#include <asm/udbg.h>
c374e00e SW	29	#include <asm/io.h>
15f8c604	30	#include <asm/cpm.h>
7aa1aa6e	31	#include <soc/fsl/qe/qe.h>
15f8c604	32
c374e00e SW	33	#include <mm/mmu_decl.h>
c374e00e SW	34
e193325e LP	35	#if defined(CONFIG_CPM2) \|\| defined(CONFIG_8xx_GPIO)
	36	#include <linux/of_gpio.h>
	37	#endif
	38
c374e00e SW	39	#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
	40	static u32 __iomem *cpm_udbg_txdesc =
	41	(u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
	42
	43	static void udbg_putc_cpm(char c)
	44	{
	45	u8 __iomem txbuf = (u8 __iomem __force )in_be32(&cpm_udbg_txdesc[1]);
	46
	47	if (c == '\n')
5e82eb33	48	udbg_putc_cpm('\r');
c374e00e SW	49
	50	while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
	51	;
	52
	53	out_8(txbuf, c);
	54	out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
	55	}
	56
	57	void __init udbg_init_cpm(void)
	58	{
	59	if (cpm_udbg_txdesc) {
	60	#ifdef CONFIG_CPM2
8d1cf34e	61	setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
c374e00e SW	62	#endif
	63	udbg_putc = udbg_putc_cpm;
	64	}
	65	}
	66	#endif
15f8c604	67
e193325e LP	68	#if defined(CONFIG_CPM2) \|\| defined(CONFIG_8xx_GPIO)
	69
	70	struct cpm2_ioports {
	71	u32 dir, par, sor, odr, dat;
	72	u32 res[3];
	73	};
	74
	75	struct cpm2_gpio32_chip {
	76	struct of_mm_gpio_chip mm_gc;
	77	spinlock_t lock;
	78
	79	/* shadowed data register to clear/set bits safely */
	80	u32 cpdata;
	81	};
	82
e193325e LP	83	static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
e193325e LP	84	{
a14a2d48	85	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc);
e193325e LP	86	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	87
	88	cpm2_gc->cpdata = in_be32(&iop->dat);
	89	}
	90
	91	static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
	92	{
	93	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	94	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	95	u32 pin_mask;
	96
	97	pin_mask = 1 << (31 - gpio);
	98
	99	return !!(in_be32(&iop->dat) & pin_mask);
	100	}
	101
639d6445 LP	102	static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
639d6445 LP	103	int value)
e193325e	104	{
a14a2d48	105	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc);
e193325e	106	struct cpm2_ioports __iomem *iop = mm_gc->regs;
e193325e LP	107
	108	if (value)
	109	cpm2_gc->cpdata \|= pin_mask;
	110	else
	111	cpm2_gc->cpdata &= ~pin_mask;
	112
	113	out_be32(&iop->dat, cpm2_gc->cpdata);
639d6445 LP	114	}
	115
	116	static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
	117	{
	118	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
a14a2d48	119	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
639d6445 LP	120	unsigned long flags;
	121	u32 pin_mask = 1 << (31 - gpio);
	122
	123	spin_lock_irqsave(&cpm2_gc->lock, flags);
	124
	125	__cpm2_gpio32_set(mm_gc, pin_mask, value);
e193325e LP	126
	127	spin_unlock_irqrestore(&cpm2_gc->lock, flags);
	128	}
	129
	130	static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	131	{
	132	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
a14a2d48	133	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
e193325e	134	struct cpm2_ioports __iomem *iop = mm_gc->regs;
639d6445 LP	135	unsigned long flags;
639d6445 LP	136	u32 pin_mask = 1 << (31 - gpio);
e193325e	137
639d6445	138	spin_lock_irqsave(&cpm2_gc->lock, flags);
e193325e LP	139
e193325e LP	140	setbits32(&iop->dir, pin_mask);
639d6445	141	__cpm2_gpio32_set(mm_gc, pin_mask, val);
e193325e	142
639d6445	143	spin_unlock_irqrestore(&cpm2_gc->lock, flags);
e193325e LP	144
	145	return 0;
	146	}
	147
	148	static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
	149	{
	150	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
a14a2d48	151	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
e193325e	152	struct cpm2_ioports __iomem *iop = mm_gc->regs;
639d6445 LP	153	unsigned long flags;
639d6445 LP	154	u32 pin_mask = 1 << (31 - gpio);
e193325e	155
639d6445	156	spin_lock_irqsave(&cpm2_gc->lock, flags);
e193325e LP	157
	158	clrbits32(&iop->dir, pin_mask);
	159
639d6445 LP	160	spin_unlock_irqrestore(&cpm2_gc->lock, flags);
639d6445 LP	161
e193325e LP	162	return 0;
	163	}
	164
	165	int cpm2_gpiochip_add32(struct device_node *np)
	166	{
	167	struct cpm2_gpio32_chip *cpm2_gc;
	168	struct of_mm_gpio_chip *mm_gc;
e193325e LP	169	struct gpio_chip *gc;
	170
	171	cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
	172	if (!cpm2_gc)
	173	return -ENOMEM;
	174
	175	spin_lock_init(&cpm2_gc->lock);
	176
	177	mm_gc = &cpm2_gc->mm_gc;
a19e3da5	178	gc = &mm_gc->gc;
e193325e LP	179
e193325e LP	180	mm_gc->save_regs = cpm2_gpio32_save_regs;
e193325e LP	181	gc->ngpio = 32;
	182	gc->direction_input = cpm2_gpio32_dir_in;
	183	gc->direction_output = cpm2_gpio32_dir_out;
	184	gc->get = cpm2_gpio32_get;
	185	gc->set = cpm2_gpio32_set;
	186
a14a2d48	187	return of_mm_gpiochip_add_data(np, mm_gc, cpm2_gc);
e193325e LP	188	}
e193325e LP	189	#endif /* CONFIG_CPM2 \|\| CONFIG_8xx_GPIO */