Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1beb6a7d | 2 | * arch/powerpc/sysdev/dart_iommu.c |
1da177e4 | 3 | * |
91f14480 | 4 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
1beb6a7d BH |
5 | * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>, |
6 | * IBM Corporation | |
1da177e4 LT |
7 | * |
8 | * Based on pSeries_iommu.c: | |
9 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation | |
91f14480 | 10 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
1da177e4 | 11 | * |
1beb6a7d BH |
12 | * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu. |
13 | * | |
1da177e4 | 14 | * |
1da177e4 LT |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
1beb6a7d | 19 | * |
1da177e4 LT |
20 | * This program is distributed in the hope that it will be useful, |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
1beb6a7d | 24 | * |
1da177e4 LT |
25 | * You should have received a copy of the GNU General Public License |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/init.h> |
31 | #include <linux/types.h> | |
1da177e4 LT |
32 | #include <linux/mm.h> |
33 | #include <linux/spinlock.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/dma-mapping.h> | |
37 | #include <linux/vmalloc.h> | |
7e11580b | 38 | #include <linux/suspend.h> |
95f72d1e | 39 | #include <linux/memblock.h> |
5a0e3ad6 | 40 | #include <linux/gfp.h> |
1da177e4 LT |
41 | #include <asm/io.h> |
42 | #include <asm/prom.h> | |
1da177e4 LT |
43 | #include <asm/iommu.h> |
44 | #include <asm/pci-bridge.h> | |
45 | #include <asm/machdep.h> | |
1da177e4 | 46 | #include <asm/cacheflush.h> |
d387899f | 47 | #include <asm/ppc-pci.h> |
1da177e4 | 48 | |
9933f299 DG |
49 | #include "dart.h" |
50 | ||
1da177e4 LT |
51 | /* Physical base address and size of the DART table */ |
52 | unsigned long dart_tablebase; /* exported to htab_initialize */ | |
53 | static unsigned long dart_tablesize; | |
54 | ||
55 | /* Virtual base address of the DART table */ | |
56 | static u32 *dart_vbase; | |
7e11580b JB |
57 | #ifdef CONFIG_PM |
58 | static u32 *dart_copy; | |
59 | #endif | |
1da177e4 LT |
60 | |
61 | /* Mapped base address for the dart */ | |
6fa2ffe9 | 62 | static unsigned int __iomem *dart; |
1da177e4 LT |
63 | |
64 | /* Dummy val that entries are set to when unused */ | |
65 | static unsigned int dart_emptyval; | |
66 | ||
1beb6a7d BH |
67 | static struct iommu_table iommu_table_dart; |
68 | static int iommu_table_dart_inited; | |
1da177e4 | 69 | static int dart_dirty; |
1beb6a7d | 70 | static int dart_is_u4; |
1da177e4 | 71 | |
8fb07c04 BH |
72 | #define DART_U4_BYPASS_BASE 0x8000000000ull |
73 | ||
1da177e4 LT |
74 | #define DBG(...) |
75 | ||
d900bd73 AB |
76 | static DEFINE_SPINLOCK(invalidate_lock); |
77 | ||
1da177e4 LT |
78 | static inline void dart_tlb_invalidate_all(void) |
79 | { | |
80 | unsigned long l = 0; | |
1beb6a7d | 81 | unsigned int reg, inv_bit; |
1da177e4 | 82 | unsigned long limit; |
d900bd73 AB |
83 | unsigned long flags; |
84 | ||
85 | spin_lock_irqsave(&invalidate_lock, flags); | |
1da177e4 LT |
86 | |
87 | DBG("dart: flush\n"); | |
88 | ||
89 | /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the | |
90 | * control register and wait for it to clear. | |
91 | * | |
92 | * Gotcha: Sometimes, the DART won't detect that the bit gets | |
93 | * set. If so, clear it and set it again. | |
1beb6a7d | 94 | */ |
1da177e4 LT |
95 | |
96 | limit = 0; | |
97 | ||
1beb6a7d | 98 | inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB; |
1da177e4 | 99 | retry: |
1da177e4 | 100 | l = 0; |
1beb6a7d BH |
101 | reg = DART_IN(DART_CNTL); |
102 | reg |= inv_bit; | |
103 | DART_OUT(DART_CNTL, reg); | |
104 | ||
105 | while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit)) | |
1da177e4 | 106 | l++; |
1beb6a7d | 107 | if (l == (1L << limit)) { |
1da177e4 LT |
108 | if (limit < 4) { |
109 | limit++; | |
feb76c7b OJ |
110 | reg = DART_IN(DART_CNTL); |
111 | reg &= ~inv_bit; | |
1beb6a7d | 112 | DART_OUT(DART_CNTL, reg); |
1da177e4 LT |
113 | goto retry; |
114 | } else | |
1beb6a7d | 115 | panic("DART: TLB did not flush after waiting a long " |
1da177e4 LT |
116 | "time. Buggy U3 ?"); |
117 | } | |
d900bd73 AB |
118 | |
119 | spin_unlock_irqrestore(&invalidate_lock, flags); | |
1da177e4 LT |
120 | } |
121 | ||
feb76c7b OJ |
122 | static inline void dart_tlb_invalidate_one(unsigned long bus_rpn) |
123 | { | |
124 | unsigned int reg; | |
125 | unsigned int l, limit; | |
d900bd73 AB |
126 | unsigned long flags; |
127 | ||
128 | spin_lock_irqsave(&invalidate_lock, flags); | |
feb76c7b OJ |
129 | |
130 | reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE | | |
131 | (bus_rpn & DART_CNTL_U4_IONE_MASK); | |
132 | DART_OUT(DART_CNTL, reg); | |
133 | ||
134 | limit = 0; | |
135 | wait_more: | |
136 | l = 0; | |
137 | while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) { | |
138 | rmb(); | |
139 | l++; | |
140 | } | |
141 | ||
142 | if (l == (1L << limit)) { | |
143 | if (limit < 4) { | |
144 | limit++; | |
145 | goto wait_more; | |
146 | } else | |
147 | panic("DART: TLB did not flush after waiting a long " | |
148 | "time. Buggy U4 ?"); | |
149 | } | |
d900bd73 AB |
150 | |
151 | spin_unlock_irqrestore(&invalidate_lock, flags); | |
feb76c7b OJ |
152 | } |
153 | ||
1da177e4 LT |
154 | static void dart_flush(struct iommu_table *tbl) |
155 | { | |
eeac5c14 | 156 | mb(); |
feb76c7b | 157 | if (dart_dirty) { |
1da177e4 | 158 | dart_tlb_invalidate_all(); |
feb76c7b OJ |
159 | dart_dirty = 0; |
160 | } | |
1da177e4 LT |
161 | } |
162 | ||
6490c490 | 163 | static int dart_build(struct iommu_table *tbl, long index, |
1da177e4 | 164 | long npages, unsigned long uaddr, |
4f3dd8a0 MN |
165 | enum dma_data_direction direction, |
166 | struct dma_attrs *attrs) | |
1da177e4 LT |
167 | { |
168 | unsigned int *dp; | |
169 | unsigned int rpn; | |
feb76c7b | 170 | long l; |
1da177e4 LT |
171 | |
172 | DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr); | |
173 | ||
174 | dp = ((unsigned int*)tbl->it_base) + index; | |
1beb6a7d | 175 | |
af901ca1 | 176 | /* On U3, all memory is contiguous, so we can move this |
1da177e4 LT |
177 | * out of the loop. |
178 | */ | |
feb76c7b OJ |
179 | l = npages; |
180 | while (l--) { | |
579468a9 | 181 | rpn = __pa(uaddr) >> DART_PAGE_SHIFT; |
1da177e4 LT |
182 | |
183 | *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK); | |
184 | ||
d0035c62 | 185 | uaddr += DART_PAGE_SIZE; |
1da177e4 LT |
186 | } |
187 | ||
eeac5c14 BH |
188 | /* make sure all updates have reached memory */ |
189 | mb(); | |
190 | in_be32((unsigned __iomem *)dp); | |
191 | mb(); | |
192 | ||
feb76c7b OJ |
193 | if (dart_is_u4) { |
194 | rpn = index; | |
feb76c7b OJ |
195 | while (npages--) |
196 | dart_tlb_invalidate_one(rpn++); | |
197 | } else { | |
198 | dart_dirty = 1; | |
199 | } | |
6490c490 | 200 | return 0; |
1da177e4 LT |
201 | } |
202 | ||
203 | ||
204 | static void dart_free(struct iommu_table *tbl, long index, long npages) | |
205 | { | |
206 | unsigned int *dp; | |
1beb6a7d | 207 | |
1da177e4 LT |
208 | /* We don't worry about flushing the TLB cache. The only drawback of |
209 | * not doing it is that we won't catch buggy device drivers doing | |
210 | * bad DMAs, but then no 32-bit architecture ever does either. | |
211 | */ | |
212 | ||
213 | DBG("dart: free at: %lx, %lx\n", index, npages); | |
214 | ||
215 | dp = ((unsigned int *)tbl->it_base) + index; | |
1beb6a7d | 216 | |
1da177e4 LT |
217 | while (npages--) |
218 | *(dp++) = dart_emptyval; | |
219 | } | |
220 | ||
221 | ||
109b60f0 | 222 | static int __init dart_init(struct device_node *dart_node) |
1da177e4 | 223 | { |
1da177e4 | 224 | unsigned int i; |
1beb6a7d BH |
225 | unsigned long tmp, base, size; |
226 | struct resource r; | |
1da177e4 LT |
227 | |
228 | if (dart_tablebase == 0 || dart_tablesize == 0) { | |
1beb6a7d BH |
229 | printk(KERN_INFO "DART: table not allocated, using " |
230 | "direct DMA\n"); | |
1da177e4 LT |
231 | return -ENODEV; |
232 | } | |
233 | ||
1beb6a7d BH |
234 | if (of_address_to_resource(dart_node, 0, &r)) |
235 | panic("DART: can't get register base ! "); | |
236 | ||
1da177e4 LT |
237 | /* Make sure nothing from the DART range remains in the CPU cache |
238 | * from a previous mapping that existed before the kernel took | |
239 | * over | |
240 | */ | |
1beb6a7d BH |
241 | flush_dcache_phys_range(dart_tablebase, |
242 | dart_tablebase + dart_tablesize); | |
1da177e4 LT |
243 | |
244 | /* Allocate a spare page to map all invalid DART pages. We need to do | |
245 | * that to work around what looks like a problem with the HT bridge | |
246 | * prefetching into invalid pages and corrupting data | |
247 | */ | |
95f72d1e | 248 | tmp = memblock_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE); |
1beb6a7d BH |
249 | dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) & |
250 | DARTMAP_RPNMASK); | |
1da177e4 | 251 | |
1beb6a7d | 252 | /* Map in DART registers */ |
28f65c11 | 253 | dart = ioremap(r.start, resource_size(&r)); |
1da177e4 | 254 | if (dart == NULL) |
1beb6a7d | 255 | panic("DART: Cannot map registers!"); |
1da177e4 | 256 | |
1beb6a7d | 257 | /* Map in DART table */ |
579468a9 | 258 | dart_vbase = ioremap(__pa(dart_tablebase), dart_tablesize); |
1da177e4 LT |
259 | |
260 | /* Fill initial table */ | |
261 | for (i = 0; i < dart_tablesize/4; i++) | |
262 | dart_vbase[i] = dart_emptyval; | |
263 | ||
264 | /* Initialize DART with table base and enable it. */ | |
1beb6a7d BH |
265 | base = dart_tablebase >> DART_PAGE_SHIFT; |
266 | size = dart_tablesize >> DART_PAGE_SHIFT; | |
267 | if (dart_is_u4) { | |
56c8eaee | 268 | size &= DART_SIZE_U4_SIZE_MASK; |
1beb6a7d BH |
269 | DART_OUT(DART_BASE_U4, base); |
270 | DART_OUT(DART_SIZE_U4, size); | |
271 | DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE); | |
272 | } else { | |
56c8eaee | 273 | size &= DART_CNTL_U3_SIZE_MASK; |
1beb6a7d BH |
274 | DART_OUT(DART_CNTL, |
275 | DART_CNTL_U3_ENABLE | | |
276 | (base << DART_CNTL_U3_BASE_SHIFT) | | |
277 | (size << DART_CNTL_U3_SIZE_SHIFT)); | |
278 | } | |
1da177e4 LT |
279 | |
280 | /* Invalidate DART to get rid of possible stale TLBs */ | |
281 | dart_tlb_invalidate_all(); | |
282 | ||
1beb6a7d BH |
283 | printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n", |
284 | dart_is_u4 ? "U4" : "U3"); | |
1da177e4 LT |
285 | |
286 | return 0; | |
287 | } | |
288 | ||
1beb6a7d | 289 | static void iommu_table_dart_setup(void) |
1da177e4 | 290 | { |
1beb6a7d BH |
291 | iommu_table_dart.it_busno = 0; |
292 | iommu_table_dart.it_offset = 0; | |
1da177e4 | 293 | /* it_size is in number of entries */ |
5d2efba6 | 294 | iommu_table_dart.it_size = dart_tablesize / sizeof(u32); |
1da177e4 LT |
295 | |
296 | /* Initialize the common IOMMU code */ | |
1beb6a7d BH |
297 | iommu_table_dart.it_base = (unsigned long)dart_vbase; |
298 | iommu_table_dart.it_index = 0; | |
299 | iommu_table_dart.it_blocksize = 1; | |
ca1588e7 | 300 | iommu_init_table(&iommu_table_dart, -1); |
1da177e4 LT |
301 | |
302 | /* Reserve the last page of the DART to avoid possible prefetch | |
303 | * past the DART mapped area | |
304 | */ | |
1beb6a7d | 305 | set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map); |
1da177e4 LT |
306 | } |
307 | ||
8fb07c04 | 308 | static void dma_dev_setup_dart(struct device *dev) |
1da177e4 | 309 | { |
1da177e4 LT |
310 | /* We only have one iommu table on the mac for now, which makes |
311 | * things simple. Setup all PCI devices to point to this table | |
1da177e4 | 312 | */ |
8fb07c04 BH |
313 | if (get_dma_ops(dev) == &dma_direct_ops) |
314 | set_dma_offset(dev, DART_U4_BYPASS_BASE); | |
315 | else | |
316 | set_iommu_table_base(dev, &iommu_table_dart); | |
317 | } | |
318 | ||
319 | static void pci_dma_dev_setup_dart(struct pci_dev *dev) | |
320 | { | |
321 | dma_dev_setup_dart(&dev->dev); | |
1da177e4 LT |
322 | } |
323 | ||
12d04eef | 324 | static void pci_dma_bus_setup_dart(struct pci_bus *bus) |
1da177e4 | 325 | { |
1beb6a7d BH |
326 | if (!iommu_table_dart_inited) { |
327 | iommu_table_dart_inited = 1; | |
328 | iommu_table_dart_setup(); | |
1da177e4 | 329 | } |
1da177e4 LT |
330 | } |
331 | ||
8fb07c04 BH |
332 | static bool dart_device_on_pcie(struct device *dev) |
333 | { | |
334 | struct device_node *np = of_node_get(dev->of_node); | |
335 | ||
336 | while(np) { | |
337 | if (of_device_is_compatible(np, "U4-pcie") || | |
338 | of_device_is_compatible(np, "u4-pcie")) { | |
339 | of_node_put(np); | |
340 | return true; | |
341 | } | |
342 | np = of_get_next_parent(np); | |
343 | } | |
344 | return false; | |
345 | } | |
346 | ||
347 | static int dart_dma_set_mask(struct device *dev, u64 dma_mask) | |
348 | { | |
349 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
350 | return -EIO; | |
351 | ||
352 | /* U4 supports a DART bypass, we use it for 64-bit capable | |
353 | * devices to improve performances. However, that only works | |
354 | * for devices connected to U4 own PCIe interface, not bridged | |
355 | * through hypertransport. We need the device to support at | |
356 | * least 40 bits of addresses. | |
357 | */ | |
358 | if (dart_device_on_pcie(dev) && dma_mask >= DMA_BIT_MASK(40)) { | |
359 | dev_info(dev, "Using 64-bit DMA iommu bypass\n"); | |
360 | set_dma_ops(dev, &dma_direct_ops); | |
361 | } else { | |
362 | dev_info(dev, "Using 32-bit DMA via iommu\n"); | |
363 | set_dma_ops(dev, &dma_iommu_ops); | |
364 | } | |
365 | dma_dev_setup_dart(dev); | |
366 | ||
367 | *dev->dma_mask = dma_mask; | |
368 | return 0; | |
369 | } | |
370 | ||
109b60f0 | 371 | void __init iommu_init_early_dart(void) |
1da177e4 LT |
372 | { |
373 | struct device_node *dn; | |
374 | ||
375 | /* Find the DART in the device-tree */ | |
376 | dn = of_find_compatible_node(NULL, "dart", "u3-dart"); | |
1beb6a7d BH |
377 | if (dn == NULL) { |
378 | dn = of_find_compatible_node(NULL, "dart", "u4-dart"); | |
379 | if (dn == NULL) | |
34c4d012 | 380 | return; /* use default direct_dma_ops */ |
1beb6a7d BH |
381 | dart_is_u4 = 1; |
382 | } | |
1da177e4 | 383 | |
8fb07c04 BH |
384 | /* Initialize the DART HW */ |
385 | if (dart_init(dn) != 0) | |
386 | goto bail; | |
387 | ||
1da177e4 LT |
388 | /* Setup low level TCE operations for the core IOMMU code */ |
389 | ppc_md.tce_build = dart_build; | |
390 | ppc_md.tce_free = dart_free; | |
391 | ppc_md.tce_flush = dart_flush; | |
392 | ||
8fb07c04 BH |
393 | /* Setup bypass if supported */ |
394 | if (dart_is_u4) | |
395 | ppc_md.dma_set_mask = dart_dma_set_mask; | |
1da177e4 | 396 | |
8fb07c04 BH |
397 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_dart; |
398 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_dart; | |
399 | ||
400 | /* Setup pci_dma ops */ | |
401 | set_pci_dma_ops(&dma_iommu_ops); | |
402 | return; | |
1beb6a7d BH |
403 | |
404 | bail: | |
405 | /* If init failed, use direct iommu and null setup functions */ | |
12d04eef BH |
406 | ppc_md.pci_dma_dev_setup = NULL; |
407 | ppc_md.pci_dma_bus_setup = NULL; | |
1beb6a7d BH |
408 | |
409 | /* Setup pci_dma ops */ | |
98747770 | 410 | set_pci_dma_ops(&dma_direct_ops); |
1da177e4 LT |
411 | } |
412 | ||
7e11580b JB |
413 | #ifdef CONFIG_PM |
414 | static void iommu_dart_save(void) | |
415 | { | |
416 | memcpy(dart_copy, dart_vbase, 2*1024*1024); | |
417 | } | |
418 | ||
419 | static void iommu_dart_restore(void) | |
420 | { | |
421 | memcpy(dart_vbase, dart_copy, 2*1024*1024); | |
422 | dart_tlb_invalidate_all(); | |
423 | } | |
424 | ||
425 | static int __init iommu_init_late_dart(void) | |
426 | { | |
427 | unsigned long tbasepfn; | |
428 | struct page *p; | |
429 | ||
430 | /* if no dart table exists then we won't need to save it | |
431 | * and the area has also not been reserved */ | |
432 | if (!dart_tablebase) | |
433 | return 0; | |
434 | ||
435 | tbasepfn = __pa(dart_tablebase) >> PAGE_SHIFT; | |
436 | register_nosave_region_late(tbasepfn, | |
437 | tbasepfn + ((1<<24) >> PAGE_SHIFT)); | |
438 | ||
439 | /* For suspend we need to copy the dart contents because | |
440 | * it is not part of the regular mapping (see above) and | |
441 | * thus not saved automatically. The memory for this copy | |
442 | * must be allocated early because we need 2 MB. */ | |
443 | p = alloc_pages(GFP_KERNEL, 21 - PAGE_SHIFT); | |
444 | BUG_ON(!p); | |
445 | dart_copy = page_address(p); | |
446 | ||
447 | ppc_md.iommu_save = iommu_dart_save; | |
448 | ppc_md.iommu_restore = iommu_dart_restore; | |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
453 | late_initcall(iommu_init_late_dart); | |
454 | #endif | |
1da177e4 | 455 | |
1beb6a7d | 456 | void __init alloc_dart_table(void) |
1da177e4 | 457 | { |
28897731 | 458 | /* Only reserve DART space if machine has more than 1GB of RAM |
1da177e4 | 459 | * or if requested with iommu=on on cmdline. |
28897731 OJ |
460 | * |
461 | * 1GB of RAM is picked as limit because some default devices | |
462 | * (i.e. Airport Extreme) have 30 bit address range limits. | |
1da177e4 | 463 | */ |
28897731 OJ |
464 | |
465 | if (iommu_is_off) | |
466 | return; | |
467 | ||
95f72d1e | 468 | if (!iommu_force_on && memblock_end_of_DRAM() <= 0x40000000ull) |
1da177e4 LT |
469 | return; |
470 | ||
471 | /* 512 pages (2MB) is max DART tablesize. */ | |
472 | dart_tablesize = 1UL << 21; | |
473 | /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we | |
474 | * will blow up an entire large page anyway in the kernel mapping | |
475 | */ | |
476 | dart_tablebase = (unsigned long) | |
579468a9 | 477 | __va(memblock_alloc_base(1UL<<24, 1UL<<24, 0x80000000L)); |
1da177e4 | 478 | |
1beb6a7d | 479 | printk(KERN_INFO "DART table allocated at: %lx\n", dart_tablebase); |
1da177e4 | 480 | } |