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6db92cc9 | 1 | /* |
163f22dc | 2 | * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc |
6db92cc9 HR |
3 | * |
4 | * QorIQ based Cache Controller Memory Mapped Registers | |
5 | * | |
6 | * Author: Vivek Mahajan <vivek.mahajan@freescale.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #ifndef __FSL_85XX_CACHE_CTLR_H__ | |
24 | #define __FSL_85XX_CACHE_CTLR_H__ | |
25 | ||
26 | #define L2CR_L2FI 0x40000000 /* L2 flash invalidate */ | |
27 | #define L2CR_L2IO 0x00200000 /* L2 instruction only */ | |
28 | #define L2CR_SRAM_ZERO 0x00000000 /* L2SRAM zero size */ | |
29 | #define L2CR_SRAM_FULL 0x00010000 /* L2SRAM full size */ | |
30 | #define L2CR_SRAM_HALF 0x00020000 /* L2SRAM half size */ | |
31 | #define L2CR_SRAM_TWO_HALFS 0x00030000 /* L2SRAM two half sizes */ | |
32 | #define L2CR_SRAM_QUART 0x00040000 /* L2SRAM one quarter size */ | |
33 | #define L2CR_SRAM_TWO_QUARTS 0x00050000 /* L2SRAM two quarter size */ | |
34 | #define L2CR_SRAM_EIGHTH 0x00060000 /* L2SRAM one eighth size */ | |
35 | #define L2CR_SRAM_TWO_EIGHTH 0x00070000 /* L2SRAM two eighth size */ | |
36 | ||
37 | #define L2SRAM_OPTIMAL_SZ_SHIFT 0x00000003 /* Optimum size for L2SRAM */ | |
38 | ||
39 | #define L2SRAM_BAR_MSK_LO18 0xFFFFC000 /* Lower 18 bits */ | |
40 | #define L2SRAM_BARE_MSK_HI4 0x0000000F /* Upper 4 bits */ | |
41 | ||
42 | enum cache_sram_lock_ways { | |
43 | LOCK_WAYS_ZERO, | |
44 | LOCK_WAYS_EIGHTH, | |
45 | LOCK_WAYS_TWO_EIGHTH, | |
46 | LOCK_WAYS_HALF = 4, | |
47 | LOCK_WAYS_FULL = 8, | |
48 | }; | |
49 | ||
50 | struct mpc85xx_l2ctlr { | |
51 | u32 ctl; /* 0x000 - L2 control */ | |
52 | u8 res1[0xC]; | |
53 | u32 ewar0; /* 0x010 - External write address 0 */ | |
54 | u32 ewarea0; /* 0x014 - External write address extended 0 */ | |
55 | u32 ewcr0; /* 0x018 - External write ctrl */ | |
56 | u8 res2[4]; | |
57 | u32 ewar1; /* 0x020 - External write address 1 */ | |
58 | u32 ewarea1; /* 0x024 - External write address extended 1 */ | |
59 | u32 ewcr1; /* 0x028 - External write ctrl 1 */ | |
60 | u8 res3[4]; | |
61 | u32 ewar2; /* 0x030 - External write address 2 */ | |
62 | u32 ewarea2; /* 0x034 - External write address extended 2 */ | |
63 | u32 ewcr2; /* 0x038 - External write ctrl 2 */ | |
64 | u8 res4[4]; | |
65 | u32 ewar3; /* 0x040 - External write address 3 */ | |
66 | u32 ewarea3; /* 0x044 - External write address extended 3 */ | |
67 | u32 ewcr3; /* 0x048 - External write ctrl 3 */ | |
68 | u8 res5[0xB4]; | |
69 | u32 srbar0; /* 0x100 - SRAM base address 0 */ | |
70 | u32 srbarea0; /* 0x104 - SRAM base addr reg ext address 0 */ | |
71 | u32 srbar1; /* 0x108 - SRAM base address 1 */ | |
72 | u32 srbarea1; /* 0x10C - SRAM base addr reg ext address 1 */ | |
73 | u8 res6[0xCF0]; | |
74 | u32 errinjhi; /* 0xE00 - Error injection mask high */ | |
75 | u32 errinjlo; /* 0xE04 - Error injection mask low */ | |
76 | u32 errinjctl; /* 0xE08 - Error injection tag/ecc control */ | |
77 | u8 res7[0x14]; | |
78 | u32 captdatahi; /* 0xE20 - Error data high capture */ | |
79 | u32 captdatalo; /* 0xE24 - Error data low capture */ | |
80 | u32 captecc; /* 0xE28 - Error syndrome */ | |
81 | u8 res8[0x14]; | |
82 | u32 errdet; /* 0xE40 - Error detect */ | |
83 | u32 errdis; /* 0xE44 - Error disable */ | |
84 | u32 errinten; /* 0xE48 - Error interrupt enable */ | |
85 | u32 errattr; /* 0xE4c - Error attribute capture */ | |
86 | u32 erradrrl; /* 0xE50 - Error address capture low */ | |
87 | u32 erradrrh; /* 0xE54 - Error address capture high */ | |
88 | u32 errctl; /* 0xE58 - Error control */ | |
89 | u8 res9[0x1A4]; | |
90 | }; | |
91 | ||
92 | struct sram_parameters { | |
93 | unsigned int sram_size; | |
163f22dc | 94 | phys_addr_t sram_offset; |
6db92cc9 HR |
95 | }; |
96 | ||
97 | extern int instantiate_cache_sram(struct platform_device *dev, | |
98 | struct sram_parameters sram_params); | |
99 | extern void remove_cache_sram(struct platform_device *dev); | |
100 | ||
101 | #endif /* __FSL_85XX_CACHE_CTLR_H__ */ |