[deliverable/linux.git] / arch / powerpc / sysdev / fsl_85xx_l2ctlr.c

/*
 * Copyright 2009-2010 Freescale Semiconductor, Inc.
 *
 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
 *
 * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <asm/io.h>

#include "fsl_85xx_cache_ctlr.h"

static char *sram_size;
static char *sram_offset;
struct mpc85xx_l2ctlr __iomem *l2ctlr;

static long get_cache_sram_size(void)
{
	unsigned long val;

	if (!sram_size || (strict_strtoul(sram_size, 0, &val) < 0))
		return -EINVAL;

	return val;
}

static long get_cache_sram_offset(void)
{
	unsigned long val;

	if (!sram_offset || (strict_strtoul(sram_offset, 0, &val) < 0))
		return -EINVAL;

	return val;
}

static int __init get_size_from_cmdline(char *str)
{
	if (!str)
		return 0;

	sram_size = str;
	return 1;
}

static int __init get_offset_from_cmdline(char *str)
{
	if (!str)
		return 0;

	sram_offset = str;
	return 1;
}

__setup("cache-sram-size=", get_size_from_cmdline);
__setup("cache-sram-offset=", get_offset_from_cmdline);

static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
{
	long rval;
	unsigned int rem;
	unsigned char ways;
	const unsigned int *prop;
	unsigned int l2cache_size;
	struct sram_parameters sram_params;

	if (!dev->dev.of_node) {
		dev_err(&dev->dev, "Device's OF-node is NULL\n");
		return -EINVAL;
	}

	prop = of_get_property(dev->dev.of_node, "cache-size", NULL);
	if (!prop) {
		dev_err(&dev->dev, "Missing L2 cache-size\n");
		return -EINVAL;
	}
	l2cache_size = *prop;

	sram_params.sram_size  = get_cache_sram_size();
	if ((int)sram_params.sram_size <= 0) {
		dev_err(&dev->dev,
			"Entire L2 as cache, Aborting Cache-SRAM stuff\n");
		return -EINVAL;
	}

	sram_params.sram_offset  = get_cache_sram_offset();
	if ((int64_t)sram_params.sram_offset <= 0) {
		dev_err(&dev->dev,
			"Entire L2 as cache, provide a valid sram offset\n");
		return -EINVAL;
	}


	rem = l2cache_size % sram_params.sram_size;
	ways = LOCK_WAYS_FULL * sram_params.sram_size / l2cache_size;
	if (rem || (ways & (ways - 1))) {
		dev_err(&dev->dev, "Illegal cache-sram-size in command line\n");
		return -EINVAL;
	}

	l2ctlr = of_iomap(dev->dev.of_node, 0);
	if (!l2ctlr) {
		dev_err(&dev->dev, "Can't map L2 controller\n");
		return -EINVAL;
	}

	/*
	 * Write bits[0-17] to srbar0
	 */
	out_be32(&l2ctlr->srbar0,
		sram_params.sram_offset & L2SRAM_BAR_MSK_LO18);

	/*
	 * Write bits[18-21] to srbare0
	 */
#ifdef CONFIG_PHYS_64BIT
	out_be32(&l2ctlr->srbarea0,
		(sram_params.sram_offset >> 32) & L2SRAM_BARE_MSK_HI4);
#endif

	clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);

	switch (ways) {
	case LOCK_WAYS_EIGHTH:
		setbits32(&l2ctlr->ctl,
			L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
		break;

	case LOCK_WAYS_TWO_EIGHTH:
		setbits32(&l2ctlr->ctl,
			L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART);
		break;

	case LOCK_WAYS_HALF:
		setbits32(&l2ctlr->ctl,
			L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
		break;

	case LOCK_WAYS_FULL:
	default:
		setbits32(&l2ctlr->ctl,
			L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
		break;
	}
	eieio();

	rval = instantiate_cache_sram(dev, sram_params);
	if (rval < 0) {
		dev_err(&dev->dev, "Can't instantiate Cache-SRAM\n");
		iounmap(l2ctlr);
		return -EINVAL;
	}

	return 0;
}

static int __devexit mpc85xx_l2ctlr_of_remove(struct platform_device *dev)
{
	BUG_ON(!l2ctlr);

	iounmap(l2ctlr);
	remove_cache_sram(dev);
	dev_info(&dev->dev, "MPC85xx L2 controller unloaded\n");

	return 0;
}

static struct of_device_id mpc85xx_l2ctlr_of_match[] = {
	{
		.compatible = "fsl,p2020-l2-cache-controller",
	},
	{
		.compatible = "fsl,p2010-l2-cache-controller",
	},
	{
		.compatible = "fsl,p1020-l2-cache-controller",
	},
	{
		.compatible = "fsl,p1011-l2-cache-controller",
	},
	{
		.compatible = "fsl,p1013-l2-cache-controller",
	},
	{
		.compatible = "fsl,p1022-l2-cache-controller",
	},
	{
		.compatible = "fsl,mpc8548-l2-cache-controller",
	},
	{},
};

static struct platform_driver mpc85xx_l2ctlr_of_platform_driver = {
	.driver	= {
		.name		= "fsl-l2ctlr",
		.owner		= THIS_MODULE,
		.of_match_table	= mpc85xx_l2ctlr_of_match,
	},
	.probe		= mpc85xx_l2ctlr_of_probe,
	.remove		= __devexit_p(mpc85xx_l2ctlr_of_remove),
};

static __init int mpc85xx_l2ctlr_of_init(void)
{
	return platform_driver_register(&mpc85xx_l2ctlr_of_platform_driver);
}

static void __exit mpc85xx_l2ctlr_of_exit(void)
{
	platform_driver_unregister(&mpc85xx_l2ctlr_of_platform_driver);
}

subsys_initcall(mpc85xx_l2ctlr_of_init);
module_exit(mpc85xx_l2ctlr_of_exit);

MODULE_DESCRIPTION("Freescale MPC85xx L2 controller init");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
6db92cc9 HR	1	/*
	2	* Copyright 2009-2010 Freescale Semiconductor, Inc.
	3	*
	4	* QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
	5	*
	6	* Author: Vivek Mahajan <vivek.mahajan@freescale.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/kernel.h>
e4399461	24	#include <linux/module.h>
6db92cc9 HR	25	#include <linux/of_platform.h>
	26	#include <asm/io.h>
	27
	28	#include "fsl_85xx_cache_ctlr.h"
	29
	30	static char *sram_size;
	31	static char *sram_offset;
	32	struct mpc85xx_l2ctlr __iomem *l2ctlr;
	33
	34	static long get_cache_sram_size(void)
	35	{
	36	unsigned long val;
	37
	38	if (!sram_size \|\| (strict_strtoul(sram_size, 0, &val) < 0))
	39	return -EINVAL;
	40
	41	return val;
	42	}
	43
	44	static long get_cache_sram_offset(void)
	45	{
	46	unsigned long val;
	47
	48	if (!sram_offset \|\| (strict_strtoul(sram_offset, 0, &val) < 0))
	49	return -EINVAL;
	50
	51	return val;
	52	}
	53
	54	static int __init get_size_from_cmdline(char *str)
	55	{
	56	if (!str)
	57	return 0;
	58
	59	sram_size = str;
	60	return 1;
	61	}
	62
	63	static int __init get_offset_from_cmdline(char *str)
	64	{
	65	if (!str)
	66	return 0;
	67
	68	sram_offset = str;
	69	return 1;
	70	}
	71
	72	__setup("cache-sram-size=", get_size_from_cmdline);
	73	__setup("cache-sram-offset=", get_offset_from_cmdline);
	74
00006124	75	static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
6db92cc9 HR	76	{
	77	long rval;
	78	unsigned int rem;
	79	unsigned char ways;
	80	const unsigned int *prop;
	81	unsigned int l2cache_size;
	82	struct sram_parameters sram_params;
	83
	84	if (!dev->dev.of_node) {
	85	dev_err(&dev->dev, "Device's OF-node is NULL\n");
	86	return -EINVAL;
	87	}
	88
	89	prop = of_get_property(dev->dev.of_node, "cache-size", NULL);
	90	if (!prop) {
	91	dev_err(&dev->dev, "Missing L2 cache-size\n");
	92	return -EINVAL;
	93	}
	94	l2cache_size = *prop;
	95
	96	sram_params.sram_size = get_cache_sram_size();
b0aea14b	97	if ((int)sram_params.sram_size <= 0) {
6db92cc9 HR	98	dev_err(&dev->dev,
	99	"Entire L2 as cache, Aborting Cache-SRAM stuff\n");
	100	return -EINVAL;
	101	}
	102
	103	sram_params.sram_offset = get_cache_sram_offset();
b0aea14b	104	if ((int64_t)sram_params.sram_offset <= 0) {
6db92cc9 HR	105	dev_err(&dev->dev,
	106	"Entire L2 as cache, provide a valid sram offset\n");
	107	return -EINVAL;
	108	}
	109
	110
	111	rem = l2cache_size % sram_params.sram_size;
	112	ways = LOCK_WAYS_FULL * sram_params.sram_size / l2cache_size;
	113	if (rem \|\| (ways & (ways - 1))) {
	114	dev_err(&dev->dev, "Illegal cache-sram-size in command line\n");
	115	return -EINVAL;
	116	}
	117
	118	l2ctlr = of_iomap(dev->dev.of_node, 0);
	119	if (!l2ctlr) {
	120	dev_err(&dev->dev, "Can't map L2 controller\n");
	121	return -EINVAL;
	122	}
	123
	124	/*
	125	* Write bits[0-17] to srbar0
	126	*/
	127	out_be32(&l2ctlr->srbar0,
	128	sram_params.sram_offset & L2SRAM_BAR_MSK_LO18);
	129
	130	/*
	131	* Write bits[18-21] to srbare0
	132	*/
	133	#ifdef CONFIG_PHYS_64BIT
	134	out_be32(&l2ctlr->srbarea0,
	135	(sram_params.sram_offset >> 32) & L2SRAM_BARE_MSK_HI4);
	136	#endif
	137
	138	clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);
	139
	140	switch (ways) {
	141	case LOCK_WAYS_EIGHTH:
	142	setbits32(&l2ctlr->ctl,
	143	L2CR_L2E \| L2CR_L2FI \| L2CR_SRAM_EIGHTH);
	144	break;
	145
	146	case LOCK_WAYS_TWO_EIGHTH:
	147	setbits32(&l2ctlr->ctl,
	148	L2CR_L2E \| L2CR_L2FI \| L2CR_SRAM_QUART);
	149	break;
	150
	151	case LOCK_WAYS_HALF:
	152	setbits32(&l2ctlr->ctl,
	153	L2CR_L2E \| L2CR_L2FI \| L2CR_SRAM_HALF);
	154	break;
	155
	156	case LOCK_WAYS_FULL:
	157	default:
	158	setbits32(&l2ctlr->ctl,
	159	L2CR_L2E \| L2CR_L2FI \| L2CR_SRAM_FULL);
	160	break;
	161	}
	162	eieio();
	163
	164	rval = instantiate_cache_sram(dev, sram_params);
	165	if (rval < 0) {
	166	dev_err(&dev->dev, "Can't instantiate Cache-SRAM\n");
	167	iounmap(l2ctlr);
	168	return -EINVAL;
169	}
170
171	return 0;
172	}
173
174	static int __devexit mpc85xx_l2ctlr_of_remove(struct platform_device *dev)
175	{
176	BUG_ON(!l2ctlr);
177
178	iounmap(l2ctlr);
179	remove_cache_sram(dev);
180	dev_info(&dev->dev, "MPC85xx L2 controller unloaded\n");
181
182	return 0;
183	}
184
185	static struct of_device_id mpc85xx_l2ctlr_of_match[] = {
186	{
187	.compatible = "fsl,p2020-l2-cache-controller",
188	},
189	{
190	.compatible = "fsl,p2010-l2-cache-controller",
191	},
192	{
193	.compatible = "fsl,p1020-l2-cache-controller",
194	},
195	{
196	.compatible = "fsl,p1011-l2-cache-controller",
197	},
198	{
199	.compatible = "fsl,p1013-l2-cache-controller",
200	},
201	{
202	.compatible = "fsl,p1022-l2-cache-controller",
203	},
401a376e	204	{
	205	.compatible = "fsl,mpc8548-l2-cache-controller",
	206	},
6db92cc9 HR	207	{},
	208	};
	209
00006124	210	static struct platform_driver mpc85xx_l2ctlr_of_platform_driver = {
6db92cc9 HR	211	.driver = {
	212	.name = "fsl-l2ctlr",
	213	.owner = THIS_MODULE,
	214	.of_match_table = mpc85xx_l2ctlr_of_match,
	215	},
	216	.probe = mpc85xx_l2ctlr_of_probe,
	217	.remove = __devexit_p(mpc85xx_l2ctlr_of_remove),
	218	};
	219
	220	static __init int mpc85xx_l2ctlr_of_init(void)
	221	{
00006124	222	return platform_driver_register(&mpc85xx_l2ctlr_of_platform_driver);
6db92cc9 HR	223	}
	224
	225	static void __exit mpc85xx_l2ctlr_of_exit(void)
	226	{
00006124	227	platform_driver_unregister(&mpc85xx_l2ctlr_of_platform_driver);
6db92cc9 HR	228	}
	229
	230	subsys_initcall(mpc85xx_l2ctlr_of_init);
	231	module_exit(mpc85xx_l2ctlr_of_exit);
	232
	233	MODULE_DESCRIPTION("Freescale MPC85xx L2 controller init");
	234	MODULE_LICENSE("GPL v2");