Commit | Line | Data |
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34e36c15 | 1 | /* |
6820fead | 2 | * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. |
34e36c15 JJ |
3 | * |
4 | * Author: Tony Li <tony.li@freescale.com> | |
5 | * Jason Jin <Jason.jin@freescale.com> | |
6 | * | |
7 | * The hwirq alloc and free code reuse from sysdev/mpic_msi.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; version 2 of the | |
12 | * License. | |
13 | * | |
14 | */ | |
15 | #include <linux/irq.h> | |
16 | #include <linux/bootmem.h> | |
34e36c15 JJ |
17 | #include <linux/msi.h> |
18 | #include <linux/pci.h> | |
5a0e3ad6 | 19 | #include <linux/slab.h> |
34e36c15 JJ |
20 | #include <linux/of_platform.h> |
21 | #include <sysdev/fsl_soc.h> | |
22 | #include <asm/prom.h> | |
23 | #include <asm/hw_irq.h> | |
24 | #include <asm/ppc-pci.h> | |
02adac60 | 25 | #include <asm/mpic.h> |
34e36c15 | 26 | #include "fsl_msi.h" |
b8f44ec2 | 27 | #include "fsl_pci.h" |
34e36c15 | 28 | |
694a7a36 LY |
29 | LIST_HEAD(msi_head); |
30 | ||
34e36c15 JJ |
31 | struct fsl_msi_feature { |
32 | u32 fsl_pic_ip; | |
33 | u32 msiir_offset; | |
34 | }; | |
35 | ||
02adac60 LY |
36 | struct fsl_msi_cascade_data { |
37 | struct fsl_msi *msi_data; | |
38 | int index; | |
39 | }; | |
34e36c15 JJ |
40 | |
41 | static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg) | |
42 | { | |
43 | return in_be32(base + (reg >> 2)); | |
44 | } | |
45 | ||
34e36c15 JJ |
46 | /* |
47 | * We do not need this actually. The MSIR register has been read once | |
48 | * in the cascade interrupt. So, this MSI interrupt has been acked | |
49 | */ | |
37e16615 | 50 | static void fsl_msi_end_irq(struct irq_data *d) |
34e36c15 JJ |
51 | { |
52 | } | |
53 | ||
54 | static struct irq_chip fsl_msi_chip = { | |
1c9db525 TG |
55 | .irq_mask = mask_msi_irq, |
56 | .irq_unmask = unmask_msi_irq, | |
37e16615 | 57 | .irq_ack = fsl_msi_end_irq, |
fc380c0c | 58 | .name = "FSL-MSI", |
34e36c15 JJ |
59 | }; |
60 | ||
61 | static int fsl_msi_host_map(struct irq_host *h, unsigned int virq, | |
62 | irq_hw_number_t hw) | |
63 | { | |
80818813 | 64 | struct fsl_msi *msi_data = h->host_data; |
34e36c15 JJ |
65 | struct irq_chip *chip = &fsl_msi_chip; |
66 | ||
98488db9 | 67 | irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING); |
34e36c15 | 68 | |
ec775d0e TG |
69 | irq_set_chip_data(virq, msi_data); |
70 | irq_set_chip_and_handler(virq, chip, handle_edge_irq); | |
34e36c15 JJ |
71 | |
72 | return 0; | |
73 | } | |
74 | ||
75 | static struct irq_host_ops fsl_msi_host_ops = { | |
76 | .map = fsl_msi_host_map, | |
77 | }; | |
78 | ||
34e36c15 JJ |
79 | static int fsl_msi_init_allocator(struct fsl_msi *msi_data) |
80 | { | |
692d1037 | 81 | int rc; |
34e36c15 | 82 | |
7e7ab367 ME |
83 | rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS, |
84 | msi_data->irqhost->of_node); | |
85 | if (rc) | |
86 | return rc; | |
34e36c15 | 87 | |
7e7ab367 ME |
88 | rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap); |
89 | if (rc < 0) { | |
90 | msi_bitmap_free(&msi_data->bitmap); | |
91 | return rc; | |
34e36c15 JJ |
92 | } |
93 | ||
34e36c15 | 94 | return 0; |
34e36c15 JJ |
95 | } |
96 | ||
97 | static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type) | |
98 | { | |
99 | if (type == PCI_CAP_ID_MSIX) | |
100 | pr_debug("fslmsi: MSI-X untested, trying anyway.\n"); | |
101 | ||
102 | return 0; | |
103 | } | |
104 | ||
105 | static void fsl_teardown_msi_irqs(struct pci_dev *pdev) | |
106 | { | |
107 | struct msi_desc *entry; | |
80818813 | 108 | struct fsl_msi *msi_data; |
34e36c15 JJ |
109 | |
110 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
111 | if (entry->irq == NO_IRQ) | |
112 | continue; | |
ec775d0e TG |
113 | msi_data = irq_get_handler_data(entry->irq); |
114 | irq_set_msi_desc(entry->irq, NULL); | |
7e7ab367 ME |
115 | msi_bitmap_free_hwirqs(&msi_data->bitmap, |
116 | virq_to_hw(entry->irq), 1); | |
34e36c15 JJ |
117 | irq_dispose_mapping(entry->irq); |
118 | } | |
119 | ||
120 | return; | |
121 | } | |
122 | ||
123 | static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, | |
80818813 LCB |
124 | struct msi_msg *msg, |
125 | struct fsl_msi *fsl_msi_data) | |
34e36c15 | 126 | { |
80818813 | 127 | struct fsl_msi *msi_data = fsl_msi_data; |
3da34aae | 128 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
b8f44ec2 | 129 | u64 base = fsl_pci_immrbar_base(hose); |
34e36c15 | 130 | |
b8f44ec2 KG |
131 | msg->address_lo = msi_data->msi_addr_lo + lower_32_bits(base); |
132 | msg->address_hi = msi_data->msi_addr_hi + upper_32_bits(base); | |
3da34aae | 133 | |
34e36c15 JJ |
134 | msg->data = hwirq; |
135 | ||
136 | pr_debug("%s: allocated srs: %d, ibs: %d\n", | |
137 | __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG); | |
138 | } | |
139 | ||
140 | static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |
141 | { | |
694a7a36 | 142 | int rc, hwirq = -ENOMEM; |
34e36c15 JJ |
143 | unsigned int virq; |
144 | struct msi_desc *entry; | |
145 | struct msi_msg msg; | |
80818813 | 146 | struct fsl_msi *msi_data; |
34e36c15 JJ |
147 | |
148 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
694a7a36 LY |
149 | list_for_each_entry(msi_data, &msi_head, list) { |
150 | hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1); | |
151 | if (hwirq >= 0) | |
152 | break; | |
153 | } | |
80818813 | 154 | |
34e36c15 JJ |
155 | if (hwirq < 0) { |
156 | rc = hwirq; | |
157 | pr_debug("%s: fail allocating msi interrupt\n", | |
158 | __func__); | |
159 | goto out_free; | |
160 | } | |
161 | ||
162 | virq = irq_create_mapping(msi_data->irqhost, hwirq); | |
163 | ||
164 | if (virq == NO_IRQ) { | |
7e7ab367 | 165 | pr_debug("%s: fail mapping hwirq 0x%x\n", |
34e36c15 | 166 | __func__, hwirq); |
7e7ab367 | 167 | msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1); |
34e36c15 JJ |
168 | rc = -ENOSPC; |
169 | goto out_free; | |
170 | } | |
ec775d0e TG |
171 | irq_set_handler_data(virq, msi_data); |
172 | irq_set_msi_desc(virq, entry); | |
34e36c15 | 173 | |
80818813 | 174 | fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data); |
34e36c15 JJ |
175 | write_msi_msg(virq, &msg); |
176 | } | |
177 | return 0; | |
178 | ||
179 | out_free: | |
694a7a36 | 180 | /* free by the caller of this function */ |
34e36c15 JJ |
181 | return rc; |
182 | } | |
183 | ||
692d1037 | 184 | static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) |
34e36c15 | 185 | { |
ddaedd1c TG |
186 | struct irq_chip *chip = irq_desc_get_chip(desc); |
187 | struct irq_data *idata = irq_desc_get_irq_data(desc); | |
34e36c15 | 188 | unsigned int cascade_irq; |
02adac60 | 189 | struct fsl_msi *msi_data; |
34e36c15 JJ |
190 | int msir_index = -1; |
191 | u32 msir_value = 0; | |
192 | u32 intr_index; | |
193 | u32 have_shift = 0; | |
02adac60 LY |
194 | struct fsl_msi_cascade_data *cascade_data; |
195 | ||
ec775d0e | 196 | cascade_data = (struct fsl_msi_cascade_data *)irq_get_handler_data(irq); |
02adac60 | 197 | msi_data = cascade_data->msi_data; |
34e36c15 | 198 | |
239007b8 | 199 | raw_spin_lock(&desc->lock); |
34e36c15 | 200 | if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { |
37e16615 | 201 | if (chip->irq_mask_ack) |
ddaedd1c | 202 | chip->irq_mask_ack(idata); |
34e36c15 | 203 | else { |
ddaedd1c TG |
204 | chip->irq_mask(idata); |
205 | chip->irq_ack(idata); | |
34e36c15 JJ |
206 | } |
207 | } | |
208 | ||
ddaedd1c | 209 | if (unlikely(irqd_irq_inprogress(idata))) |
34e36c15 JJ |
210 | goto unlock; |
211 | ||
02adac60 | 212 | msir_index = cascade_data->index; |
34e36c15 JJ |
213 | |
214 | if (msir_index >= NR_MSI_REG) | |
215 | cascade_irq = NO_IRQ; | |
216 | ||
ddaedd1c | 217 | irqd_set_chained_irq_inprogress(idata); |
80818813 | 218 | switch (msi_data->feature & FSL_PIC_IP_MASK) { |
34e36c15 JJ |
219 | case FSL_PIC_IP_MPIC: |
220 | msir_value = fsl_msi_read(msi_data->msi_regs, | |
221 | msir_index * 0x10); | |
222 | break; | |
223 | case FSL_PIC_IP_IPIC: | |
224 | msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4); | |
225 | break; | |
226 | } | |
227 | ||
228 | while (msir_value) { | |
229 | intr_index = ffs(msir_value) - 1; | |
230 | ||
231 | cascade_irq = irq_linear_revmap(msi_data->irqhost, | |
692d1037 AV |
232 | msir_index * IRQS_PER_MSI_REG + |
233 | intr_index + have_shift); | |
34e36c15 JJ |
234 | if (cascade_irq != NO_IRQ) |
235 | generic_handle_irq(cascade_irq); | |
692d1037 AV |
236 | have_shift += intr_index + 1; |
237 | msir_value = msir_value >> (intr_index + 1); | |
34e36c15 | 238 | } |
ddaedd1c | 239 | irqd_clr_chained_irq_inprogress(idata); |
34e36c15 JJ |
240 | |
241 | switch (msi_data->feature & FSL_PIC_IP_MASK) { | |
242 | case FSL_PIC_IP_MPIC: | |
ddaedd1c | 243 | chip->irq_eoi(idata); |
34e36c15 JJ |
244 | break; |
245 | case FSL_PIC_IP_IPIC: | |
ddaedd1c TG |
246 | if (!irqd_irq_disabled(idata) && chip->irq_unmask) |
247 | chip->irq_unmask(idata); | |
34e36c15 JJ |
248 | break; |
249 | } | |
250 | unlock: | |
239007b8 | 251 | raw_spin_unlock(&desc->lock); |
34e36c15 JJ |
252 | } |
253 | ||
a454dc50 | 254 | static int fsl_of_msi_remove(struct platform_device *ofdev) |
48059993 LY |
255 | { |
256 | struct fsl_msi *msi = ofdev->dev.platform_data; | |
257 | int virq, i; | |
258 | struct fsl_msi_cascade_data *cascade_data; | |
259 | ||
260 | if (msi->list.prev != NULL) | |
261 | list_del(&msi->list); | |
262 | for (i = 0; i < NR_MSI_REG; i++) { | |
263 | virq = msi->msi_virqs[i]; | |
264 | if (virq != NO_IRQ) { | |
ec775d0e | 265 | cascade_data = irq_get_handler_data(virq); |
48059993 LY |
266 | kfree(cascade_data); |
267 | irq_dispose_mapping(virq); | |
268 | } | |
269 | } | |
270 | if (msi->bitmap.bitmap) | |
271 | msi_bitmap_free(&msi->bitmap); | |
272 | iounmap(msi->msi_regs); | |
273 | kfree(msi); | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
6820fead SW |
278 | static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi, |
279 | struct platform_device *dev, | |
280 | int offset, int irq_index) | |
281 | { | |
282 | struct fsl_msi_cascade_data *cascade_data = NULL; | |
283 | int virt_msir; | |
284 | ||
285 | virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index); | |
286 | if (virt_msir == NO_IRQ) { | |
287 | dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n", | |
288 | __func__, irq_index); | |
289 | return 0; | |
290 | } | |
291 | ||
292 | cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL); | |
293 | if (!cascade_data) { | |
294 | dev_err(&dev->dev, "No memory for MSI cascade data\n"); | |
295 | return -ENOMEM; | |
296 | } | |
297 | ||
298 | msi->msi_virqs[irq_index] = virt_msir; | |
299 | cascade_data->index = offset + irq_index; | |
300 | cascade_data->msi_data = msi; | |
ec775d0e TG |
301 | irq_set_handler_data(virt_msir, cascade_data); |
302 | irq_set_chained_handler(virt_msir, fsl_msi_cascade); | |
6820fead SW |
303 | |
304 | return 0; | |
305 | } | |
306 | ||
00006124 | 307 | static int __devinit fsl_of_msi_probe(struct platform_device *dev) |
34e36c15 JJ |
308 | { |
309 | struct fsl_msi *msi; | |
310 | struct resource res; | |
6820fead | 311 | int err, i, j, irq_index, count; |
34e36c15 | 312 | int rc; |
34e36c15 | 313 | const u32 *p; |
00006124 | 314 | struct fsl_msi_feature *features; |
061ca4ad LY |
315 | int len; |
316 | u32 offset; | |
6820fead | 317 | static const u32 all_avail[] = { 0, NR_MSI_IRQS }; |
34e36c15 | 318 | |
00006124 GL |
319 | if (!dev->dev.of_match) |
320 | return -EINVAL; | |
321 | features = dev->dev.of_match->data; | |
322 | ||
34e36c15 JJ |
323 | printk(KERN_DEBUG "Setting up Freescale MSI support\n"); |
324 | ||
325 | msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL); | |
326 | if (!msi) { | |
327 | dev_err(&dev->dev, "No memory for MSI structure\n"); | |
48059993 | 328 | return -ENOMEM; |
34e36c15 | 329 | } |
48059993 | 330 | dev->dev.platform_data = msi; |
34e36c15 | 331 | |
61c7a080 | 332 | msi->irqhost = irq_alloc_host(dev->dev.of_node, IRQ_HOST_MAP_LINEAR, |
611cd90c | 333 | NR_MSI_IRQS, &fsl_msi_host_ops, 0); |
34e36c15 | 334 | |
34e36c15 JJ |
335 | if (msi->irqhost == NULL) { |
336 | dev_err(&dev->dev, "No memory for MSI irqhost\n"); | |
34e36c15 JJ |
337 | err = -ENOMEM; |
338 | goto error_out; | |
339 | } | |
340 | ||
341 | /* Get the MSI reg base */ | |
61c7a080 | 342 | err = of_address_to_resource(dev->dev.of_node, 0, &res); |
34e36c15 JJ |
343 | if (err) { |
344 | dev_err(&dev->dev, "%s resource error!\n", | |
61c7a080 | 345 | dev->dev.of_node->full_name); |
34e36c15 JJ |
346 | goto error_out; |
347 | } | |
348 | ||
349 | msi->msi_regs = ioremap(res.start, res.end - res.start + 1); | |
350 | if (!msi->msi_regs) { | |
351 | dev_err(&dev->dev, "ioremap problem failed\n"); | |
352 | goto error_out; | |
353 | } | |
354 | ||
692d1037 | 355 | msi->feature = features->fsl_pic_ip; |
34e36c15 JJ |
356 | |
357 | msi->irqhost->host_data = msi; | |
358 | ||
359 | msi->msi_addr_hi = 0x0; | |
3da34aae | 360 | msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff); |
34e36c15 JJ |
361 | |
362 | rc = fsl_msi_init_allocator(msi); | |
363 | if (rc) { | |
364 | dev_err(&dev->dev, "Error allocating MSI bitmap\n"); | |
365 | goto error_out; | |
366 | } | |
367 | ||
6820fead SW |
368 | p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len); |
369 | if (p && len % (2 * sizeof(u32)) != 0) { | |
370 | dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n", | |
371 | __func__); | |
34e36c15 JJ |
372 | err = -EINVAL; |
373 | goto error_out; | |
374 | } | |
6820fead SW |
375 | |
376 | if (!p) | |
377 | p = all_avail; | |
378 | ||
379 | for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) { | |
380 | if (p[i * 2] % IRQS_PER_MSI_REG || | |
381 | p[i * 2 + 1] % IRQS_PER_MSI_REG) { | |
382 | printk(KERN_WARNING "%s: %s: msi available range of %u at %u is not IRQ-aligned\n", | |
383 | __func__, dev->dev.of_node->full_name, | |
384 | p[i * 2 + 1], p[i * 2]); | |
385 | err = -EINVAL; | |
386 | goto error_out; | |
387 | } | |
388 | ||
389 | offset = p[i * 2] / IRQS_PER_MSI_REG; | |
390 | count = p[i * 2 + 1] / IRQS_PER_MSI_REG; | |
391 | ||
392 | for (j = 0; j < count; j++, irq_index++) { | |
393 | err = fsl_msi_setup_hwirq(msi, dev, offset, irq_index); | |
394 | if (err) | |
02adac60 | 395 | goto error_out; |
34e36c15 JJ |
396 | } |
397 | } | |
398 | ||
694a7a36 | 399 | list_add_tail(&msi->list, &msi_head); |
34e36c15 | 400 | |
80818813 LCB |
401 | /* The multiple setting ppc_md.setup_msi_irqs will not harm things */ |
402 | if (!ppc_md.setup_msi_irqs) { | |
403 | ppc_md.setup_msi_irqs = fsl_setup_msi_irqs; | |
404 | ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs; | |
405 | ppc_md.msi_check_device = fsl_msi_check_device; | |
406 | } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) { | |
407 | dev_err(&dev->dev, "Different MSI driver already installed!\n"); | |
408 | err = -ENODEV; | |
409 | goto error_out; | |
410 | } | |
34e36c15 JJ |
411 | return 0; |
412 | error_out: | |
48059993 | 413 | fsl_of_msi_remove(dev); |
34e36c15 JJ |
414 | return err; |
415 | } | |
416 | ||
417 | static const struct fsl_msi_feature mpic_msi_feature = { | |
418 | .fsl_pic_ip = FSL_PIC_IP_MPIC, | |
419 | .msiir_offset = 0x140, | |
420 | }; | |
421 | ||
422 | static const struct fsl_msi_feature ipic_msi_feature = { | |
423 | .fsl_pic_ip = FSL_PIC_IP_IPIC, | |
424 | .msiir_offset = 0x38, | |
425 | }; | |
426 | ||
427 | static const struct of_device_id fsl_of_msi_ids[] = { | |
428 | { | |
429 | .compatible = "fsl,mpic-msi", | |
430 | .data = (void *)&mpic_msi_feature, | |
431 | }, | |
432 | { | |
433 | .compatible = "fsl,ipic-msi", | |
434 | .data = (void *)&ipic_msi_feature, | |
435 | }, | |
436 | {} | |
437 | }; | |
438 | ||
00006124 | 439 | static struct platform_driver fsl_of_msi_driver = { |
4018294b GL |
440 | .driver = { |
441 | .name = "fsl-msi", | |
442 | .owner = THIS_MODULE, | |
443 | .of_match_table = fsl_of_msi_ids, | |
444 | }, | |
34e36c15 | 445 | .probe = fsl_of_msi_probe, |
48059993 | 446 | .remove = fsl_of_msi_remove, |
34e36c15 JJ |
447 | }; |
448 | ||
449 | static __init int fsl_of_msi_init(void) | |
450 | { | |
00006124 | 451 | return platform_driver_register(&fsl_of_msi_driver); |
34e36c15 JJ |
452 | } |
453 | ||
454 | subsys_initcall(fsl_of_msi_init); |