Merge tag 'samsung-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene...
[deliverable/linux.git] / arch / powerpc / sysdev / fsl_msi.c
CommitLineData
34e36c15 1/*
6820fead 2 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
34e36c15
JJ
3 *
4 * Author: Tony Li <tony.li@freescale.com>
5 * Jason Jin <Jason.jin@freescale.com>
6 *
7 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 */
15#include <linux/irq.h>
16#include <linux/bootmem.h>
34e36c15
JJ
17#include <linux/msi.h>
18#include <linux/pci.h>
5a0e3ad6 19#include <linux/slab.h>
34e36c15 20#include <linux/of_platform.h>
543c043c 21#include <linux/interrupt.h>
de99f53d 22#include <linux/seq_file.h>
34e36c15
JJ
23#include <sysdev/fsl_soc.h>
24#include <asm/prom.h>
25#include <asm/hw_irq.h>
26#include <asm/ppc-pci.h>
02adac60 27#include <asm/mpic.h>
446bc1ff
TT
28#include <asm/fsl_hcalls.h>
29
34e36c15 30#include "fsl_msi.h"
b8f44ec2 31#include "fsl_pci.h"
34e36c15 32
f31dd944
ML
33#define MSIIR_OFFSET_MASK 0xfffff
34#define MSIIR_IBS_SHIFT 0
35#define MSIIR_SRS_SHIFT 5
36#define MSIIR1_IBS_SHIFT 4
37#define MSIIR1_SRS_SHIFT 0
38#define MSI_SRS_MASK 0xf
39#define MSI_IBS_MASK 0x1f
40
41#define msi_hwirq(msi, msir_index, intr_index) \
42 ((msir_index) << (msi)->srs_shift | \
43 ((intr_index) << (msi)->ibs_shift))
44
6cce76dc 45static LIST_HEAD(msi_head);
694a7a36 46
34e36c15
JJ
47struct fsl_msi_feature {
48 u32 fsl_pic_ip;
2bcd1c0c 49 u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
34e36c15
JJ
50};
51
02adac60
LY
52struct fsl_msi_cascade_data {
53 struct fsl_msi *msi_data;
54 int index;
83495231 55 int virq;
02adac60 56};
34e36c15
JJ
57
58static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
59{
60 return in_be32(base + (reg >> 2));
61}
62
34e36c15
JJ
63/*
64 * We do not need this actually. The MSIR register has been read once
65 * in the cascade interrupt. So, this MSI interrupt has been acked
66*/
37e16615 67static void fsl_msi_end_irq(struct irq_data *d)
34e36c15
JJ
68{
69}
70
de99f53d
TL
71static void fsl_msi_print_chip(struct irq_data *irqd, struct seq_file *p)
72{
73 struct fsl_msi *msi_data = irqd->domain->host_data;
74 irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
75 int cascade_virq, srs;
76
77 srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK;
78 cascade_virq = msi_data->cascade_array[srs]->virq;
79
80 seq_printf(p, " fsl-msi-%d", cascade_virq);
81}
82
83
34e36c15 84static struct irq_chip fsl_msi_chip = {
1c9db525
TG
85 .irq_mask = mask_msi_irq,
86 .irq_unmask = unmask_msi_irq,
37e16615 87 .irq_ack = fsl_msi_end_irq,
de99f53d 88 .irq_print_chip = fsl_msi_print_chip,
34e36c15
JJ
89};
90
bae1d8f1 91static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
34e36c15
JJ
92 irq_hw_number_t hw)
93{
80818813 94 struct fsl_msi *msi_data = h->host_data;
34e36c15
JJ
95 struct irq_chip *chip = &fsl_msi_chip;
96
98488db9 97 irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
34e36c15 98
ec775d0e
TG
99 irq_set_chip_data(virq, msi_data);
100 irq_set_chip_and_handler(virq, chip, handle_edge_irq);
34e36c15
JJ
101
102 return 0;
103}
104
9f70b8eb 105static const struct irq_domain_ops fsl_msi_host_ops = {
34e36c15
JJ
106 .map = fsl_msi_host_map,
107};
108
34e36c15
JJ
109static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
110{
f31dd944 111 int rc, hwirq;
34e36c15 112
f31dd944 113 rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX,
7e7ab367
ME
114 msi_data->irqhost->of_node);
115 if (rc)
116 return rc;
34e36c15 117
f31dd944
ML
118 /*
119 * Reserve all the hwirqs
120 * The available hwirqs will be released in fsl_msi_setup_hwirq()
121 */
122 for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
123 msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
34e36c15 124
34e36c15 125 return 0;
34e36c15
JJ
126}
127
34e36c15
JJ
128static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
129{
130 struct msi_desc *entry;
80818813 131 struct fsl_msi *msi_data;
34e36c15
JJ
132
133 list_for_each_entry(entry, &pdev->msi_list, list) {
134 if (entry->irq == NO_IRQ)
135 continue;
d1921bcd 136 msi_data = irq_get_chip_data(entry->irq);
ec775d0e 137 irq_set_msi_desc(entry->irq, NULL);
7e7ab367
ME
138 msi_bitmap_free_hwirqs(&msi_data->bitmap,
139 virq_to_hw(entry->irq), 1);
34e36c15
JJ
140 irq_dispose_mapping(entry->irq);
141 }
142
143 return;
144}
145
146static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
80818813
LCB
147 struct msi_msg *msg,
148 struct fsl_msi *fsl_msi_data)
34e36c15 149{
80818813 150 struct fsl_msi *msi_data = fsl_msi_data;
3da34aae 151 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2bcd1c0c
TT
152 u64 address; /* Physical address of the MSIIR */
153 int len;
6cce76dc 154 const __be64 *reg;
2bcd1c0c
TT
155
156 /* If the msi-address-64 property exists, then use it */
157 reg = of_get_property(hose->dn, "msi-address-64", &len);
158 if (reg && (len == sizeof(u64)))
159 address = be64_to_cpup(reg);
160 else
161 address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
34e36c15 162
2bcd1c0c
TT
163 msg->address_lo = lower_32_bits(address);
164 msg->address_hi = upper_32_bits(address);
3da34aae 165
34e36c15
JJ
166 msg->data = hwirq;
167
f31dd944
ML
168 pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
169 (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
170 (hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
34e36c15
JJ
171}
172
173static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
174{
895d603f
TT
175 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
176 struct device_node *np;
177 phandle phandle = 0;
694a7a36 178 int rc, hwirq = -ENOMEM;
34e36c15
JJ
179 unsigned int virq;
180 struct msi_desc *entry;
181 struct msi_msg msg;
80818813 182 struct fsl_msi *msi_data;
34e36c15 183
6b2fd7ef
AG
184 if (type == PCI_CAP_ID_MSIX)
185 pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
186
895d603f
TT
187 /*
188 * If the PCI node has an fsl,msi property, then we need to use it
189 * to find the specific MSI.
190 */
191 np = of_parse_phandle(hose->dn, "fsl,msi", 0);
192 if (np) {
446bc1ff 193 if (of_device_is_compatible(np, "fsl,mpic-msi") ||
67e35c3a
TL
194 of_device_is_compatible(np, "fsl,vmpic-msi") ||
195 of_device_is_compatible(np, "fsl,vmpic-msi-v4.3"))
895d603f
TT
196 phandle = np->phandle;
197 else {
446bc1ff
TT
198 dev_err(&pdev->dev,
199 "node %s has an invalid fsl,msi phandle %u\n",
200 hose->dn->full_name, np->phandle);
895d603f
TT
201 return -EINVAL;
202 }
203 }
204
34e36c15 205 list_for_each_entry(entry, &pdev->msi_list, list) {
895d603f
TT
206 /*
207 * Loop over all the MSI devices until we find one that has an
208 * available interrupt.
209 */
694a7a36 210 list_for_each_entry(msi_data, &msi_head, list) {
895d603f
TT
211 /*
212 * If the PCI node has an fsl,msi property, then we
213 * restrict our search to the corresponding MSI node.
214 * The simplest way is to skip over MSI nodes with the
215 * wrong phandle. Under the Freescale hypervisor, this
216 * has the additional benefit of skipping over MSI
217 * nodes that are not mapped in the PAMU.
218 */
219 if (phandle && (phandle != msi_data->phandle))
220 continue;
221
694a7a36
LY
222 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
223 if (hwirq >= 0)
224 break;
225 }
80818813 226
34e36c15
JJ
227 if (hwirq < 0) {
228 rc = hwirq;
446bc1ff 229 dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
34e36c15
JJ
230 goto out_free;
231 }
232
233 virq = irq_create_mapping(msi_data->irqhost, hwirq);
234
235 if (virq == NO_IRQ) {
446bc1ff 236 dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
7e7ab367 237 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
34e36c15
JJ
238 rc = -ENOSPC;
239 goto out_free;
240 }
d1921bcd 241 /* chip_data is msi_data via host->hostdata in host->map() */
ec775d0e 242 irq_set_msi_desc(virq, entry);
34e36c15 243
80818813 244 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
34e36c15
JJ
245 write_msi_msg(virq, &msg);
246 }
247 return 0;
248
249out_free:
694a7a36 250 /* free by the caller of this function */
34e36c15
JJ
251 return rc;
252}
253
543c043c 254static irqreturn_t fsl_msi_cascade(int irq, void *data)
34e36c15
JJ
255{
256 unsigned int cascade_irq;
02adac60 257 struct fsl_msi *msi_data;
34e36c15
JJ
258 int msir_index = -1;
259 u32 msir_value = 0;
260 u32 intr_index;
261 u32 have_shift = 0;
543c043c
TL
262 struct fsl_msi_cascade_data *cascade_data = data;
263 irqreturn_t ret = IRQ_NONE;
02adac60 264
02adac60 265 msi_data = cascade_data->msi_data;
34e36c15 266
02adac60 267 msir_index = cascade_data->index;
34e36c15 268
f31dd944 269 if (msir_index >= NR_MSI_REG_MAX)
34e36c15
JJ
270 cascade_irq = NO_IRQ;
271
80818813 272 switch (msi_data->feature & FSL_PIC_IP_MASK) {
34e36c15
JJ
273 case FSL_PIC_IP_MPIC:
274 msir_value = fsl_msi_read(msi_data->msi_regs,
275 msir_index * 0x10);
276 break;
277 case FSL_PIC_IP_IPIC:
278 msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
279 break;
305bcf26
SW
280#ifdef CONFIG_EPAPR_PARAVIRT
281 case FSL_PIC_IP_VMPIC: {
282 unsigned int ret;
446bc1ff
TT
283 ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
284 if (ret) {
285 pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
286 "irq %u (ret=%u)\n", irq, ret);
287 msir_value = 0;
288 }
289 break;
34e36c15 290 }
305bcf26
SW
291#endif
292 }
34e36c15
JJ
293
294 while (msir_value) {
295 intr_index = ffs(msir_value) - 1;
296
297 cascade_irq = irq_linear_revmap(msi_data->irqhost,
f31dd944
ML
298 msi_hwirq(msi_data, msir_index,
299 intr_index + have_shift));
543c043c 300 if (cascade_irq != NO_IRQ) {
34e36c15 301 generic_handle_irq(cascade_irq);
543c043c
TL
302 ret = IRQ_HANDLED;
303 }
692d1037
AV
304 have_shift += intr_index + 1;
305 msir_value = msir_value >> (intr_index + 1);
34e36c15 306 }
34e36c15 307
543c043c 308 return ret;
34e36c15
JJ
309}
310
a454dc50 311static int fsl_of_msi_remove(struct platform_device *ofdev)
48059993 312{
6c4c82e2 313 struct fsl_msi *msi = platform_get_drvdata(ofdev);
48059993 314 int virq, i;
48059993
LY
315
316 if (msi->list.prev != NULL)
317 list_del(&msi->list);
f31dd944 318 for (i = 0; i < NR_MSI_REG_MAX; i++) {
83495231
TL
319 if (msi->cascade_array[i]) {
320 virq = msi->cascade_array[i]->virq;
321
322 BUG_ON(virq == NO_IRQ);
83495231 323
543c043c 324 free_irq(virq, msi->cascade_array[i]);
83495231 325 kfree(msi->cascade_array[i]);
48059993
LY
326 irq_dispose_mapping(virq);
327 }
328 }
329 if (msi->bitmap.bitmap)
330 msi_bitmap_free(&msi->bitmap);
446bc1ff
TT
331 if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
332 iounmap(msi->msi_regs);
48059993
LY
333 kfree(msi);
334
335 return 0;
336}
337
58631ad1
SAS
338static struct lock_class_key fsl_msi_irq_class;
339
cad5cef6
GKH
340static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
341 int offset, int irq_index)
6820fead
SW
342{
343 struct fsl_msi_cascade_data *cascade_data = NULL;
543c043c 344 int virt_msir, i, ret;
6820fead
SW
345
346 virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
347 if (virt_msir == NO_IRQ) {
348 dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
349 __func__, irq_index);
350 return 0;
351 }
352
353 cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
354 if (!cascade_data) {
355 dev_err(&dev->dev, "No memory for MSI cascade data\n");
356 return -ENOMEM;
357 }
58631ad1 358 irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
22285118 359 cascade_data->index = offset;
6820fead 360 cascade_data->msi_data = msi;
83495231
TL
361 cascade_data->virq = virt_msir;
362 msi->cascade_array[irq_index] = cascade_data;
543c043c
TL
363
364 ret = request_irq(virt_msir, fsl_msi_cascade, 0,
365 "fsl-msi-cascade", cascade_data);
366 if (ret) {
367 dev_err(&dev->dev, "failed to request_irq(%d), ret = %d\n",
368 virt_msir, ret);
369 return ret;
370 }
6820fead 371
f31dd944
ML
372 /* Release the hwirqs corresponding to this MSI register */
373 for (i = 0; i < IRQS_PER_MSI_REG; i++)
374 msi_bitmap_free_hwirqs(&msi->bitmap,
375 msi_hwirq(msi, offset, i), 1);
376
6820fead
SW
377 return 0;
378}
379
b1608d69 380static const struct of_device_id fsl_of_msi_ids[];
cad5cef6 381static int fsl_of_msi_probe(struct platform_device *dev)
34e36c15 382{
b1608d69 383 const struct of_device_id *match;
34e36c15 384 struct fsl_msi *msi;
f31dd944 385 struct resource res, msiir;
6820fead 386 int err, i, j, irq_index, count;
34e36c15 387 const u32 *p;
f318f1d7 388 const struct fsl_msi_feature *features;
061ca4ad
LY
389 int len;
390 u32 offset;
34e36c15 391
b1608d69
GL
392 match = of_match_device(fsl_of_msi_ids, &dev->dev);
393 if (!match)
00006124 394 return -EINVAL;
b1608d69 395 features = match->data;
00006124 396
34e36c15
JJ
397 printk(KERN_DEBUG "Setting up Freescale MSI support\n");
398
399 msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
400 if (!msi) {
401 dev_err(&dev->dev, "No memory for MSI structure\n");
48059993 402 return -ENOMEM;
34e36c15 403 }
6c4c82e2 404 platform_set_drvdata(dev, msi);
34e36c15 405
a8db8cf0 406 msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
f31dd944 407 NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi);
34e36c15 408
34e36c15
JJ
409 if (msi->irqhost == NULL) {
410 dev_err(&dev->dev, "No memory for MSI irqhost\n");
34e36c15
JJ
411 err = -ENOMEM;
412 goto error_out;
413 }
414
446bc1ff
TT
415 /*
416 * Under the Freescale hypervisor, the msi nodes don't have a 'reg'
417 * property. Instead, we use hypercalls to access the MSI.
418 */
419 if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
420 err = of_address_to_resource(dev->dev.of_node, 0, &res);
421 if (err) {
422 dev_err(&dev->dev, "invalid resource for node %s\n",
61c7a080 423 dev->dev.of_node->full_name);
446bc1ff
TT
424 goto error_out;
425 }
34e36c15 426
446bc1ff
TT
427 msi->msi_regs = ioremap(res.start, resource_size(&res));
428 if (!msi->msi_regs) {
b53804c7 429 err = -ENOMEM;
446bc1ff
TT
430 dev_err(&dev->dev, "could not map node %s\n",
431 dev->dev.of_node->full_name);
432 goto error_out;
433 }
434 msi->msiir_offset =
435 features->msiir_offset + (res.start & 0xfffff);
f31dd944
ML
436
437 /*
438 * First read the MSIIR/MSIIR1 offset from dts
439 * On failure use the hardcode MSIIR offset
440 */
441 if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
442 msi->msiir_offset = features->msiir_offset +
443 (res.start & MSIIR_OFFSET_MASK);
444 else
445 msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
34e36c15
JJ
446 }
447
692d1037 448 msi->feature = features->fsl_pic_ip;
34e36c15 449
895d603f
TT
450 /*
451 * Remember the phandle, so that we can match with any PCI nodes
452 * that have an "fsl,msi" property.
453 */
454 msi->phandle = dev->dev.of_node->phandle;
455
f8dc6eb7
WY
456 err = fsl_msi_init_allocator(msi);
457 if (err) {
34e36c15
JJ
458 dev_err(&dev->dev, "Error allocating MSI bitmap\n");
459 goto error_out;
460 }
461
6820fead 462 p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
6820fead 463
67e35c3a
TL
464 if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3") ||
465 of_device_is_compatible(dev->dev.of_node, "fsl,vmpic-msi-v4.3")) {
f31dd944
ML
466 msi->srs_shift = MSIIR1_SRS_SHIFT;
467 msi->ibs_shift = MSIIR1_IBS_SHIFT;
468 if (p)
469 dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n",
470 __func__);
471
472 for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1;
473 irq_index++) {
474 err = fsl_msi_setup_hwirq(msi, dev,
475 irq_index, irq_index);
476 if (err)
477 goto error_out;
478 }
479 } else {
480 static const u32 all_avail[] =
481 { 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };
6820fead 482
f31dd944
ML
483 msi->srs_shift = MSIIR_SRS_SHIFT;
484 msi->ibs_shift = MSIIR_IBS_SHIFT;
485
486 if (p && len % (2 * sizeof(u32)) != 0) {
487 dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
488 __func__);
6820fead
SW
489 err = -EINVAL;
490 goto error_out;
491 }
492
f31dd944
ML
493 if (!p) {
494 p = all_avail;
495 len = sizeof(all_avail);
496 }
6820fead 497
f31dd944
ML
498 for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
499 if (p[i * 2] % IRQS_PER_MSI_REG ||
500 p[i * 2 + 1] % IRQS_PER_MSI_REG) {
501 pr_warn("%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
502 __func__, dev->dev.of_node->full_name,
503 p[i * 2 + 1], p[i * 2]);
504 err = -EINVAL;
02adac60 505 goto error_out;
f31dd944
ML
506 }
507
508 offset = p[i * 2] / IRQS_PER_MSI_REG;
509 count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
510
511 for (j = 0; j < count; j++, irq_index++) {
512 err = fsl_msi_setup_hwirq(msi, dev, offset + j,
513 irq_index);
514 if (err)
515 goto error_out;
516 }
34e36c15
JJ
517 }
518 }
519
694a7a36 520 list_add_tail(&msi->list, &msi_head);
34e36c15 521
80818813
LCB
522 /* The multiple setting ppc_md.setup_msi_irqs will not harm things */
523 if (!ppc_md.setup_msi_irqs) {
524 ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
525 ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
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LCB
526 } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
527 dev_err(&dev->dev, "Different MSI driver already installed!\n");
528 err = -ENODEV;
529 goto error_out;
530 }
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JJ
531 return 0;
532error_out:
48059993 533 fsl_of_msi_remove(dev);
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JJ
534 return err;
535}
536
537static const struct fsl_msi_feature mpic_msi_feature = {
538 .fsl_pic_ip = FSL_PIC_IP_MPIC,
539 .msiir_offset = 0x140,
540};
541
542static const struct fsl_msi_feature ipic_msi_feature = {
543 .fsl_pic_ip = FSL_PIC_IP_IPIC,
544 .msiir_offset = 0x38,
545};
546
446bc1ff
TT
547static const struct fsl_msi_feature vmpic_msi_feature = {
548 .fsl_pic_ip = FSL_PIC_IP_VMPIC,
549 .msiir_offset = 0,
550};
551
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JJ
552static const struct of_device_id fsl_of_msi_ids[] = {
553 {
554 .compatible = "fsl,mpic-msi",
a99cc82b 555 .data = &mpic_msi_feature,
34e36c15 556 },
f31dd944
ML
557 {
558 .compatible = "fsl,mpic-msi-v4.3",
559 .data = &mpic_msi_feature,
560 },
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JJ
561 {
562 .compatible = "fsl,ipic-msi",
a99cc82b 563 .data = &ipic_msi_feature,
34e36c15 564 },
305bcf26 565#ifdef CONFIG_EPAPR_PARAVIRT
446bc1ff
TT
566 {
567 .compatible = "fsl,vmpic-msi",
a99cc82b 568 .data = &vmpic_msi_feature,
446bc1ff 569 },
67e35c3a
TL
570 {
571 .compatible = "fsl,vmpic-msi-v4.3",
572 .data = &vmpic_msi_feature,
573 },
305bcf26 574#endif
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575 {}
576};
577
00006124 578static struct platform_driver fsl_of_msi_driver = {
4018294b
GL
579 .driver = {
580 .name = "fsl-msi",
581 .owner = THIS_MODULE,
582 .of_match_table = fsl_of_msi_ids,
583 },
34e36c15 584 .probe = fsl_of_msi_probe,
48059993 585 .remove = fsl_of_msi_remove,
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JJ
586};
587
588static __init int fsl_of_msi_init(void)
589{
00006124 590 return platform_driver_register(&fsl_of_msi_driver);
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JJ
591}
592
593subsys_initcall(fsl_of_msi_init);
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