Commit | Line | Data |
---|---|---|
2b0c28d7 | 1 | /* |
d02443a6 | 2 | * Freescale MPC85xx/MPC86xx RapidIO support |
2b0c28d7 | 3 | * |
ad1e9380 ZW |
4 | * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc. |
5 | * Zhang Wei <wei.zhang@freescale.com> | |
6 | * | |
2b0c28d7 MP |
7 | * Copyright 2005 MontaVista Software, Inc. |
8 | * Matt Porter <mporter@kernel.crashing.org> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | */ | |
15 | ||
2b0c28d7 MP |
16 | #include <linux/init.h> |
17 | #include <linux/module.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/dma-mapping.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/rio.h> | |
22 | #include <linux/rio_drv.h> | |
cc2bb696 | 23 | #include <linux/of_platform.h> |
61b26917 | 24 | #include <linux/delay.h> |
2b0c28d7 MP |
25 | |
26 | #include <asm/io.h> | |
27 | ||
ad1e9380 ZW |
28 | /* RapidIO definition irq, which read from OF-tree */ |
29 | #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq) | |
30 | #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq) | |
31 | #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq) | |
32 | ||
2b0c28d7 | 33 | #define RIO_ATMU_REGS_OFFSET 0x10c00 |
61b26917 ZW |
34 | #define RIO_P_MSG_REGS_OFFSET 0x11000 |
35 | #define RIO_S_MSG_REGS_OFFSET 0x13000 | |
36 | #define RIO_ESCSR 0x158 | |
37 | #define RIO_CCSR 0x15c | |
38 | #define RIO_ISR_AACR 0x10120 | |
39 | #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */ | |
2b0c28d7 MP |
40 | #define RIO_MAINT_WIN_SIZE 0x400000 |
41 | #define RIO_DBELL_WIN_SIZE 0x1000 | |
42 | ||
43 | #define RIO_MSG_OMR_MUI 0x00000002 | |
44 | #define RIO_MSG_OSR_TE 0x00000080 | |
45 | #define RIO_MSG_OSR_QOI 0x00000020 | |
46 | #define RIO_MSG_OSR_QFI 0x00000010 | |
47 | #define RIO_MSG_OSR_MUB 0x00000004 | |
48 | #define RIO_MSG_OSR_EOMI 0x00000002 | |
49 | #define RIO_MSG_OSR_QEI 0x00000001 | |
50 | ||
51 | #define RIO_MSG_IMR_MI 0x00000002 | |
52 | #define RIO_MSG_ISR_TE 0x00000080 | |
53 | #define RIO_MSG_ISR_QFI 0x00000010 | |
54 | #define RIO_MSG_ISR_DIQI 0x00000001 | |
55 | ||
56 | #define RIO_MSG_DESC_SIZE 32 | |
57 | #define RIO_MSG_BUFFER_SIZE 4096 | |
58 | #define RIO_MIN_TX_RING_SIZE 2 | |
59 | #define RIO_MAX_TX_RING_SIZE 2048 | |
60 | #define RIO_MIN_RX_RING_SIZE 2 | |
61 | #define RIO_MAX_RX_RING_SIZE 2048 | |
62 | ||
63 | #define DOORBELL_DMR_DI 0x00000002 | |
64 | #define DOORBELL_DSR_TE 0x00000080 | |
65 | #define DOORBELL_DSR_QFI 0x00000010 | |
66 | #define DOORBELL_DSR_DIQI 0x00000001 | |
67 | #define DOORBELL_TID_OFFSET 0x03 | |
68 | #define DOORBELL_SID_OFFSET 0x05 | |
69 | #define DOORBELL_INFO_OFFSET 0x06 | |
70 | ||
71 | #define DOORBELL_MESSAGE_SIZE 0x08 | |
72 | #define DBELL_SID(x) (*(u8 *)(x + DOORBELL_SID_OFFSET)) | |
73 | #define DBELL_TID(x) (*(u8 *)(x + DOORBELL_TID_OFFSET)) | |
74 | #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET)) | |
75 | ||
2b0c28d7 MP |
76 | struct rio_atmu_regs { |
77 | u32 rowtar; | |
61b26917 | 78 | u32 rowtear; |
2b0c28d7 MP |
79 | u32 rowbar; |
80 | u32 pad2; | |
81 | u32 rowar; | |
82 | u32 pad3[3]; | |
83 | }; | |
84 | ||
85 | struct rio_msg_regs { | |
86 | u32 omr; | |
87 | u32 osr; | |
88 | u32 pad1; | |
89 | u32 odqdpar; | |
90 | u32 pad2; | |
91 | u32 osar; | |
92 | u32 odpr; | |
93 | u32 odatr; | |
94 | u32 odcr; | |
95 | u32 pad3; | |
96 | u32 odqepar; | |
97 | u32 pad4[13]; | |
98 | u32 imr; | |
99 | u32 isr; | |
100 | u32 pad5; | |
101 | u32 ifqdpar; | |
102 | u32 pad6; | |
103 | u32 ifqepar; | |
61b26917 ZW |
104 | u32 pad7[226]; |
105 | u32 odmr; | |
106 | u32 odsr; | |
107 | u32 res0[4]; | |
108 | u32 oddpr; | |
109 | u32 oddatr; | |
110 | u32 res1[3]; | |
111 | u32 odretcr; | |
112 | u32 res2[12]; | |
2b0c28d7 MP |
113 | u32 dmr; |
114 | u32 dsr; | |
115 | u32 pad8; | |
116 | u32 dqdpar; | |
117 | u32 pad9; | |
118 | u32 dqepar; | |
119 | u32 pad10[26]; | |
120 | u32 pwmr; | |
121 | u32 pwsr; | |
122 | u32 pad11; | |
123 | u32 pwqbar; | |
124 | }; | |
125 | ||
126 | struct rio_tx_desc { | |
127 | u32 res1; | |
128 | u32 saddr; | |
129 | u32 dport; | |
130 | u32 dattr; | |
131 | u32 res2; | |
132 | u32 res3; | |
133 | u32 dwcnt; | |
134 | u32 res4; | |
135 | }; | |
136 | ||
ad1e9380 | 137 | struct rio_dbell_ring { |
2b0c28d7 MP |
138 | void *virt; |
139 | dma_addr_t phys; | |
ad1e9380 | 140 | }; |
2b0c28d7 | 141 | |
ad1e9380 | 142 | struct rio_msg_tx_ring { |
2b0c28d7 MP |
143 | void *virt; |
144 | dma_addr_t phys; | |
145 | void *virt_buffer[RIO_MAX_TX_RING_SIZE]; | |
146 | dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE]; | |
147 | int tx_slot; | |
148 | int size; | |
6978bbc0 | 149 | void *dev_id; |
ad1e9380 | 150 | }; |
2b0c28d7 | 151 | |
ad1e9380 | 152 | struct rio_msg_rx_ring { |
2b0c28d7 MP |
153 | void *virt; |
154 | dma_addr_t phys; | |
155 | void *virt_buffer[RIO_MAX_RX_RING_SIZE]; | |
156 | int rx_slot; | |
157 | int size; | |
6978bbc0 | 158 | void *dev_id; |
ad1e9380 ZW |
159 | }; |
160 | ||
161 | struct rio_priv { | |
162 | void __iomem *regs_win; | |
163 | struct rio_atmu_regs __iomem *atmu_regs; | |
164 | struct rio_atmu_regs __iomem *maint_atmu_regs; | |
165 | struct rio_atmu_regs __iomem *dbell_atmu_regs; | |
166 | void __iomem *dbell_win; | |
167 | void __iomem *maint_win; | |
168 | struct rio_msg_regs __iomem *msg_regs; | |
169 | struct rio_dbell_ring dbell_ring; | |
170 | struct rio_msg_tx_ring msg_tx_ring; | |
171 | struct rio_msg_rx_ring msg_rx_ring; | |
172 | int bellirq; | |
173 | int txirq; | |
174 | int rxirq; | |
175 | }; | |
2b0c28d7 MP |
176 | |
177 | /** | |
d02443a6 | 178 | * fsl_rio_doorbell_send - Send a MPC85xx doorbell message |
2b0c28d7 MP |
179 | * @index: ID of RapidIO interface |
180 | * @destid: Destination ID of target device | |
181 | * @data: 16-bit info field of RapidIO doorbell message | |
182 | * | |
183 | * Sends a MPC85xx doorbell message. Returns %0 on success or | |
184 | * %-EINVAL on failure. | |
185 | */ | |
ad1e9380 ZW |
186 | static int fsl_rio_doorbell_send(struct rio_mport *mport, |
187 | int index, u16 destid, u16 data) | |
2b0c28d7 | 188 | { |
ad1e9380 | 189 | struct rio_priv *priv = mport->priv; |
d02443a6 | 190 | pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n", |
2b0c28d7 | 191 | index, destid, data); |
61b26917 ZW |
192 | switch (mport->phy_type) { |
193 | case RIO_PHY_PARALLEL: | |
194 | out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22); | |
195 | out_be16(priv->dbell_win, data); | |
196 | break; | |
197 | case RIO_PHY_SERIAL: | |
198 | /* In the serial version silicons, such as MPC8548, MPC8641, | |
199 | * below operations is must be. | |
200 | */ | |
201 | out_be32(&priv->msg_regs->odmr, 0x00000000); | |
202 | out_be32(&priv->msg_regs->odretcr, 0x00000004); | |
203 | out_be32(&priv->msg_regs->oddpr, destid << 16); | |
204 | out_be32(&priv->msg_regs->oddatr, data); | |
205 | out_be32(&priv->msg_regs->odmr, 0x00000001); | |
206 | break; | |
207 | } | |
2b0c28d7 MP |
208 | |
209 | return 0; | |
210 | } | |
211 | ||
212 | /** | |
d02443a6 | 213 | * fsl_local_config_read - Generate a MPC85xx local config space read |
2b0c28d7 MP |
214 | * @index: ID of RapdiIO interface |
215 | * @offset: Offset into configuration space | |
216 | * @len: Length (in bytes) of the maintenance transaction | |
217 | * @data: Value to be read into | |
218 | * | |
219 | * Generates a MPC85xx local configuration space read. Returns %0 on | |
220 | * success or %-EINVAL on failure. | |
221 | */ | |
ad1e9380 ZW |
222 | static int fsl_local_config_read(struct rio_mport *mport, |
223 | int index, u32 offset, int len, u32 *data) | |
2b0c28d7 | 224 | { |
ad1e9380 | 225 | struct rio_priv *priv = mport->priv; |
d02443a6 | 226 | pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index, |
2b0c28d7 | 227 | offset); |
ad1e9380 | 228 | *data = in_be32(priv->regs_win + offset); |
2b0c28d7 MP |
229 | |
230 | return 0; | |
231 | } | |
232 | ||
233 | /** | |
d02443a6 | 234 | * fsl_local_config_write - Generate a MPC85xx local config space write |
2b0c28d7 MP |
235 | * @index: ID of RapdiIO interface |
236 | * @offset: Offset into configuration space | |
237 | * @len: Length (in bytes) of the maintenance transaction | |
238 | * @data: Value to be written | |
239 | * | |
240 | * Generates a MPC85xx local configuration space write. Returns %0 on | |
241 | * success or %-EINVAL on failure. | |
242 | */ | |
ad1e9380 ZW |
243 | static int fsl_local_config_write(struct rio_mport *mport, |
244 | int index, u32 offset, int len, u32 data) | |
2b0c28d7 | 245 | { |
ad1e9380 | 246 | struct rio_priv *priv = mport->priv; |
2b0c28d7 | 247 | pr_debug |
d02443a6 | 248 | ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n", |
2b0c28d7 | 249 | index, offset, data); |
ad1e9380 | 250 | out_be32(priv->regs_win + offset, data); |
2b0c28d7 MP |
251 | |
252 | return 0; | |
253 | } | |
254 | ||
255 | /** | |
d02443a6 | 256 | * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction |
2b0c28d7 MP |
257 | * @index: ID of RapdiIO interface |
258 | * @destid: Destination ID of transaction | |
259 | * @hopcount: Number of hops to target device | |
260 | * @offset: Offset into configuration space | |
261 | * @len: Length (in bytes) of the maintenance transaction | |
262 | * @val: Location to be read into | |
263 | * | |
264 | * Generates a MPC85xx read maintenance transaction. Returns %0 on | |
265 | * success or %-EINVAL on failure. | |
266 | */ | |
267 | static int | |
ad1e9380 ZW |
268 | fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid, |
269 | u8 hopcount, u32 offset, int len, u32 *val) | |
2b0c28d7 | 270 | { |
ad1e9380 | 271 | struct rio_priv *priv = mport->priv; |
2b0c28d7 MP |
272 | u8 *data; |
273 | ||
274 | pr_debug | |
d02443a6 | 275 | ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n", |
2b0c28d7 | 276 | index, destid, hopcount, offset, len); |
ad1e9380 | 277 | out_be32(&priv->maint_atmu_regs->rowtar, |
2b0c28d7 MP |
278 | (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9)); |
279 | ||
ad1e9380 | 280 | data = (u8 *) priv->maint_win + offset; |
2b0c28d7 MP |
281 | switch (len) { |
282 | case 1: | |
283 | *val = in_8((u8 *) data); | |
284 | break; | |
285 | case 2: | |
286 | *val = in_be16((u16 *) data); | |
287 | break; | |
288 | default: | |
289 | *val = in_be32((u32 *) data); | |
290 | break; | |
291 | } | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
296 | /** | |
d02443a6 | 297 | * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction |
2b0c28d7 MP |
298 | * @index: ID of RapdiIO interface |
299 | * @destid: Destination ID of transaction | |
300 | * @hopcount: Number of hops to target device | |
301 | * @offset: Offset into configuration space | |
302 | * @len: Length (in bytes) of the maintenance transaction | |
303 | * @val: Value to be written | |
304 | * | |
305 | * Generates an MPC85xx write maintenance transaction. Returns %0 on | |
306 | * success or %-EINVAL on failure. | |
307 | */ | |
308 | static int | |
ad1e9380 ZW |
309 | fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid, |
310 | u8 hopcount, u32 offset, int len, u32 val) | |
2b0c28d7 | 311 | { |
ad1e9380 | 312 | struct rio_priv *priv = mport->priv; |
2b0c28d7 MP |
313 | u8 *data; |
314 | pr_debug | |
d02443a6 | 315 | ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", |
2b0c28d7 | 316 | index, destid, hopcount, offset, len, val); |
ad1e9380 | 317 | out_be32(&priv->maint_atmu_regs->rowtar, |
2b0c28d7 MP |
318 | (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9)); |
319 | ||
ad1e9380 | 320 | data = (u8 *) priv->maint_win + offset; |
2b0c28d7 MP |
321 | switch (len) { |
322 | case 1: | |
323 | out_8((u8 *) data, val); | |
324 | break; | |
325 | case 2: | |
326 | out_be16((u16 *) data, val); | |
327 | break; | |
328 | default: | |
329 | out_be32((u32 *) data, val); | |
330 | break; | |
331 | } | |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
336 | /** | |
337 | * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue | |
338 | * @mport: Master port with outbound message queue | |
339 | * @rdev: Target of outbound message | |
340 | * @mbox: Outbound mailbox | |
341 | * @buffer: Message to add to outbound queue | |
342 | * @len: Length of message | |
343 | * | |
344 | * Adds the @buffer message to the MPC85xx outbound message queue. Returns | |
345 | * %0 on success or %-EINVAL on failure. | |
346 | */ | |
347 | int | |
348 | rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, | |
349 | void *buffer, size_t len) | |
350 | { | |
ad1e9380 | 351 | struct rio_priv *priv = mport->priv; |
2b0c28d7 | 352 | u32 omr; |
ad1e9380 ZW |
353 | struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt |
354 | + priv->msg_tx_ring.tx_slot; | |
2b0c28d7 MP |
355 | int ret = 0; |
356 | ||
357 | pr_debug | |
358 | ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n", | |
359 | rdev->destid, mbox, (int)buffer, len); | |
360 | ||
361 | if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { | |
362 | ret = -EINVAL; | |
363 | goto out; | |
364 | } | |
365 | ||
366 | /* Copy and clear rest of buffer */ | |
ad1e9380 ZW |
367 | memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer, |
368 | len); | |
2b0c28d7 | 369 | if (len < (RIO_MAX_MSG_SIZE - 4)) |
ad1e9380 ZW |
370 | memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot] |
371 | + len, 0, RIO_MAX_MSG_SIZE - len); | |
2b0c28d7 | 372 | |
61b26917 ZW |
373 | switch (mport->phy_type) { |
374 | case RIO_PHY_PARALLEL: | |
375 | /* Set mbox field for message */ | |
376 | desc->dport = mbox & 0x3; | |
2b0c28d7 | 377 | |
61b26917 ZW |
378 | /* Enable EOMI interrupt, set priority, and set destid */ |
379 | desc->dattr = 0x28000000 | (rdev->destid << 2); | |
380 | break; | |
381 | case RIO_PHY_SERIAL: | |
382 | /* Set mbox field for message, and set destid */ | |
383 | desc->dport = (rdev->destid << 16) | (mbox & 0x3); | |
384 | ||
385 | /* Enable EOMI interrupt and priority */ | |
386 | desc->dattr = 0x28000000; | |
387 | break; | |
388 | } | |
2b0c28d7 MP |
389 | |
390 | /* Set transfer size aligned to next power of 2 (in double words) */ | |
391 | desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); | |
392 | ||
393 | /* Set snooping and source buffer address */ | |
ad1e9380 ZW |
394 | desc->saddr = 0x00000004 |
395 | | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot]; | |
2b0c28d7 MP |
396 | |
397 | /* Increment enqueue pointer */ | |
ad1e9380 ZW |
398 | omr = in_be32(&priv->msg_regs->omr); |
399 | out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI); | |
2b0c28d7 MP |
400 | |
401 | /* Go to next descriptor */ | |
ad1e9380 ZW |
402 | if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size) |
403 | priv->msg_tx_ring.tx_slot = 0; | |
2b0c28d7 MP |
404 | |
405 | out: | |
406 | return ret; | |
407 | } | |
408 | ||
409 | EXPORT_SYMBOL_GPL(rio_hw_add_outb_message); | |
410 | ||
411 | /** | |
d02443a6 | 412 | * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler |
2b0c28d7 MP |
413 | * @irq: Linux interrupt number |
414 | * @dev_instance: Pointer to interrupt-specific data | |
2b0c28d7 MP |
415 | * |
416 | * Handles outbound message interrupts. Executes a register outbound | |
a8de5ce9 | 417 | * mailbox event handler and acks the interrupt occurrence. |
2b0c28d7 MP |
418 | */ |
419 | static irqreturn_t | |
d02443a6 | 420 | fsl_rio_tx_handler(int irq, void *dev_instance) |
2b0c28d7 MP |
421 | { |
422 | int osr; | |
423 | struct rio_mport *port = (struct rio_mport *)dev_instance; | |
ad1e9380 | 424 | struct rio_priv *priv = port->priv; |
2b0c28d7 | 425 | |
ad1e9380 | 426 | osr = in_be32(&priv->msg_regs->osr); |
2b0c28d7 MP |
427 | |
428 | if (osr & RIO_MSG_OSR_TE) { | |
429 | pr_info("RIO: outbound message transmission error\n"); | |
ad1e9380 | 430 | out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE); |
2b0c28d7 MP |
431 | goto out; |
432 | } | |
433 | ||
434 | if (osr & RIO_MSG_OSR_QOI) { | |
435 | pr_info("RIO: outbound message queue overflow\n"); | |
ad1e9380 | 436 | out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI); |
2b0c28d7 MP |
437 | goto out; |
438 | } | |
439 | ||
440 | if (osr & RIO_MSG_OSR_EOMI) { | |
ad1e9380 ZW |
441 | u32 dqp = in_be32(&priv->msg_regs->odqdpar); |
442 | int slot = (dqp - priv->msg_tx_ring.phys) >> 5; | |
443 | port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1, | |
444 | slot); | |
2b0c28d7 MP |
445 | |
446 | /* Ack the end-of-message interrupt */ | |
ad1e9380 | 447 | out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI); |
2b0c28d7 MP |
448 | } |
449 | ||
450 | out: | |
451 | return IRQ_HANDLED; | |
452 | } | |
453 | ||
454 | /** | |
455 | * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox | |
456 | * @mport: Master port implementing the outbound message unit | |
6978bbc0 | 457 | * @dev_id: Device specific pointer to pass on event |
2b0c28d7 MP |
458 | * @mbox: Mailbox to open |
459 | * @entries: Number of entries in the outbound mailbox ring | |
460 | * | |
461 | * Initializes buffer ring, request the outbound message interrupt, | |
462 | * and enables the outbound message unit. Returns %0 on success and | |
463 | * %-EINVAL or %-ENOMEM on failure. | |
464 | */ | |
6978bbc0 | 465 | int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) |
2b0c28d7 MP |
466 | { |
467 | int i, j, rc = 0; | |
ad1e9380 | 468 | struct rio_priv *priv = mport->priv; |
2b0c28d7 MP |
469 | |
470 | if ((entries < RIO_MIN_TX_RING_SIZE) || | |
471 | (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) { | |
472 | rc = -EINVAL; | |
473 | goto out; | |
474 | } | |
475 | ||
476 | /* Initialize shadow copy ring */ | |
ad1e9380 ZW |
477 | priv->msg_tx_ring.dev_id = dev_id; |
478 | priv->msg_tx_ring.size = entries; | |
479 | ||
480 | for (i = 0; i < priv->msg_tx_ring.size; i++) { | |
481 | priv->msg_tx_ring.virt_buffer[i] = | |
482 | dma_alloc_coherent(NULL, RIO_MSG_BUFFER_SIZE, | |
483 | &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL); | |
484 | if (!priv->msg_tx_ring.virt_buffer[i]) { | |
2b0c28d7 | 485 | rc = -ENOMEM; |
ad1e9380 ZW |
486 | for (j = 0; j < priv->msg_tx_ring.size; j++) |
487 | if (priv->msg_tx_ring.virt_buffer[j]) | |
2b0c28d7 | 488 | dma_free_coherent(NULL, |
ad1e9380 ZW |
489 | RIO_MSG_BUFFER_SIZE, |
490 | priv->msg_tx_ring. | |
491 | virt_buffer[j], | |
492 | priv->msg_tx_ring. | |
493 | phys_buffer[j]); | |
2b0c28d7 MP |
494 | goto out; |
495 | } | |
496 | } | |
497 | ||
498 | /* Initialize outbound message descriptor ring */ | |
ad1e9380 ZW |
499 | priv->msg_tx_ring.virt = dma_alloc_coherent(NULL, |
500 | priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, | |
501 | &priv->msg_tx_ring.phys, GFP_KERNEL); | |
502 | if (!priv->msg_tx_ring.virt) { | |
2b0c28d7 MP |
503 | rc = -ENOMEM; |
504 | goto out_dma; | |
505 | } | |
ad1e9380 ZW |
506 | memset(priv->msg_tx_ring.virt, 0, |
507 | priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE); | |
508 | priv->msg_tx_ring.tx_slot = 0; | |
2b0c28d7 MP |
509 | |
510 | /* Point dequeue/enqueue pointers at first entry in ring */ | |
ad1e9380 ZW |
511 | out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys); |
512 | out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys); | |
2b0c28d7 MP |
513 | |
514 | /* Configure for snooping */ | |
ad1e9380 | 515 | out_be32(&priv->msg_regs->osar, 0x00000004); |
2b0c28d7 MP |
516 | |
517 | /* Clear interrupt status */ | |
ad1e9380 | 518 | out_be32(&priv->msg_regs->osr, 0x000000b3); |
2b0c28d7 MP |
519 | |
520 | /* Hook up outbound message handler */ | |
ad1e9380 ZW |
521 | rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0, |
522 | "msg_tx", (void *)mport); | |
523 | if (rc < 0) | |
2b0c28d7 MP |
524 | goto out_irq; |
525 | ||
526 | /* | |
527 | * Configure outbound message unit | |
528 | * Snooping | |
529 | * Interrupts (all enabled, except QEIE) | |
530 | * Chaining mode | |
531 | * Disable | |
532 | */ | |
ad1e9380 | 533 | out_be32(&priv->msg_regs->omr, 0x00100220); |
2b0c28d7 MP |
534 | |
535 | /* Set number of entries */ | |
ad1e9380 ZW |
536 | out_be32(&priv->msg_regs->omr, |
537 | in_be32(&priv->msg_regs->omr) | | |
2b0c28d7 MP |
538 | ((get_bitmask_order(entries) - 2) << 12)); |
539 | ||
540 | /* Now enable the unit */ | |
ad1e9380 | 541 | out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1); |
2b0c28d7 MP |
542 | |
543 | out: | |
544 | return rc; | |
545 | ||
546 | out_irq: | |
ad1e9380 ZW |
547 | dma_free_coherent(NULL, priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, |
548 | priv->msg_tx_ring.virt, priv->msg_tx_ring.phys); | |
2b0c28d7 MP |
549 | |
550 | out_dma: | |
ad1e9380 | 551 | for (i = 0; i < priv->msg_tx_ring.size; i++) |
2b0c28d7 | 552 | dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE, |
ad1e9380 ZW |
553 | priv->msg_tx_ring.virt_buffer[i], |
554 | priv->msg_tx_ring.phys_buffer[i]); | |
2b0c28d7 MP |
555 | |
556 | return rc; | |
557 | } | |
558 | ||
559 | /** | |
560 | * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox | |
561 | * @mport: Master port implementing the outbound message unit | |
562 | * @mbox: Mailbox to close | |
563 | * | |
564 | * Disables the outbound message unit, free all buffers, and | |
565 | * frees the outbound message interrupt. | |
566 | */ | |
567 | void rio_close_outb_mbox(struct rio_mport *mport, int mbox) | |
568 | { | |
ad1e9380 | 569 | struct rio_priv *priv = mport->priv; |
2b0c28d7 | 570 | /* Disable inbound message unit */ |
ad1e9380 | 571 | out_be32(&priv->msg_regs->omr, 0); |
2b0c28d7 MP |
572 | |
573 | /* Free ring */ | |
ad1e9380 ZW |
574 | dma_free_coherent(NULL, priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, |
575 | priv->msg_tx_ring.virt, priv->msg_tx_ring.phys); | |
2b0c28d7 MP |
576 | |
577 | /* Free interrupt */ | |
ad1e9380 | 578 | free_irq(IRQ_RIO_TX(mport), (void *)mport); |
2b0c28d7 MP |
579 | } |
580 | ||
581 | /** | |
d02443a6 | 582 | * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler |
2b0c28d7 MP |
583 | * @irq: Linux interrupt number |
584 | * @dev_instance: Pointer to interrupt-specific data | |
2b0c28d7 MP |
585 | * |
586 | * Handles inbound message interrupts. Executes a registered inbound | |
a8de5ce9 | 587 | * mailbox event handler and acks the interrupt occurrence. |
2b0c28d7 MP |
588 | */ |
589 | static irqreturn_t | |
d02443a6 | 590 | fsl_rio_rx_handler(int irq, void *dev_instance) |
2b0c28d7 MP |
591 | { |
592 | int isr; | |
593 | struct rio_mport *port = (struct rio_mport *)dev_instance; | |
ad1e9380 | 594 | struct rio_priv *priv = port->priv; |
2b0c28d7 | 595 | |
ad1e9380 | 596 | isr = in_be32(&priv->msg_regs->isr); |
2b0c28d7 MP |
597 | |
598 | if (isr & RIO_MSG_ISR_TE) { | |
599 | pr_info("RIO: inbound message reception error\n"); | |
ad1e9380 | 600 | out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE); |
2b0c28d7 MP |
601 | goto out; |
602 | } | |
603 | ||
604 | /* XXX Need to check/dispatch until queue empty */ | |
605 | if (isr & RIO_MSG_ISR_DIQI) { | |
606 | /* | |
607 | * We implement *only* mailbox 0, but can receive messages | |
608 | * for any mailbox/letter to that mailbox destination. So, | |
609 | * make the callback with an unknown/invalid mailbox number | |
610 | * argument. | |
611 | */ | |
ad1e9380 | 612 | port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1); |
2b0c28d7 MP |
613 | |
614 | /* Ack the queueing interrupt */ | |
ad1e9380 | 615 | out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI); |
2b0c28d7 MP |
616 | } |
617 | ||
618 | out: | |
619 | return IRQ_HANDLED; | |
620 | } | |
621 | ||
622 | /** | |
623 | * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox | |
624 | * @mport: Master port implementing the inbound message unit | |
6978bbc0 | 625 | * @dev_id: Device specific pointer to pass on event |
2b0c28d7 MP |
626 | * @mbox: Mailbox to open |
627 | * @entries: Number of entries in the inbound mailbox ring | |
628 | * | |
629 | * Initializes buffer ring, request the inbound message interrupt, | |
630 | * and enables the inbound message unit. Returns %0 on success | |
631 | * and %-EINVAL or %-ENOMEM on failure. | |
632 | */ | |
6978bbc0 | 633 | int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) |
2b0c28d7 MP |
634 | { |
635 | int i, rc = 0; | |
ad1e9380 | 636 | struct rio_priv *priv = mport->priv; |
2b0c28d7 MP |
637 | |
638 | if ((entries < RIO_MIN_RX_RING_SIZE) || | |
639 | (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) { | |
640 | rc = -EINVAL; | |
641 | goto out; | |
642 | } | |
643 | ||
644 | /* Initialize client buffer ring */ | |
ad1e9380 ZW |
645 | priv->msg_rx_ring.dev_id = dev_id; |
646 | priv->msg_rx_ring.size = entries; | |
647 | priv->msg_rx_ring.rx_slot = 0; | |
648 | for (i = 0; i < priv->msg_rx_ring.size; i++) | |
649 | priv->msg_rx_ring.virt_buffer[i] = NULL; | |
2b0c28d7 MP |
650 | |
651 | /* Initialize inbound message ring */ | |
ad1e9380 ZW |
652 | priv->msg_rx_ring.virt = dma_alloc_coherent(NULL, |
653 | priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE, | |
654 | &priv->msg_rx_ring.phys, GFP_KERNEL); | |
655 | if (!priv->msg_rx_ring.virt) { | |
2b0c28d7 MP |
656 | rc = -ENOMEM; |
657 | goto out; | |
658 | } | |
659 | ||
660 | /* Point dequeue/enqueue pointers at first entry in ring */ | |
ad1e9380 ZW |
661 | out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys); |
662 | out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys); | |
2b0c28d7 MP |
663 | |
664 | /* Clear interrupt status */ | |
ad1e9380 | 665 | out_be32(&priv->msg_regs->isr, 0x00000091); |
2b0c28d7 MP |
666 | |
667 | /* Hook up inbound message handler */ | |
ad1e9380 ZW |
668 | rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0, |
669 | "msg_rx", (void *)mport); | |
670 | if (rc < 0) { | |
2b0c28d7 | 671 | dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE, |
ad1e9380 ZW |
672 | priv->msg_tx_ring.virt_buffer[i], |
673 | priv->msg_tx_ring.phys_buffer[i]); | |
2b0c28d7 MP |
674 | goto out; |
675 | } | |
676 | ||
677 | /* | |
678 | * Configure inbound message unit: | |
679 | * Snooping | |
680 | * 4KB max message size | |
681 | * Unmask all interrupt sources | |
682 | * Disable | |
683 | */ | |
ad1e9380 | 684 | out_be32(&priv->msg_regs->imr, 0x001b0060); |
2b0c28d7 MP |
685 | |
686 | /* Set number of queue entries */ | |
ad1e9380 | 687 | setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); |
2b0c28d7 MP |
688 | |
689 | /* Now enable the unit */ | |
ad1e9380 | 690 | setbits32(&priv->msg_regs->imr, 0x1); |
2b0c28d7 MP |
691 | |
692 | out: | |
693 | return rc; | |
694 | } | |
695 | ||
696 | /** | |
697 | * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox | |
698 | * @mport: Master port implementing the inbound message unit | |
699 | * @mbox: Mailbox to close | |
700 | * | |
701 | * Disables the inbound message unit, free all buffers, and | |
702 | * frees the inbound message interrupt. | |
703 | */ | |
704 | void rio_close_inb_mbox(struct rio_mport *mport, int mbox) | |
705 | { | |
ad1e9380 | 706 | struct rio_priv *priv = mport->priv; |
2b0c28d7 | 707 | /* Disable inbound message unit */ |
ad1e9380 | 708 | out_be32(&priv->msg_regs->imr, 0); |
2b0c28d7 MP |
709 | |
710 | /* Free ring */ | |
ad1e9380 ZW |
711 | dma_free_coherent(NULL, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE, |
712 | priv->msg_rx_ring.virt, priv->msg_rx_ring.phys); | |
2b0c28d7 MP |
713 | |
714 | /* Free interrupt */ | |
ad1e9380 | 715 | free_irq(IRQ_RIO_RX(mport), (void *)mport); |
2b0c28d7 MP |
716 | } |
717 | ||
718 | /** | |
719 | * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue | |
720 | * @mport: Master port implementing the inbound message unit | |
721 | * @mbox: Inbound mailbox number | |
722 | * @buf: Buffer to add to inbound queue | |
723 | * | |
724 | * Adds the @buf buffer to the MPC85xx inbound message queue. Returns | |
725 | * %0 on success or %-EINVAL on failure. | |
726 | */ | |
727 | int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) | |
728 | { | |
729 | int rc = 0; | |
ad1e9380 | 730 | struct rio_priv *priv = mport->priv; |
2b0c28d7 MP |
731 | |
732 | pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", | |
ad1e9380 | 733 | priv->msg_rx_ring.rx_slot); |
2b0c28d7 | 734 | |
ad1e9380 | 735 | if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) { |
2b0c28d7 MP |
736 | printk(KERN_ERR |
737 | "RIO: error adding inbound buffer %d, buffer exists\n", | |
ad1e9380 | 738 | priv->msg_rx_ring.rx_slot); |
2b0c28d7 MP |
739 | rc = -EINVAL; |
740 | goto out; | |
741 | } | |
742 | ||
ad1e9380 ZW |
743 | priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf; |
744 | if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size) | |
745 | priv->msg_rx_ring.rx_slot = 0; | |
2b0c28d7 MP |
746 | |
747 | out: | |
748 | return rc; | |
749 | } | |
750 | ||
751 | EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer); | |
752 | ||
753 | /** | |
754 | * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit | |
755 | * @mport: Master port implementing the inbound message unit | |
756 | * @mbox: Inbound mailbox number | |
757 | * | |
758 | * Gets the next available inbound message from the inbound message queue. | |
759 | * A pointer to the message is returned on success or NULL on failure. | |
760 | */ | |
761 | void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox) | |
762 | { | |
ad1e9380 | 763 | struct rio_priv *priv = mport->priv; |
2b0c28d7 MP |
764 | u32 phys_buf, virt_buf; |
765 | void *buf = NULL; | |
766 | int buf_idx; | |
767 | ||
ad1e9380 | 768 | phys_buf = in_be32(&priv->msg_regs->ifqdpar); |
2b0c28d7 MP |
769 | |
770 | /* If no more messages, then bail out */ | |
ad1e9380 | 771 | if (phys_buf == in_be32(&priv->msg_regs->ifqepar)) |
2b0c28d7 MP |
772 | goto out2; |
773 | ||
ad1e9380 ZW |
774 | virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf |
775 | - priv->msg_rx_ring.phys); | |
776 | buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; | |
777 | buf = priv->msg_rx_ring.virt_buffer[buf_idx]; | |
2b0c28d7 MP |
778 | |
779 | if (!buf) { | |
780 | printk(KERN_ERR | |
781 | "RIO: inbound message copy failed, no buffers\n"); | |
782 | goto out1; | |
783 | } | |
784 | ||
785 | /* Copy max message size, caller is expected to allocate that big */ | |
786 | memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE); | |
787 | ||
788 | /* Clear the available buffer */ | |
ad1e9380 | 789 | priv->msg_rx_ring.virt_buffer[buf_idx] = NULL; |
2b0c28d7 MP |
790 | |
791 | out1: | |
ad1e9380 | 792 | setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI); |
2b0c28d7 MP |
793 | |
794 | out2: | |
795 | return buf; | |
796 | } | |
797 | ||
798 | EXPORT_SYMBOL_GPL(rio_hw_get_inb_message); | |
799 | ||
800 | /** | |
d02443a6 | 801 | * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler |
2b0c28d7 MP |
802 | * @irq: Linux interrupt number |
803 | * @dev_instance: Pointer to interrupt-specific data | |
2b0c28d7 MP |
804 | * |
805 | * Handles doorbell interrupts. Parses a list of registered | |
806 | * doorbell event handlers and executes a matching event handler. | |
807 | */ | |
808 | static irqreturn_t | |
d02443a6 | 809 | fsl_rio_dbell_handler(int irq, void *dev_instance) |
2b0c28d7 MP |
810 | { |
811 | int dsr; | |
812 | struct rio_mport *port = (struct rio_mport *)dev_instance; | |
ad1e9380 | 813 | struct rio_priv *priv = port->priv; |
2b0c28d7 | 814 | |
ad1e9380 | 815 | dsr = in_be32(&priv->msg_regs->dsr); |
2b0c28d7 MP |
816 | |
817 | if (dsr & DOORBELL_DSR_TE) { | |
818 | pr_info("RIO: doorbell reception error\n"); | |
ad1e9380 | 819 | out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE); |
2b0c28d7 MP |
820 | goto out; |
821 | } | |
822 | ||
823 | if (dsr & DOORBELL_DSR_QFI) { | |
824 | pr_info("RIO: doorbell queue full\n"); | |
ad1e9380 | 825 | out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI); |
2b0c28d7 MP |
826 | goto out; |
827 | } | |
828 | ||
829 | /* XXX Need to check/dispatch until queue empty */ | |
830 | if (dsr & DOORBELL_DSR_DIQI) { | |
831 | u32 dmsg = | |
ad1e9380 ZW |
832 | (u32) priv->dbell_ring.virt + |
833 | (in_be32(&priv->msg_regs->dqdpar) & 0xfff); | |
2b0c28d7 MP |
834 | struct rio_dbell *dbell; |
835 | int found = 0; | |
836 | ||
837 | pr_debug | |
838 | ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n", | |
839 | DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); | |
840 | ||
841 | list_for_each_entry(dbell, &port->dbells, node) { | |
842 | if ((dbell->res->start <= DBELL_INF(dmsg)) && | |
843 | (dbell->res->end >= DBELL_INF(dmsg))) { | |
844 | found = 1; | |
845 | break; | |
846 | } | |
847 | } | |
848 | if (found) { | |
6978bbc0 | 849 | dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg), |
2b0c28d7 MP |
850 | DBELL_INF(dmsg)); |
851 | } else { | |
852 | pr_debug | |
853 | ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n", | |
854 | DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); | |
855 | } | |
ad1e9380 ZW |
856 | setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI); |
857 | out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI); | |
2b0c28d7 MP |
858 | } |
859 | ||
860 | out: | |
861 | return IRQ_HANDLED; | |
862 | } | |
863 | ||
864 | /** | |
d02443a6 | 865 | * fsl_rio_doorbell_init - MPC85xx doorbell interface init |
2b0c28d7 MP |
866 | * @mport: Master port implementing the inbound doorbell unit |
867 | * | |
868 | * Initializes doorbell unit hardware and inbound DMA buffer | |
d02443a6 | 869 | * ring. Called from fsl_rio_setup(). Returns %0 on success |
2b0c28d7 MP |
870 | * or %-ENOMEM on failure. |
871 | */ | |
d02443a6 | 872 | static int fsl_rio_doorbell_init(struct rio_mport *mport) |
2b0c28d7 | 873 | { |
ad1e9380 | 874 | struct rio_priv *priv = mport->priv; |
2b0c28d7 MP |
875 | int rc = 0; |
876 | ||
877 | /* Map outbound doorbell window immediately after maintenance window */ | |
ad1e9380 ZW |
878 | priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE, |
879 | RIO_DBELL_WIN_SIZE); | |
880 | if (!priv->dbell_win) { | |
2b0c28d7 MP |
881 | printk(KERN_ERR |
882 | "RIO: unable to map outbound doorbell window\n"); | |
883 | rc = -ENOMEM; | |
884 | goto out; | |
885 | } | |
886 | ||
887 | /* Initialize inbound doorbells */ | |
ad1e9380 ZW |
888 | priv->dbell_ring.virt = dma_alloc_coherent(NULL, 512 * |
889 | DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL); | |
890 | if (!priv->dbell_ring.virt) { | |
2b0c28d7 MP |
891 | printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n"); |
892 | rc = -ENOMEM; | |
ad1e9380 | 893 | iounmap(priv->dbell_win); |
2b0c28d7 MP |
894 | goto out; |
895 | } | |
896 | ||
897 | /* Point dequeue/enqueue pointers at first entry in ring */ | |
ad1e9380 ZW |
898 | out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys); |
899 | out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys); | |
2b0c28d7 MP |
900 | |
901 | /* Clear interrupt status */ | |
ad1e9380 | 902 | out_be32(&priv->msg_regs->dsr, 0x00000091); |
2b0c28d7 MP |
903 | |
904 | /* Hook up doorbell handler */ | |
ad1e9380 ZW |
905 | rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0, |
906 | "dbell_rx", (void *)mport); | |
907 | if (rc < 0) { | |
908 | iounmap(priv->dbell_win); | |
2b0c28d7 | 909 | dma_free_coherent(NULL, 512 * DOORBELL_MESSAGE_SIZE, |
ad1e9380 | 910 | priv->dbell_ring.virt, priv->dbell_ring.phys); |
2b0c28d7 MP |
911 | printk(KERN_ERR |
912 | "MPC85xx RIO: unable to request inbound doorbell irq"); | |
913 | goto out; | |
914 | } | |
915 | ||
916 | /* Configure doorbells for snooping, 512 entries, and enable */ | |
ad1e9380 | 917 | out_be32(&priv->msg_regs->dmr, 0x00108161); |
2b0c28d7 MP |
918 | |
919 | out: | |
920 | return rc; | |
921 | } | |
922 | ||
923 | static char *cmdline = NULL; | |
924 | ||
d02443a6 | 925 | static int fsl_rio_get_hdid(int index) |
2b0c28d7 MP |
926 | { |
927 | /* XXX Need to parse multiple entries in some format */ | |
928 | if (!cmdline) | |
929 | return -1; | |
930 | ||
931 | return simple_strtol(cmdline, NULL, 0); | |
932 | } | |
933 | ||
d02443a6 | 934 | static int fsl_rio_get_cmdline(char *s) |
2b0c28d7 MP |
935 | { |
936 | if (!s) | |
937 | return 0; | |
938 | ||
939 | cmdline = s; | |
940 | return 1; | |
941 | } | |
942 | ||
d02443a6 | 943 | __setup("riohdid=", fsl_rio_get_cmdline); |
2b0c28d7 MP |
944 | |
945 | /** | |
d02443a6 | 946 | * fsl_rio_setup - Setup MPC85xx RapidIO interface |
cc2bb696 | 947 | * @fsl_rio_setup - Setup Freescale PowerPC RapidIO interface |
2b0c28d7 MP |
948 | * |
949 | * Initializes MPC85xx RapidIO hardware interface, configures | |
950 | * master port with system-specific info, and registers the | |
951 | * master port with the RapidIO subsystem. | |
952 | */ | |
cc2bb696 | 953 | int fsl_rio_setup(struct of_device *dev) |
2b0c28d7 MP |
954 | { |
955 | struct rio_ops *ops; | |
956 | struct rio_mport *port; | |
cc2bb696 ZW |
957 | struct rio_priv *priv; |
958 | int rc = 0; | |
959 | const u32 *dt_range, *cell; | |
960 | struct resource regs; | |
961 | int rlen; | |
61b26917 | 962 | u32 ccsr; |
cc2bb696 ZW |
963 | u64 law_start, law_size; |
964 | int paw, aw, sw; | |
965 | ||
966 | if (!dev->node) { | |
967 | dev_err(&dev->dev, "Device OF-Node is NULL"); | |
968 | return -EFAULT; | |
969 | } | |
970 | ||
971 | rc = of_address_to_resource(dev->node, 0, ®s); | |
972 | if (rc) { | |
973 | dev_err(&dev->dev, "Can't get %s property 'reg'\n", | |
974 | dev->node->full_name); | |
975 | return -EFAULT; | |
976 | } | |
977 | dev_info(&dev->dev, "Of-device full name %s\n", dev->node->full_name); | |
978 | dev_info(&dev->dev, "Regs start 0x%08x size 0x%08x\n", regs.start, | |
979 | regs.end - regs.start + 1); | |
980 | ||
981 | dt_range = of_get_property(dev->node, "ranges", &rlen); | |
982 | if (!dt_range) { | |
983 | dev_err(&dev->dev, "Can't get %s property 'ranges'\n", | |
984 | dev->node->full_name); | |
985 | return -EFAULT; | |
986 | } | |
987 | ||
988 | /* Get node address wide */ | |
989 | cell = of_get_property(dev->node, "#address-cells", NULL); | |
990 | if (cell) | |
991 | aw = *cell; | |
992 | else | |
993 | aw = of_n_addr_cells(dev->node); | |
994 | /* Get node size wide */ | |
995 | cell = of_get_property(dev->node, "#size-cells", NULL); | |
996 | if (cell) | |
997 | sw = *cell; | |
998 | else | |
999 | sw = of_n_size_cells(dev->node); | |
1000 | /* Get parent address wide wide */ | |
1001 | paw = of_n_addr_cells(dev->node); | |
1002 | ||
1003 | law_start = of_read_number(dt_range + aw, paw); | |
1004 | law_size = of_read_number(dt_range + aw + paw, sw); | |
1005 | ||
1006 | dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n", | |
1007 | law_start, law_size); | |
2b0c28d7 MP |
1008 | |
1009 | ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL); | |
d02443a6 ZW |
1010 | ops->lcread = fsl_local_config_read; |
1011 | ops->lcwrite = fsl_local_config_write; | |
1012 | ops->cread = fsl_rio_config_read; | |
1013 | ops->cwrite = fsl_rio_config_write; | |
1014 | ops->dsend = fsl_rio_doorbell_send; | |
2b0c28d7 | 1015 | |
ad1e9380 | 1016 | port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); |
2b0c28d7 MP |
1017 | port->id = 0; |
1018 | port->index = 0; | |
ad1e9380 ZW |
1019 | |
1020 | priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL); | |
1021 | if (!priv) { | |
1022 | printk(KERN_ERR "Can't alloc memory for 'priv'\n"); | |
1023 | rc = -ENOMEM; | |
1024 | goto err; | |
1025 | } | |
1026 | ||
2b0c28d7 MP |
1027 | INIT_LIST_HEAD(&port->dbells); |
1028 | port->iores.start = law_start; | |
1029 | port->iores.end = law_start + law_size; | |
1030 | port->iores.flags = IORESOURCE_MEM; | |
1031 | ||
cc2bb696 ZW |
1032 | priv->bellirq = irq_of_parse_and_map(dev->node, 2); |
1033 | priv->txirq = irq_of_parse_and_map(dev->node, 3); | |
1034 | priv->rxirq = irq_of_parse_and_map(dev->node, 4); | |
1035 | dev_info(&dev->dev, "bellirq: %d, txirq: %d, rxirq %d\n", priv->bellirq, | |
1036 | priv->txirq, priv->rxirq); | |
1037 | ||
2b0c28d7 MP |
1038 | rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); |
1039 | rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0); | |
1040 | rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); | |
1041 | strcpy(port->name, "RIO0 mport"); | |
1042 | ||
1043 | port->ops = ops; | |
d02443a6 | 1044 | port->host_deviceid = fsl_rio_get_hdid(port->id); |
2b0c28d7 | 1045 | |
ad1e9380 | 1046 | port->priv = priv; |
2b0c28d7 MP |
1047 | rio_register_mport(port); |
1048 | ||
cc2bb696 | 1049 | priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1); |
e0423236 | 1050 | |
61b26917 ZW |
1051 | /* Probe the master port phy type */ |
1052 | ccsr = in_be32(priv->regs_win + RIO_CCSR); | |
1053 | port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL; | |
1054 | dev_info(&dev->dev, "RapidIO PHY type: %s\n", | |
1055 | (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" : | |
1056 | ((port->phy_type == RIO_PHY_SERIAL) ? "serial" : | |
1057 | "unknown")); | |
1058 | ||
e0423236 ZW |
1059 | port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR)) |
1060 | & RIO_PEF_CTLS) >> 4; | |
1061 | dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", | |
1062 | port->sys_size ? 65536 : 256); | |
1063 | ||
ad1e9380 ZW |
1064 | priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win |
1065 | + RIO_ATMU_REGS_OFFSET); | |
1066 | priv->maint_atmu_regs = priv->atmu_regs + 1; | |
1067 | priv->dbell_atmu_regs = priv->atmu_regs + 2; | |
61b26917 ZW |
1068 | priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win + |
1069 | ((port->phy_type == RIO_PHY_SERIAL) ? | |
1070 | RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET)); | |
1071 | ||
1072 | /* Set to receive any dist ID for serial RapidIO controller. */ | |
1073 | if (port->phy_type == RIO_PHY_SERIAL) | |
1074 | out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA); | |
2b0c28d7 MP |
1075 | |
1076 | /* Configure maintenance transaction window */ | |
ad1e9380 ZW |
1077 | out_be32(&priv->maint_atmu_regs->rowbar, 0x000c0000); |
1078 | out_be32(&priv->maint_atmu_regs->rowar, 0x80077015); | |
2b0c28d7 | 1079 | |
ad1e9380 | 1080 | priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE); |
2b0c28d7 MP |
1081 | |
1082 | /* Configure outbound doorbell window */ | |
ad1e9380 ZW |
1083 | out_be32(&priv->dbell_atmu_regs->rowbar, 0x000c0400); |
1084 | out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); | |
d02443a6 | 1085 | fsl_rio_doorbell_init(port); |
ad1e9380 | 1086 | |
cc2bb696 | 1087 | return 0; |
ad1e9380 ZW |
1088 | err: |
1089 | if (priv) | |
1090 | iounmap(priv->regs_win); | |
cc2bb696 | 1091 | kfree(ops); |
ad1e9380 ZW |
1092 | kfree(priv); |
1093 | kfree(port); | |
cc2bb696 | 1094 | return rc; |
2b0c28d7 | 1095 | } |
cc2bb696 ZW |
1096 | |
1097 | /* The probe function for RapidIO peer-to-peer network. | |
1098 | */ | |
1099 | static int __devinit fsl_of_rio_rpn_probe(struct of_device *dev, | |
1100 | const struct of_device_id *match) | |
1101 | { | |
1102 | int rc; | |
1103 | printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n", | |
1104 | dev->node->full_name); | |
1105 | ||
1106 | rc = fsl_rio_setup(dev); | |
1107 | if (rc) | |
1108 | goto out; | |
1109 | ||
1110 | /* Enumerate all registered ports */ | |
1111 | rc = rio_init_mports(); | |
1112 | out: | |
1113 | return rc; | |
1114 | }; | |
1115 | ||
1116 | static const struct of_device_id fsl_of_rio_rpn_ids[] = { | |
1117 | { | |
1118 | .compatible = "fsl,rapidio-delta", | |
1119 | }, | |
1120 | {}, | |
1121 | }; | |
1122 | ||
1123 | static struct of_platform_driver fsl_of_rio_rpn_driver = { | |
1124 | .name = "fsl-of-rio", | |
1125 | .match_table = fsl_of_rio_rpn_ids, | |
1126 | .probe = fsl_of_rio_rpn_probe, | |
1127 | }; | |
1128 | ||
1129 | static __init int fsl_of_rio_rpn_init(void) | |
1130 | { | |
1131 | return of_register_platform_driver(&fsl_of_rio_rpn_driver); | |
1132 | } | |
1133 | ||
1134 | subsys_initcall(fsl_of_rio_rpn_init); |