Commit | Line | Data |
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2b0c28d7 | 1 | /* |
d02443a6 | 2 | * Freescale MPC85xx/MPC86xx RapidIO support |
2b0c28d7 | 3 | * |
bd4fb654 TM |
4 | * Copyright 2009 Sysgo AG |
5 | * Thomas Moll <thomas.moll@sysgo.com> | |
6 | * - fixed maintenance access routines, check for aligned access | |
7 | * | |
5b2074ae AB |
8 | * Copyright 2009 Integrated Device Technology, Inc. |
9 | * Alex Bounine <alexandre.bounine@idt.com> | |
10 | * - Added Port-Write message handling | |
11 | * - Added Machine Check exception handling | |
12 | * | |
6ff31453 | 13 | * Copyright (C) 2007, 2008, 2010 Freescale Semiconductor, Inc. |
ad1e9380 ZW |
14 | * Zhang Wei <wei.zhang@freescale.com> |
15 | * | |
2b0c28d7 MP |
16 | * Copyright 2005 MontaVista Software, Inc. |
17 | * Matt Porter <mporter@kernel.crashing.org> | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or modify it | |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2 of the License, or (at your | |
22 | * option) any later version. | |
23 | */ | |
24 | ||
2b0c28d7 MP |
25 | #include <linux/init.h> |
26 | #include <linux/module.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | #include <linux/interrupt.h> | |
0dbbbf1a | 30 | #include <linux/device.h> |
2b0c28d7 MP |
31 | #include <linux/rio.h> |
32 | #include <linux/rio_drv.h> | |
cc2bb696 | 33 | #include <linux/of_platform.h> |
61b26917 | 34 | #include <linux/delay.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
5b2074ae | 36 | #include <linux/kfifo.h> |
2b0c28d7 MP |
37 | |
38 | #include <asm/io.h> | |
a52c8f52 AB |
39 | #include <asm/machdep.h> |
40 | #include <asm/uaccess.h> | |
2b0c28d7 | 41 | |
5b2074ae AB |
42 | #undef DEBUG_PW /* Port-Write debugging */ |
43 | ||
ad1e9380 ZW |
44 | /* RapidIO definition irq, which read from OF-tree */ |
45 | #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq) | |
46 | #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq) | |
47 | #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq) | |
5b2074ae | 48 | #define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq) |
ad1e9380 | 49 | |
6ff31453 SX |
50 | #define IPWSR_CLEAR 0x98 |
51 | #define OMSR_CLEAR 0x1cb3 | |
52 | #define IMSR_CLEAR 0x491 | |
53 | #define IDSR_CLEAR 0x91 | |
54 | #define ODSR_CLEAR 0x1c00 | |
55 | #define LTLEECSR_ENABLE_ALL 0xFFC000FC | |
56 | #define ESCSR_CLEAR 0x07120204 | |
57 | ||
58 | #define RIO_PORT1_EDCSR 0x0640 | |
59 | #define RIO_PORT2_EDCSR 0x0680 | |
60 | #define RIO_PORT1_IECSR 0x10130 | |
61 | #define RIO_PORT2_IECSR 0x101B0 | |
62 | #define RIO_IM0SR 0x13064 | |
63 | #define RIO_IM1SR 0x13164 | |
64 | #define RIO_OM0SR 0x13004 | |
65 | #define RIO_OM1SR 0x13104 | |
66 | ||
2b0c28d7 | 67 | #define RIO_ATMU_REGS_OFFSET 0x10c00 |
61b26917 ZW |
68 | #define RIO_P_MSG_REGS_OFFSET 0x11000 |
69 | #define RIO_S_MSG_REGS_OFFSET 0x13000 | |
af84ca38 | 70 | #define RIO_GCCSR 0x13c |
61b26917 | 71 | #define RIO_ESCSR 0x158 |
6ff31453 | 72 | #define RIO_PORT2_ESCSR 0x178 |
61b26917 | 73 | #define RIO_CCSR 0x15c |
5b2074ae | 74 | #define RIO_LTLEDCSR 0x0608 |
6ff31453 SX |
75 | #define RIO_LTLEDCSR_IER 0x80000000 |
76 | #define RIO_LTLEDCSR_PRT 0x01000000 | |
5b2074ae AB |
77 | #define RIO_LTLEECSR 0x060c |
78 | #define RIO_EPWISR 0x10010 | |
61b26917 ZW |
79 | #define RIO_ISR_AACR 0x10120 |
80 | #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */ | |
2b0c28d7 MP |
81 | #define RIO_MAINT_WIN_SIZE 0x400000 |
82 | #define RIO_DBELL_WIN_SIZE 0x1000 | |
83 | ||
84 | #define RIO_MSG_OMR_MUI 0x00000002 | |
85 | #define RIO_MSG_OSR_TE 0x00000080 | |
86 | #define RIO_MSG_OSR_QOI 0x00000020 | |
87 | #define RIO_MSG_OSR_QFI 0x00000010 | |
88 | #define RIO_MSG_OSR_MUB 0x00000004 | |
89 | #define RIO_MSG_OSR_EOMI 0x00000002 | |
90 | #define RIO_MSG_OSR_QEI 0x00000001 | |
91 | ||
92 | #define RIO_MSG_IMR_MI 0x00000002 | |
93 | #define RIO_MSG_ISR_TE 0x00000080 | |
94 | #define RIO_MSG_ISR_QFI 0x00000010 | |
95 | #define RIO_MSG_ISR_DIQI 0x00000001 | |
96 | ||
5b2074ae AB |
97 | #define RIO_IPWMR_SEN 0x00100000 |
98 | #define RIO_IPWMR_QFIE 0x00000100 | |
99 | #define RIO_IPWMR_EIE 0x00000020 | |
100 | #define RIO_IPWMR_CQ 0x00000002 | |
101 | #define RIO_IPWMR_PWE 0x00000001 | |
102 | ||
103 | #define RIO_IPWSR_QF 0x00100000 | |
104 | #define RIO_IPWSR_TE 0x00000080 | |
105 | #define RIO_IPWSR_QFI 0x00000010 | |
106 | #define RIO_IPWSR_PWD 0x00000008 | |
107 | #define RIO_IPWSR_PWB 0x00000004 | |
108 | ||
6ff31453 SX |
109 | /* EPWISR Error match value */ |
110 | #define RIO_EPWISR_PINT1 0x80000000 | |
111 | #define RIO_EPWISR_PINT2 0x40000000 | |
112 | #define RIO_EPWISR_MU 0x00000002 | |
93e2cbd2 AB |
113 | #define RIO_EPWISR_PW 0x00000001 |
114 | ||
2b0c28d7 MP |
115 | #define RIO_MSG_DESC_SIZE 32 |
116 | #define RIO_MSG_BUFFER_SIZE 4096 | |
117 | #define RIO_MIN_TX_RING_SIZE 2 | |
118 | #define RIO_MAX_TX_RING_SIZE 2048 | |
119 | #define RIO_MIN_RX_RING_SIZE 2 | |
120 | #define RIO_MAX_RX_RING_SIZE 2048 | |
121 | ||
122 | #define DOORBELL_DMR_DI 0x00000002 | |
123 | #define DOORBELL_DSR_TE 0x00000080 | |
124 | #define DOORBELL_DSR_QFI 0x00000010 | |
125 | #define DOORBELL_DSR_DIQI 0x00000001 | |
6c39103c ZW |
126 | #define DOORBELL_TID_OFFSET 0x02 |
127 | #define DOORBELL_SID_OFFSET 0x04 | |
2b0c28d7 MP |
128 | #define DOORBELL_INFO_OFFSET 0x06 |
129 | ||
130 | #define DOORBELL_MESSAGE_SIZE 0x08 | |
6c39103c ZW |
131 | #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET)) |
132 | #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET)) | |
2b0c28d7 MP |
133 | #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET)) |
134 | ||
2b0c28d7 MP |
135 | struct rio_atmu_regs { |
136 | u32 rowtar; | |
61b26917 | 137 | u32 rowtear; |
2b0c28d7 MP |
138 | u32 rowbar; |
139 | u32 pad2; | |
140 | u32 rowar; | |
141 | u32 pad3[3]; | |
142 | }; | |
143 | ||
144 | struct rio_msg_regs { | |
abd12fe4 SX |
145 | u32 omr; /* 0xD_3000 - Outbound message 0 mode register */ |
146 | u32 osr; /* 0xD_3004 - Outbound message 0 status register */ | |
2b0c28d7 | 147 | u32 pad1; |
abd12fe4 SX |
148 | u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue |
149 | dequeue pointer address register */ | |
2b0c28d7 | 150 | u32 pad2; |
abd12fe4 SX |
151 | u32 osar; /* 0xD_3014 - Outbound message 0 source address |
152 | register */ | |
153 | u32 odpr; /* 0xD_3018 - Outbound message 0 destination port | |
154 | register */ | |
155 | u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes | |
156 | Register*/ | |
157 | u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count | |
158 | register */ | |
2b0c28d7 | 159 | u32 pad3; |
abd12fe4 SX |
160 | u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue |
161 | enqueue pointer address register */ | |
2b0c28d7 | 162 | u32 pad4[13]; |
abd12fe4 SX |
163 | u32 imr; /* 0xD_3060 - Inbound message 0 mode register */ |
164 | u32 isr; /* 0xD_3064 - Inbound message 0 status register */ | |
2b0c28d7 | 165 | u32 pad5; |
abd12fe4 SX |
166 | u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue |
167 | pointer address register*/ | |
2b0c28d7 | 168 | u32 pad6; |
abd12fe4 SX |
169 | u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue |
170 | pointer address register */ | |
61b26917 | 171 | u32 pad7[226]; |
abd12fe4 SX |
172 | u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */ |
173 | u32 odsr; /* 0xD_3404 - Outbound doorbell status register */ | |
61b26917 | 174 | u32 res0[4]; |
abd12fe4 SX |
175 | u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port |
176 | register */ | |
177 | u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes | |
178 | register */ | |
61b26917 | 179 | u32 res1[3]; |
abd12fe4 SX |
180 | u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold |
181 | configuration register */ | |
61b26917 | 182 | u32 res2[12]; |
abd12fe4 SX |
183 | u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */ |
184 | u32 dsr; /* 0xD_3464 - Inbound doorbell status register */ | |
2b0c28d7 | 185 | u32 pad8; |
abd12fe4 SX |
186 | u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer |
187 | address register */ | |
2b0c28d7 | 188 | u32 pad9; |
abd12fe4 SX |
189 | u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer |
190 | address register */ | |
2b0c28d7 | 191 | u32 pad10[26]; |
abd12fe4 SX |
192 | u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */ |
193 | u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */ | |
194 | u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address | |
195 | register */ | |
196 | u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address | |
197 | register */ | |
2b0c28d7 MP |
198 | }; |
199 | ||
200 | struct rio_tx_desc { | |
201 | u32 res1; | |
202 | u32 saddr; | |
203 | u32 dport; | |
204 | u32 dattr; | |
205 | u32 res2; | |
206 | u32 res3; | |
207 | u32 dwcnt; | |
208 | u32 res4; | |
209 | }; | |
210 | ||
ad1e9380 | 211 | struct rio_dbell_ring { |
2b0c28d7 MP |
212 | void *virt; |
213 | dma_addr_t phys; | |
ad1e9380 | 214 | }; |
2b0c28d7 | 215 | |
ad1e9380 | 216 | struct rio_msg_tx_ring { |
2b0c28d7 MP |
217 | void *virt; |
218 | dma_addr_t phys; | |
219 | void *virt_buffer[RIO_MAX_TX_RING_SIZE]; | |
220 | dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE]; | |
221 | int tx_slot; | |
222 | int size; | |
6978bbc0 | 223 | void *dev_id; |
ad1e9380 | 224 | }; |
2b0c28d7 | 225 | |
ad1e9380 | 226 | struct rio_msg_rx_ring { |
2b0c28d7 MP |
227 | void *virt; |
228 | dma_addr_t phys; | |
229 | void *virt_buffer[RIO_MAX_RX_RING_SIZE]; | |
230 | int rx_slot; | |
231 | int size; | |
6978bbc0 | 232 | void *dev_id; |
ad1e9380 ZW |
233 | }; |
234 | ||
5b2074ae AB |
235 | struct rio_port_write_msg { |
236 | void *virt; | |
237 | dma_addr_t phys; | |
238 | u32 msg_count; | |
239 | u32 err_count; | |
240 | u32 discard_count; | |
241 | }; | |
242 | ||
ad1e9380 | 243 | struct rio_priv { |
0dbbbf1a | 244 | struct device *dev; |
ad1e9380 ZW |
245 | void __iomem *regs_win; |
246 | struct rio_atmu_regs __iomem *atmu_regs; | |
247 | struct rio_atmu_regs __iomem *maint_atmu_regs; | |
248 | struct rio_atmu_regs __iomem *dbell_atmu_regs; | |
249 | void __iomem *dbell_win; | |
250 | void __iomem *maint_win; | |
251 | struct rio_msg_regs __iomem *msg_regs; | |
252 | struct rio_dbell_ring dbell_ring; | |
253 | struct rio_msg_tx_ring msg_tx_ring; | |
254 | struct rio_msg_rx_ring msg_rx_ring; | |
5b2074ae | 255 | struct rio_port_write_msg port_write_msg; |
ad1e9380 ZW |
256 | int bellirq; |
257 | int txirq; | |
258 | int rxirq; | |
5b2074ae AB |
259 | int pwirq; |
260 | struct work_struct pw_work; | |
261 | struct kfifo pw_fifo; | |
262 | spinlock_t pw_fifo_lock; | |
ad1e9380 | 263 | }; |
2b0c28d7 | 264 | |
a52c8f52 AB |
265 | #define __fsl_read_rio_config(x, addr, err, op) \ |
266 | __asm__ __volatile__( \ | |
267 | "1: "op" %1,0(%2)\n" \ | |
268 | " eieio\n" \ | |
269 | "2:\n" \ | |
270 | ".section .fixup,\"ax\"\n" \ | |
271 | "3: li %1,-1\n" \ | |
272 | " li %0,%3\n" \ | |
273 | " b 2b\n" \ | |
274 | ".section __ex_table,\"a\"\n" \ | |
275 | " .align 2\n" \ | |
276 | " .long 1b,3b\n" \ | |
277 | ".text" \ | |
278 | : "=r" (err), "=r" (x) \ | |
279 | : "b" (addr), "i" (-EFAULT), "0" (err)) | |
280 | ||
281 | static void __iomem *rio_regs_win; | |
282 | ||
ff33f182 | 283 | #ifdef CONFIG_E500 |
cce1f106 | 284 | int fsl_rio_mcheck_exception(struct pt_regs *regs) |
a52c8f52 | 285 | { |
82a9a480 SW |
286 | const struct exception_table_entry *entry; |
287 | unsigned long reason; | |
a52c8f52 | 288 | |
82a9a480 SW |
289 | if (!rio_regs_win) |
290 | return 0; | |
291 | ||
292 | reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR)); | |
293 | if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) { | |
294 | /* Check if we are prepared to handle this fault */ | |
295 | entry = search_exception_tables(regs->nip); | |
296 | if (entry) { | |
297 | pr_debug("RIO: %s - MC Exception handled\n", | |
298 | __func__); | |
299 | out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), | |
300 | 0); | |
301 | regs->msr |= MSR_RI; | |
302 | regs->nip = entry->fixup; | |
303 | return 1; | |
a52c8f52 AB |
304 | } |
305 | } | |
306 | ||
cce1f106 | 307 | return 0; |
a52c8f52 | 308 | } |
cce1f106 | 309 | EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception); |
ff33f182 | 310 | #endif |
a52c8f52 | 311 | |
2b0c28d7 | 312 | /** |
d02443a6 | 313 | * fsl_rio_doorbell_send - Send a MPC85xx doorbell message |
9941d945 | 314 | * @mport: RapidIO master port info |
2b0c28d7 MP |
315 | * @index: ID of RapidIO interface |
316 | * @destid: Destination ID of target device | |
317 | * @data: 16-bit info field of RapidIO doorbell message | |
318 | * | |
319 | * Sends a MPC85xx doorbell message. Returns %0 on success or | |
320 | * %-EINVAL on failure. | |
321 | */ | |
ad1e9380 ZW |
322 | static int fsl_rio_doorbell_send(struct rio_mport *mport, |
323 | int index, u16 destid, u16 data) | |
2b0c28d7 | 324 | { |
ad1e9380 | 325 | struct rio_priv *priv = mport->priv; |
d02443a6 | 326 | pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n", |
2b0c28d7 | 327 | index, destid, data); |
61b26917 ZW |
328 | switch (mport->phy_type) { |
329 | case RIO_PHY_PARALLEL: | |
330 | out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22); | |
331 | out_be16(priv->dbell_win, data); | |
332 | break; | |
333 | case RIO_PHY_SERIAL: | |
334 | /* In the serial version silicons, such as MPC8548, MPC8641, | |
335 | * below operations is must be. | |
336 | */ | |
337 | out_be32(&priv->msg_regs->odmr, 0x00000000); | |
338 | out_be32(&priv->msg_regs->odretcr, 0x00000004); | |
339 | out_be32(&priv->msg_regs->oddpr, destid << 16); | |
340 | out_be32(&priv->msg_regs->oddatr, data); | |
341 | out_be32(&priv->msg_regs->odmr, 0x00000001); | |
342 | break; | |
343 | } | |
2b0c28d7 MP |
344 | |
345 | return 0; | |
346 | } | |
347 | ||
348 | /** | |
d02443a6 | 349 | * fsl_local_config_read - Generate a MPC85xx local config space read |
9941d945 | 350 | * @mport: RapidIO master port info |
2b0c28d7 MP |
351 | * @index: ID of RapdiIO interface |
352 | * @offset: Offset into configuration space | |
353 | * @len: Length (in bytes) of the maintenance transaction | |
354 | * @data: Value to be read into | |
355 | * | |
356 | * Generates a MPC85xx local configuration space read. Returns %0 on | |
357 | * success or %-EINVAL on failure. | |
358 | */ | |
ad1e9380 ZW |
359 | static int fsl_local_config_read(struct rio_mport *mport, |
360 | int index, u32 offset, int len, u32 *data) | |
2b0c28d7 | 361 | { |
ad1e9380 | 362 | struct rio_priv *priv = mport->priv; |
d02443a6 | 363 | pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index, |
2b0c28d7 | 364 | offset); |
ad1e9380 | 365 | *data = in_be32(priv->regs_win + offset); |
2b0c28d7 MP |
366 | |
367 | return 0; | |
368 | } | |
369 | ||
370 | /** | |
d02443a6 | 371 | * fsl_local_config_write - Generate a MPC85xx local config space write |
9941d945 | 372 | * @mport: RapidIO master port info |
2b0c28d7 MP |
373 | * @index: ID of RapdiIO interface |
374 | * @offset: Offset into configuration space | |
375 | * @len: Length (in bytes) of the maintenance transaction | |
376 | * @data: Value to be written | |
377 | * | |
378 | * Generates a MPC85xx local configuration space write. Returns %0 on | |
379 | * success or %-EINVAL on failure. | |
380 | */ | |
ad1e9380 ZW |
381 | static int fsl_local_config_write(struct rio_mport *mport, |
382 | int index, u32 offset, int len, u32 data) | |
2b0c28d7 | 383 | { |
ad1e9380 | 384 | struct rio_priv *priv = mport->priv; |
2b0c28d7 | 385 | pr_debug |
d02443a6 | 386 | ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n", |
2b0c28d7 | 387 | index, offset, data); |
ad1e9380 | 388 | out_be32(priv->regs_win + offset, data); |
2b0c28d7 MP |
389 | |
390 | return 0; | |
391 | } | |
392 | ||
393 | /** | |
d02443a6 | 394 | * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction |
9941d945 | 395 | * @mport: RapidIO master port info |
2b0c28d7 MP |
396 | * @index: ID of RapdiIO interface |
397 | * @destid: Destination ID of transaction | |
398 | * @hopcount: Number of hops to target device | |
399 | * @offset: Offset into configuration space | |
400 | * @len: Length (in bytes) of the maintenance transaction | |
401 | * @val: Location to be read into | |
402 | * | |
403 | * Generates a MPC85xx read maintenance transaction. Returns %0 on | |
404 | * success or %-EINVAL on failure. | |
405 | */ | |
406 | static int | |
ad1e9380 ZW |
407 | fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid, |
408 | u8 hopcount, u32 offset, int len, u32 *val) | |
2b0c28d7 | 409 | { |
ad1e9380 | 410 | struct rio_priv *priv = mport->priv; |
2b0c28d7 | 411 | u8 *data; |
a52c8f52 | 412 | u32 rval, err = 0; |
2b0c28d7 MP |
413 | |
414 | pr_debug | |
d02443a6 | 415 | ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n", |
2b0c28d7 | 416 | index, destid, hopcount, offset, len); |
bd4fb654 TM |
417 | |
418 | /* 16MB maintenance window possible */ | |
419 | /* allow only aligned access to maintenance registers */ | |
420 | if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) | |
421 | return -EINVAL; | |
422 | ||
ad1e9380 | 423 | out_be32(&priv->maint_atmu_regs->rowtar, |
bd4fb654 TM |
424 | (destid << 22) | (hopcount << 12) | (offset >> 12)); |
425 | out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); | |
2b0c28d7 | 426 | |
bd4fb654 | 427 | data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); |
2b0c28d7 MP |
428 | switch (len) { |
429 | case 1: | |
a52c8f52 | 430 | __fsl_read_rio_config(rval, data, err, "lbz"); |
2b0c28d7 MP |
431 | break; |
432 | case 2: | |
a52c8f52 | 433 | __fsl_read_rio_config(rval, data, err, "lhz"); |
2b0c28d7 | 434 | break; |
bd4fb654 | 435 | case 4: |
a52c8f52 | 436 | __fsl_read_rio_config(rval, data, err, "lwz"); |
2b0c28d7 | 437 | break; |
bd4fb654 TM |
438 | default: |
439 | return -EINVAL; | |
2b0c28d7 MP |
440 | } |
441 | ||
a52c8f52 AB |
442 | if (err) { |
443 | pr_debug("RIO: cfg_read error %d for %x:%x:%x\n", | |
444 | err, destid, hopcount, offset); | |
445 | } | |
446 | ||
447 | *val = rval; | |
448 | ||
449 | return err; | |
2b0c28d7 MP |
450 | } |
451 | ||
452 | /** | |
d02443a6 | 453 | * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction |
9941d945 | 454 | * @mport: RapidIO master port info |
2b0c28d7 MP |
455 | * @index: ID of RapdiIO interface |
456 | * @destid: Destination ID of transaction | |
457 | * @hopcount: Number of hops to target device | |
458 | * @offset: Offset into configuration space | |
459 | * @len: Length (in bytes) of the maintenance transaction | |
460 | * @val: Value to be written | |
461 | * | |
462 | * Generates an MPC85xx write maintenance transaction. Returns %0 on | |
463 | * success or %-EINVAL on failure. | |
464 | */ | |
465 | static int | |
ad1e9380 ZW |
466 | fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid, |
467 | u8 hopcount, u32 offset, int len, u32 val) | |
2b0c28d7 | 468 | { |
ad1e9380 | 469 | struct rio_priv *priv = mport->priv; |
2b0c28d7 MP |
470 | u8 *data; |
471 | pr_debug | |
d02443a6 | 472 | ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", |
2b0c28d7 | 473 | index, destid, hopcount, offset, len, val); |
bd4fb654 TM |
474 | |
475 | /* 16MB maintenance windows possible */ | |
476 | /* allow only aligned access to maintenance registers */ | |
477 | if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) | |
478 | return -EINVAL; | |
479 | ||
ad1e9380 | 480 | out_be32(&priv->maint_atmu_regs->rowtar, |
bd4fb654 TM |
481 | (destid << 22) | (hopcount << 12) | (offset >> 12)); |
482 | out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); | |
2b0c28d7 | 483 | |
bd4fb654 | 484 | data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); |
2b0c28d7 MP |
485 | switch (len) { |
486 | case 1: | |
487 | out_8((u8 *) data, val); | |
488 | break; | |
489 | case 2: | |
490 | out_be16((u16 *) data, val); | |
491 | break; | |
bd4fb654 | 492 | case 4: |
2b0c28d7 MP |
493 | out_be32((u32 *) data, val); |
494 | break; | |
bd4fb654 TM |
495 | default: |
496 | return -EINVAL; | |
2b0c28d7 MP |
497 | } |
498 | ||
499 | return 0; | |
500 | } | |
501 | ||
502 | /** | |
f8f06269 | 503 | * fsl_add_outb_message - Add message to the MPC85xx outbound message queue |
2b0c28d7 MP |
504 | * @mport: Master port with outbound message queue |
505 | * @rdev: Target of outbound message | |
506 | * @mbox: Outbound mailbox | |
507 | * @buffer: Message to add to outbound queue | |
508 | * @len: Length of message | |
509 | * | |
510 | * Adds the @buffer message to the MPC85xx outbound message queue. Returns | |
511 | * %0 on success or %-EINVAL on failure. | |
512 | */ | |
f8f06269 AB |
513 | static int |
514 | fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, | |
2b0c28d7 MP |
515 | void *buffer, size_t len) |
516 | { | |
ad1e9380 | 517 | struct rio_priv *priv = mport->priv; |
2b0c28d7 | 518 | u32 omr; |
ad1e9380 ZW |
519 | struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt |
520 | + priv->msg_tx_ring.tx_slot; | |
2b0c28d7 MP |
521 | int ret = 0; |
522 | ||
f8f06269 AB |
523 | pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \ |
524 | "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len); | |
2b0c28d7 MP |
525 | |
526 | if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { | |
527 | ret = -EINVAL; | |
528 | goto out; | |
529 | } | |
530 | ||
531 | /* Copy and clear rest of buffer */ | |
ad1e9380 ZW |
532 | memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer, |
533 | len); | |
2b0c28d7 | 534 | if (len < (RIO_MAX_MSG_SIZE - 4)) |
ad1e9380 ZW |
535 | memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot] |
536 | + len, 0, RIO_MAX_MSG_SIZE - len); | |
2b0c28d7 | 537 | |
61b26917 ZW |
538 | switch (mport->phy_type) { |
539 | case RIO_PHY_PARALLEL: | |
540 | /* Set mbox field for message */ | |
541 | desc->dport = mbox & 0x3; | |
2b0c28d7 | 542 | |
61b26917 ZW |
543 | /* Enable EOMI interrupt, set priority, and set destid */ |
544 | desc->dattr = 0x28000000 | (rdev->destid << 2); | |
545 | break; | |
546 | case RIO_PHY_SERIAL: | |
547 | /* Set mbox field for message, and set destid */ | |
548 | desc->dport = (rdev->destid << 16) | (mbox & 0x3); | |
549 | ||
550 | /* Enable EOMI interrupt and priority */ | |
551 | desc->dattr = 0x28000000; | |
552 | break; | |
553 | } | |
2b0c28d7 MP |
554 | |
555 | /* Set transfer size aligned to next power of 2 (in double words) */ | |
556 | desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); | |
557 | ||
558 | /* Set snooping and source buffer address */ | |
ad1e9380 ZW |
559 | desc->saddr = 0x00000004 |
560 | | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot]; | |
2b0c28d7 MP |
561 | |
562 | /* Increment enqueue pointer */ | |
ad1e9380 ZW |
563 | omr = in_be32(&priv->msg_regs->omr); |
564 | out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI); | |
2b0c28d7 MP |
565 | |
566 | /* Go to next descriptor */ | |
ad1e9380 ZW |
567 | if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size) |
568 | priv->msg_tx_ring.tx_slot = 0; | |
2b0c28d7 MP |
569 | |
570 | out: | |
571 | return ret; | |
572 | } | |
573 | ||
2b0c28d7 | 574 | /** |
d02443a6 | 575 | * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler |
2b0c28d7 MP |
576 | * @irq: Linux interrupt number |
577 | * @dev_instance: Pointer to interrupt-specific data | |
2b0c28d7 MP |
578 | * |
579 | * Handles outbound message interrupts. Executes a register outbound | |
a8de5ce9 | 580 | * mailbox event handler and acks the interrupt occurrence. |
2b0c28d7 MP |
581 | */ |
582 | static irqreturn_t | |
d02443a6 | 583 | fsl_rio_tx_handler(int irq, void *dev_instance) |
2b0c28d7 MP |
584 | { |
585 | int osr; | |
586 | struct rio_mport *port = (struct rio_mport *)dev_instance; | |
ad1e9380 | 587 | struct rio_priv *priv = port->priv; |
2b0c28d7 | 588 | |
ad1e9380 | 589 | osr = in_be32(&priv->msg_regs->osr); |
2b0c28d7 MP |
590 | |
591 | if (osr & RIO_MSG_OSR_TE) { | |
592 | pr_info("RIO: outbound message transmission error\n"); | |
ad1e9380 | 593 | out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE); |
2b0c28d7 MP |
594 | goto out; |
595 | } | |
596 | ||
597 | if (osr & RIO_MSG_OSR_QOI) { | |
598 | pr_info("RIO: outbound message queue overflow\n"); | |
ad1e9380 | 599 | out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI); |
2b0c28d7 MP |
600 | goto out; |
601 | } | |
602 | ||
603 | if (osr & RIO_MSG_OSR_EOMI) { | |
ad1e9380 ZW |
604 | u32 dqp = in_be32(&priv->msg_regs->odqdpar); |
605 | int slot = (dqp - priv->msg_tx_ring.phys) >> 5; | |
606 | port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1, | |
607 | slot); | |
2b0c28d7 MP |
608 | |
609 | /* Ack the end-of-message interrupt */ | |
ad1e9380 | 610 | out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI); |
2b0c28d7 MP |
611 | } |
612 | ||
613 | out: | |
614 | return IRQ_HANDLED; | |
615 | } | |
616 | ||
617 | /** | |
f8f06269 | 618 | * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox |
2b0c28d7 | 619 | * @mport: Master port implementing the outbound message unit |
6978bbc0 | 620 | * @dev_id: Device specific pointer to pass on event |
2b0c28d7 MP |
621 | * @mbox: Mailbox to open |
622 | * @entries: Number of entries in the outbound mailbox ring | |
623 | * | |
624 | * Initializes buffer ring, request the outbound message interrupt, | |
625 | * and enables the outbound message unit. Returns %0 on success and | |
626 | * %-EINVAL or %-ENOMEM on failure. | |
627 | */ | |
f8f06269 AB |
628 | static int |
629 | fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) | |
2b0c28d7 MP |
630 | { |
631 | int i, j, rc = 0; | |
ad1e9380 | 632 | struct rio_priv *priv = mport->priv; |
2b0c28d7 MP |
633 | |
634 | if ((entries < RIO_MIN_TX_RING_SIZE) || | |
635 | (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) { | |
636 | rc = -EINVAL; | |
637 | goto out; | |
638 | } | |
639 | ||
640 | /* Initialize shadow copy ring */ | |
ad1e9380 ZW |
641 | priv->msg_tx_ring.dev_id = dev_id; |
642 | priv->msg_tx_ring.size = entries; | |
643 | ||
644 | for (i = 0; i < priv->msg_tx_ring.size; i++) { | |
645 | priv->msg_tx_ring.virt_buffer[i] = | |
0dbbbf1a | 646 | dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, |
ad1e9380 ZW |
647 | &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL); |
648 | if (!priv->msg_tx_ring.virt_buffer[i]) { | |
2b0c28d7 | 649 | rc = -ENOMEM; |
ad1e9380 ZW |
650 | for (j = 0; j < priv->msg_tx_ring.size; j++) |
651 | if (priv->msg_tx_ring.virt_buffer[j]) | |
0dbbbf1a | 652 | dma_free_coherent(priv->dev, |
ad1e9380 ZW |
653 | RIO_MSG_BUFFER_SIZE, |
654 | priv->msg_tx_ring. | |
655 | virt_buffer[j], | |
656 | priv->msg_tx_ring. | |
657 | phys_buffer[j]); | |
2b0c28d7 MP |
658 | goto out; |
659 | } | |
660 | } | |
661 | ||
662 | /* Initialize outbound message descriptor ring */ | |
0dbbbf1a | 663 | priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev, |
ad1e9380 ZW |
664 | priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, |
665 | &priv->msg_tx_ring.phys, GFP_KERNEL); | |
666 | if (!priv->msg_tx_ring.virt) { | |
2b0c28d7 MP |
667 | rc = -ENOMEM; |
668 | goto out_dma; | |
669 | } | |
ad1e9380 ZW |
670 | memset(priv->msg_tx_ring.virt, 0, |
671 | priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE); | |
672 | priv->msg_tx_ring.tx_slot = 0; | |
2b0c28d7 MP |
673 | |
674 | /* Point dequeue/enqueue pointers at first entry in ring */ | |
ad1e9380 ZW |
675 | out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys); |
676 | out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys); | |
2b0c28d7 MP |
677 | |
678 | /* Configure for snooping */ | |
ad1e9380 | 679 | out_be32(&priv->msg_regs->osar, 0x00000004); |
2b0c28d7 MP |
680 | |
681 | /* Clear interrupt status */ | |
ad1e9380 | 682 | out_be32(&priv->msg_regs->osr, 0x000000b3); |
2b0c28d7 MP |
683 | |
684 | /* Hook up outbound message handler */ | |
ad1e9380 ZW |
685 | rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0, |
686 | "msg_tx", (void *)mport); | |
687 | if (rc < 0) | |
2b0c28d7 MP |
688 | goto out_irq; |
689 | ||
690 | /* | |
691 | * Configure outbound message unit | |
692 | * Snooping | |
693 | * Interrupts (all enabled, except QEIE) | |
694 | * Chaining mode | |
695 | * Disable | |
696 | */ | |
ad1e9380 | 697 | out_be32(&priv->msg_regs->omr, 0x00100220); |
2b0c28d7 MP |
698 | |
699 | /* Set number of entries */ | |
ad1e9380 ZW |
700 | out_be32(&priv->msg_regs->omr, |
701 | in_be32(&priv->msg_regs->omr) | | |
2b0c28d7 MP |
702 | ((get_bitmask_order(entries) - 2) << 12)); |
703 | ||
704 | /* Now enable the unit */ | |
ad1e9380 | 705 | out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1); |
2b0c28d7 MP |
706 | |
707 | out: | |
708 | return rc; | |
709 | ||
710 | out_irq: | |
0dbbbf1a AV |
711 | dma_free_coherent(priv->dev, |
712 | priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, | |
ad1e9380 | 713 | priv->msg_tx_ring.virt, priv->msg_tx_ring.phys); |
2b0c28d7 MP |
714 | |
715 | out_dma: | |
ad1e9380 | 716 | for (i = 0; i < priv->msg_tx_ring.size; i++) |
0dbbbf1a | 717 | dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, |
ad1e9380 ZW |
718 | priv->msg_tx_ring.virt_buffer[i], |
719 | priv->msg_tx_ring.phys_buffer[i]); | |
2b0c28d7 MP |
720 | |
721 | return rc; | |
722 | } | |
723 | ||
724 | /** | |
f8f06269 | 725 | * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox |
2b0c28d7 MP |
726 | * @mport: Master port implementing the outbound message unit |
727 | * @mbox: Mailbox to close | |
728 | * | |
729 | * Disables the outbound message unit, free all buffers, and | |
730 | * frees the outbound message interrupt. | |
731 | */ | |
f8f06269 | 732 | static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox) |
2b0c28d7 | 733 | { |
ad1e9380 | 734 | struct rio_priv *priv = mport->priv; |
2b0c28d7 | 735 | /* Disable inbound message unit */ |
ad1e9380 | 736 | out_be32(&priv->msg_regs->omr, 0); |
2b0c28d7 MP |
737 | |
738 | /* Free ring */ | |
0dbbbf1a AV |
739 | dma_free_coherent(priv->dev, |
740 | priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, | |
ad1e9380 | 741 | priv->msg_tx_ring.virt, priv->msg_tx_ring.phys); |
2b0c28d7 MP |
742 | |
743 | /* Free interrupt */ | |
ad1e9380 | 744 | free_irq(IRQ_RIO_TX(mport), (void *)mport); |
2b0c28d7 MP |
745 | } |
746 | ||
747 | /** | |
d02443a6 | 748 | * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler |
2b0c28d7 MP |
749 | * @irq: Linux interrupt number |
750 | * @dev_instance: Pointer to interrupt-specific data | |
2b0c28d7 MP |
751 | * |
752 | * Handles inbound message interrupts. Executes a registered inbound | |
a8de5ce9 | 753 | * mailbox event handler and acks the interrupt occurrence. |
2b0c28d7 MP |
754 | */ |
755 | static irqreturn_t | |
d02443a6 | 756 | fsl_rio_rx_handler(int irq, void *dev_instance) |
2b0c28d7 MP |
757 | { |
758 | int isr; | |
759 | struct rio_mport *port = (struct rio_mport *)dev_instance; | |
ad1e9380 | 760 | struct rio_priv *priv = port->priv; |
2b0c28d7 | 761 | |
ad1e9380 | 762 | isr = in_be32(&priv->msg_regs->isr); |
2b0c28d7 MP |
763 | |
764 | if (isr & RIO_MSG_ISR_TE) { | |
765 | pr_info("RIO: inbound message reception error\n"); | |
ad1e9380 | 766 | out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE); |
2b0c28d7 MP |
767 | goto out; |
768 | } | |
769 | ||
770 | /* XXX Need to check/dispatch until queue empty */ | |
771 | if (isr & RIO_MSG_ISR_DIQI) { | |
772 | /* | |
773 | * We implement *only* mailbox 0, but can receive messages | |
774 | * for any mailbox/letter to that mailbox destination. So, | |
775 | * make the callback with an unknown/invalid mailbox number | |
776 | * argument. | |
777 | */ | |
ad1e9380 | 778 | port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1); |
2b0c28d7 MP |
779 | |
780 | /* Ack the queueing interrupt */ | |
ad1e9380 | 781 | out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI); |
2b0c28d7 MP |
782 | } |
783 | ||
784 | out: | |
785 | return IRQ_HANDLED; | |
786 | } | |
787 | ||
788 | /** | |
f8f06269 | 789 | * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox |
2b0c28d7 | 790 | * @mport: Master port implementing the inbound message unit |
6978bbc0 | 791 | * @dev_id: Device specific pointer to pass on event |
2b0c28d7 MP |
792 | * @mbox: Mailbox to open |
793 | * @entries: Number of entries in the inbound mailbox ring | |
794 | * | |
795 | * Initializes buffer ring, request the inbound message interrupt, | |
796 | * and enables the inbound message unit. Returns %0 on success | |
797 | * and %-EINVAL or %-ENOMEM on failure. | |
798 | */ | |
f8f06269 AB |
799 | static int |
800 | fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) | |
2b0c28d7 MP |
801 | { |
802 | int i, rc = 0; | |
ad1e9380 | 803 | struct rio_priv *priv = mport->priv; |
2b0c28d7 MP |
804 | |
805 | if ((entries < RIO_MIN_RX_RING_SIZE) || | |
806 | (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) { | |
807 | rc = -EINVAL; | |
808 | goto out; | |
809 | } | |
810 | ||
811 | /* Initialize client buffer ring */ | |
ad1e9380 ZW |
812 | priv->msg_rx_ring.dev_id = dev_id; |
813 | priv->msg_rx_ring.size = entries; | |
814 | priv->msg_rx_ring.rx_slot = 0; | |
815 | for (i = 0; i < priv->msg_rx_ring.size; i++) | |
816 | priv->msg_rx_ring.virt_buffer[i] = NULL; | |
2b0c28d7 MP |
817 | |
818 | /* Initialize inbound message ring */ | |
0dbbbf1a | 819 | priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev, |
ad1e9380 ZW |
820 | priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE, |
821 | &priv->msg_rx_ring.phys, GFP_KERNEL); | |
822 | if (!priv->msg_rx_ring.virt) { | |
2b0c28d7 MP |
823 | rc = -ENOMEM; |
824 | goto out; | |
825 | } | |
826 | ||
827 | /* Point dequeue/enqueue pointers at first entry in ring */ | |
ad1e9380 ZW |
828 | out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys); |
829 | out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys); | |
2b0c28d7 MP |
830 | |
831 | /* Clear interrupt status */ | |
ad1e9380 | 832 | out_be32(&priv->msg_regs->isr, 0x00000091); |
2b0c28d7 MP |
833 | |
834 | /* Hook up inbound message handler */ | |
ad1e9380 ZW |
835 | rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0, |
836 | "msg_rx", (void *)mport); | |
837 | if (rc < 0) { | |
0dbbbf1a | 838 | dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, |
ad1e9380 ZW |
839 | priv->msg_tx_ring.virt_buffer[i], |
840 | priv->msg_tx_ring.phys_buffer[i]); | |
2b0c28d7 MP |
841 | goto out; |
842 | } | |
843 | ||
844 | /* | |
845 | * Configure inbound message unit: | |
846 | * Snooping | |
847 | * 4KB max message size | |
848 | * Unmask all interrupt sources | |
849 | * Disable | |
850 | */ | |
ad1e9380 | 851 | out_be32(&priv->msg_regs->imr, 0x001b0060); |
2b0c28d7 MP |
852 | |
853 | /* Set number of queue entries */ | |
ad1e9380 | 854 | setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); |
2b0c28d7 MP |
855 | |
856 | /* Now enable the unit */ | |
ad1e9380 | 857 | setbits32(&priv->msg_regs->imr, 0x1); |
2b0c28d7 MP |
858 | |
859 | out: | |
860 | return rc; | |
861 | } | |
862 | ||
863 | /** | |
f8f06269 | 864 | * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox |
2b0c28d7 MP |
865 | * @mport: Master port implementing the inbound message unit |
866 | * @mbox: Mailbox to close | |
867 | * | |
868 | * Disables the inbound message unit, free all buffers, and | |
869 | * frees the inbound message interrupt. | |
870 | */ | |
f8f06269 | 871 | static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox) |
2b0c28d7 | 872 | { |
ad1e9380 | 873 | struct rio_priv *priv = mport->priv; |
2b0c28d7 | 874 | /* Disable inbound message unit */ |
ad1e9380 | 875 | out_be32(&priv->msg_regs->imr, 0); |
2b0c28d7 MP |
876 | |
877 | /* Free ring */ | |
0dbbbf1a | 878 | dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE, |
ad1e9380 | 879 | priv->msg_rx_ring.virt, priv->msg_rx_ring.phys); |
2b0c28d7 MP |
880 | |
881 | /* Free interrupt */ | |
ad1e9380 | 882 | free_irq(IRQ_RIO_RX(mport), (void *)mport); |
2b0c28d7 MP |
883 | } |
884 | ||
885 | /** | |
f8f06269 | 886 | * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue |
2b0c28d7 MP |
887 | * @mport: Master port implementing the inbound message unit |
888 | * @mbox: Inbound mailbox number | |
889 | * @buf: Buffer to add to inbound queue | |
890 | * | |
891 | * Adds the @buf buffer to the MPC85xx inbound message queue. Returns | |
892 | * %0 on success or %-EINVAL on failure. | |
893 | */ | |
f8f06269 | 894 | static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) |
2b0c28d7 MP |
895 | { |
896 | int rc = 0; | |
ad1e9380 | 897 | struct rio_priv *priv = mport->priv; |
2b0c28d7 | 898 | |
f8f06269 | 899 | pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", |
ad1e9380 | 900 | priv->msg_rx_ring.rx_slot); |
2b0c28d7 | 901 | |
ad1e9380 | 902 | if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) { |
2b0c28d7 MP |
903 | printk(KERN_ERR |
904 | "RIO: error adding inbound buffer %d, buffer exists\n", | |
ad1e9380 | 905 | priv->msg_rx_ring.rx_slot); |
2b0c28d7 MP |
906 | rc = -EINVAL; |
907 | goto out; | |
908 | } | |
909 | ||
ad1e9380 ZW |
910 | priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf; |
911 | if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size) | |
912 | priv->msg_rx_ring.rx_slot = 0; | |
2b0c28d7 MP |
913 | |
914 | out: | |
915 | return rc; | |
916 | } | |
917 | ||
2b0c28d7 | 918 | /** |
f8f06269 | 919 | * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit |
2b0c28d7 MP |
920 | * @mport: Master port implementing the inbound message unit |
921 | * @mbox: Inbound mailbox number | |
922 | * | |
923 | * Gets the next available inbound message from the inbound message queue. | |
924 | * A pointer to the message is returned on success or NULL on failure. | |
925 | */ | |
f8f06269 | 926 | static void *fsl_get_inb_message(struct rio_mport *mport, int mbox) |
2b0c28d7 | 927 | { |
ad1e9380 | 928 | struct rio_priv *priv = mport->priv; |
2b0c28d7 MP |
929 | u32 phys_buf, virt_buf; |
930 | void *buf = NULL; | |
931 | int buf_idx; | |
932 | ||
ad1e9380 | 933 | phys_buf = in_be32(&priv->msg_regs->ifqdpar); |
2b0c28d7 MP |
934 | |
935 | /* If no more messages, then bail out */ | |
ad1e9380 | 936 | if (phys_buf == in_be32(&priv->msg_regs->ifqepar)) |
2b0c28d7 MP |
937 | goto out2; |
938 | ||
ad1e9380 ZW |
939 | virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf |
940 | - priv->msg_rx_ring.phys); | |
941 | buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; | |
942 | buf = priv->msg_rx_ring.virt_buffer[buf_idx]; | |
2b0c28d7 MP |
943 | |
944 | if (!buf) { | |
945 | printk(KERN_ERR | |
946 | "RIO: inbound message copy failed, no buffers\n"); | |
947 | goto out1; | |
948 | } | |
949 | ||
950 | /* Copy max message size, caller is expected to allocate that big */ | |
951 | memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE); | |
952 | ||
953 | /* Clear the available buffer */ | |
ad1e9380 | 954 | priv->msg_rx_ring.virt_buffer[buf_idx] = NULL; |
2b0c28d7 MP |
955 | |
956 | out1: | |
ad1e9380 | 957 | setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI); |
2b0c28d7 MP |
958 | |
959 | out2: | |
960 | return buf; | |
961 | } | |
962 | ||
2b0c28d7 | 963 | /** |
d02443a6 | 964 | * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler |
2b0c28d7 MP |
965 | * @irq: Linux interrupt number |
966 | * @dev_instance: Pointer to interrupt-specific data | |
2b0c28d7 MP |
967 | * |
968 | * Handles doorbell interrupts. Parses a list of registered | |
969 | * doorbell event handlers and executes a matching event handler. | |
970 | */ | |
971 | static irqreturn_t | |
d02443a6 | 972 | fsl_rio_dbell_handler(int irq, void *dev_instance) |
2b0c28d7 MP |
973 | { |
974 | int dsr; | |
975 | struct rio_mport *port = (struct rio_mport *)dev_instance; | |
ad1e9380 | 976 | struct rio_priv *priv = port->priv; |
2b0c28d7 | 977 | |
ad1e9380 | 978 | dsr = in_be32(&priv->msg_regs->dsr); |
2b0c28d7 MP |
979 | |
980 | if (dsr & DOORBELL_DSR_TE) { | |
981 | pr_info("RIO: doorbell reception error\n"); | |
ad1e9380 | 982 | out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE); |
2b0c28d7 MP |
983 | goto out; |
984 | } | |
985 | ||
986 | if (dsr & DOORBELL_DSR_QFI) { | |
987 | pr_info("RIO: doorbell queue full\n"); | |
ad1e9380 | 988 | out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI); |
2b0c28d7 MP |
989 | } |
990 | ||
991 | /* XXX Need to check/dispatch until queue empty */ | |
992 | if (dsr & DOORBELL_DSR_DIQI) { | |
993 | u32 dmsg = | |
ad1e9380 ZW |
994 | (u32) priv->dbell_ring.virt + |
995 | (in_be32(&priv->msg_regs->dqdpar) & 0xfff); | |
2b0c28d7 MP |
996 | struct rio_dbell *dbell; |
997 | int found = 0; | |
998 | ||
999 | pr_debug | |
1000 | ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n", | |
1001 | DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); | |
1002 | ||
1003 | list_for_each_entry(dbell, &port->dbells, node) { | |
1004 | if ((dbell->res->start <= DBELL_INF(dmsg)) && | |
1005 | (dbell->res->end >= DBELL_INF(dmsg))) { | |
1006 | found = 1; | |
1007 | break; | |
1008 | } | |
1009 | } | |
1010 | if (found) { | |
6978bbc0 | 1011 | dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg), |
2b0c28d7 MP |
1012 | DBELL_INF(dmsg)); |
1013 | } else { | |
1014 | pr_debug | |
1015 | ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n", | |
1016 | DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); | |
1017 | } | |
ad1e9380 ZW |
1018 | setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI); |
1019 | out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI); | |
2b0c28d7 MP |
1020 | } |
1021 | ||
1022 | out: | |
1023 | return IRQ_HANDLED; | |
1024 | } | |
1025 | ||
1026 | /** | |
d02443a6 | 1027 | * fsl_rio_doorbell_init - MPC85xx doorbell interface init |
2b0c28d7 MP |
1028 | * @mport: Master port implementing the inbound doorbell unit |
1029 | * | |
1030 | * Initializes doorbell unit hardware and inbound DMA buffer | |
d02443a6 | 1031 | * ring. Called from fsl_rio_setup(). Returns %0 on success |
2b0c28d7 MP |
1032 | * or %-ENOMEM on failure. |
1033 | */ | |
d02443a6 | 1034 | static int fsl_rio_doorbell_init(struct rio_mport *mport) |
2b0c28d7 | 1035 | { |
ad1e9380 | 1036 | struct rio_priv *priv = mport->priv; |
2b0c28d7 MP |
1037 | int rc = 0; |
1038 | ||
1039 | /* Map outbound doorbell window immediately after maintenance window */ | |
ad1e9380 ZW |
1040 | priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE, |
1041 | RIO_DBELL_WIN_SIZE); | |
1042 | if (!priv->dbell_win) { | |
2b0c28d7 MP |
1043 | printk(KERN_ERR |
1044 | "RIO: unable to map outbound doorbell window\n"); | |
1045 | rc = -ENOMEM; | |
1046 | goto out; | |
1047 | } | |
1048 | ||
1049 | /* Initialize inbound doorbells */ | |
0dbbbf1a | 1050 | priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 * |
ad1e9380 ZW |
1051 | DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL); |
1052 | if (!priv->dbell_ring.virt) { | |
2b0c28d7 MP |
1053 | printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n"); |
1054 | rc = -ENOMEM; | |
ad1e9380 | 1055 | iounmap(priv->dbell_win); |
2b0c28d7 MP |
1056 | goto out; |
1057 | } | |
1058 | ||
1059 | /* Point dequeue/enqueue pointers at first entry in ring */ | |
ad1e9380 ZW |
1060 | out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys); |
1061 | out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys); | |
2b0c28d7 MP |
1062 | |
1063 | /* Clear interrupt status */ | |
ad1e9380 | 1064 | out_be32(&priv->msg_regs->dsr, 0x00000091); |
2b0c28d7 MP |
1065 | |
1066 | /* Hook up doorbell handler */ | |
ad1e9380 ZW |
1067 | rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0, |
1068 | "dbell_rx", (void *)mport); | |
1069 | if (rc < 0) { | |
1070 | iounmap(priv->dbell_win); | |
0dbbbf1a | 1071 | dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE, |
ad1e9380 | 1072 | priv->dbell_ring.virt, priv->dbell_ring.phys); |
2b0c28d7 MP |
1073 | printk(KERN_ERR |
1074 | "MPC85xx RIO: unable to request inbound doorbell irq"); | |
1075 | goto out; | |
1076 | } | |
1077 | ||
1078 | /* Configure doorbells for snooping, 512 entries, and enable */ | |
ad1e9380 | 1079 | out_be32(&priv->msg_regs->dmr, 0x00108161); |
2b0c28d7 MP |
1080 | |
1081 | out: | |
1082 | return rc; | |
1083 | } | |
1084 | ||
6ff31453 SX |
1085 | static void port_error_handler(struct rio_mport *port, int offset) |
1086 | { | |
1087 | /*XXX: Error recovery is not implemented, we just clear errors */ | |
1088 | out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); | |
1089 | ||
1090 | if (offset == 0) { | |
1091 | out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0); | |
1092 | out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), 0); | |
1093 | out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR); | |
1094 | } else { | |
1095 | out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0); | |
1096 | out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), 0); | |
1097 | out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR); | |
1098 | } | |
1099 | } | |
1100 | ||
1101 | static void msg_unit_error_handler(struct rio_mport *port) | |
1102 | { | |
1103 | struct rio_priv *priv = port->priv; | |
1104 | ||
1105 | /*XXX: Error recovery is not implemented, we just clear errors */ | |
1106 | out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); | |
1107 | ||
1108 | out_be32((u32 *)(rio_regs_win + RIO_IM0SR), IMSR_CLEAR); | |
1109 | out_be32((u32 *)(rio_regs_win + RIO_IM1SR), IMSR_CLEAR); | |
1110 | out_be32((u32 *)(rio_regs_win + RIO_OM0SR), OMSR_CLEAR); | |
1111 | out_be32((u32 *)(rio_regs_win + RIO_OM1SR), OMSR_CLEAR); | |
1112 | ||
1113 | out_be32(&priv->msg_regs->odsr, ODSR_CLEAR); | |
1114 | out_be32(&priv->msg_regs->dsr, IDSR_CLEAR); | |
1115 | ||
1116 | out_be32(&priv->msg_regs->pwsr, IPWSR_CLEAR); | |
1117 | } | |
1118 | ||
5b2074ae AB |
1119 | /** |
1120 | * fsl_rio_port_write_handler - MPC85xx port write interrupt handler | |
1121 | * @irq: Linux interrupt number | |
1122 | * @dev_instance: Pointer to interrupt-specific data | |
1123 | * | |
1124 | * Handles port write interrupts. Parses a list of registered | |
1125 | * port write event handlers and executes a matching event handler. | |
1126 | */ | |
1127 | static irqreturn_t | |
1128 | fsl_rio_port_write_handler(int irq, void *dev_instance) | |
1129 | { | |
1130 | u32 ipwmr, ipwsr; | |
1131 | struct rio_mport *port = (struct rio_mport *)dev_instance; | |
1132 | struct rio_priv *priv = port->priv; | |
1133 | u32 epwisr, tmp; | |
1134 | ||
5b2074ae | 1135 | epwisr = in_be32(priv->regs_win + RIO_EPWISR); |
93e2cbd2 AB |
1136 | if (!(epwisr & RIO_EPWISR_PW)) |
1137 | goto pw_done; | |
5b2074ae | 1138 | |
93e2cbd2 AB |
1139 | ipwmr = in_be32(&priv->msg_regs->pwmr); |
1140 | ipwsr = in_be32(&priv->msg_regs->pwsr); | |
5b2074ae AB |
1141 | |
1142 | #ifdef DEBUG_PW | |
1143 | pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr); | |
1144 | if (ipwsr & RIO_IPWSR_QF) | |
1145 | pr_debug(" QF"); | |
1146 | if (ipwsr & RIO_IPWSR_TE) | |
1147 | pr_debug(" TE"); | |
1148 | if (ipwsr & RIO_IPWSR_QFI) | |
1149 | pr_debug(" QFI"); | |
1150 | if (ipwsr & RIO_IPWSR_PWD) | |
1151 | pr_debug(" PWD"); | |
1152 | if (ipwsr & RIO_IPWSR_PWB) | |
1153 | pr_debug(" PWB"); | |
1154 | pr_debug(" )\n"); | |
1155 | #endif | |
5b2074ae AB |
1156 | /* Schedule deferred processing if PW was received */ |
1157 | if (ipwsr & RIO_IPWSR_QFI) { | |
1158 | /* Save PW message (if there is room in FIFO), | |
1159 | * otherwise discard it. | |
1160 | */ | |
1161 | if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) { | |
1162 | priv->port_write_msg.msg_count++; | |
1163 | kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt, | |
1164 | RIO_PW_MSG_SIZE); | |
1165 | } else { | |
1166 | priv->port_write_msg.discard_count++; | |
93e2cbd2 | 1167 | pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n", |
5b2074ae AB |
1168 | priv->port_write_msg.discard_count); |
1169 | } | |
93e2cbd2 AB |
1170 | /* Clear interrupt and issue Clear Queue command. This allows |
1171 | * another port-write to be received. | |
1172 | */ | |
1173 | out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_QFI); | |
1174 | out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ); | |
1175 | ||
5b2074ae AB |
1176 | schedule_work(&priv->pw_work); |
1177 | } | |
1178 | ||
93e2cbd2 AB |
1179 | if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) { |
1180 | priv->port_write_msg.err_count++; | |
1181 | pr_debug("RIO: Port-Write Transaction Err (%d)\n", | |
1182 | priv->port_write_msg.err_count); | |
1183 | /* Clear Transaction Error: port-write controller should be | |
1184 | * disabled when clearing this error | |
1185 | */ | |
1186 | out_be32(&priv->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE); | |
1187 | out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_TE); | |
1188 | out_be32(&priv->msg_regs->pwmr, ipwmr); | |
1189 | } | |
1190 | ||
1191 | if (ipwsr & RIO_IPWSR_PWD) { | |
1192 | priv->port_write_msg.discard_count++; | |
1193 | pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n", | |
1194 | priv->port_write_msg.discard_count); | |
1195 | out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_PWD); | |
1196 | } | |
1197 | ||
1198 | pw_done: | |
6ff31453 SX |
1199 | if (epwisr & RIO_EPWISR_PINT1) { |
1200 | tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); | |
1201 | pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); | |
1202 | port_error_handler(port, 0); | |
1203 | } | |
1204 | ||
1205 | if (epwisr & RIO_EPWISR_PINT2) { | |
1206 | tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); | |
1207 | pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); | |
1208 | port_error_handler(port, 1); | |
1209 | } | |
1210 | ||
1211 | if (epwisr & RIO_EPWISR_MU) { | |
93e2cbd2 AB |
1212 | tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); |
1213 | pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); | |
6ff31453 | 1214 | msg_unit_error_handler(port); |
93e2cbd2 | 1215 | } |
5b2074ae AB |
1216 | |
1217 | return IRQ_HANDLED; | |
1218 | } | |
1219 | ||
1220 | static void fsl_pw_dpc(struct work_struct *work) | |
1221 | { | |
1222 | struct rio_priv *priv = container_of(work, struct rio_priv, pw_work); | |
1223 | unsigned long flags; | |
1224 | u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)]; | |
1225 | ||
1226 | /* | |
1227 | * Process port-write messages | |
1228 | */ | |
1229 | spin_lock_irqsave(&priv->pw_fifo_lock, flags); | |
1230 | while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer, | |
1231 | RIO_PW_MSG_SIZE)) { | |
1232 | /* Process one message */ | |
1233 | spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); | |
1234 | #ifdef DEBUG_PW | |
1235 | { | |
1236 | u32 i; | |
1237 | pr_debug("%s : Port-Write Message:", __func__); | |
1238 | for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) { | |
1239 | if ((i%4) == 0) | |
1240 | pr_debug("\n0x%02x: 0x%08x", i*4, | |
1241 | msg_buffer[i]); | |
1242 | else | |
1243 | pr_debug(" 0x%08x", msg_buffer[i]); | |
1244 | } | |
1245 | pr_debug("\n"); | |
1246 | } | |
1247 | #endif | |
1248 | /* Pass the port-write message to RIO core for processing */ | |
1249 | rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer); | |
1250 | spin_lock_irqsave(&priv->pw_fifo_lock, flags); | |
1251 | } | |
1252 | spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); | |
1253 | } | |
1254 | ||
1255 | /** | |
1256 | * fsl_rio_pw_enable - enable/disable port-write interface init | |
1257 | * @mport: Master port implementing the port write unit | |
1258 | * @enable: 1=enable; 0=disable port-write message handling | |
1259 | */ | |
1260 | static int fsl_rio_pw_enable(struct rio_mport *mport, int enable) | |
1261 | { | |
1262 | struct rio_priv *priv = mport->priv; | |
1263 | u32 rval; | |
1264 | ||
1265 | rval = in_be32(&priv->msg_regs->pwmr); | |
1266 | ||
1267 | if (enable) | |
1268 | rval |= RIO_IPWMR_PWE; | |
1269 | else | |
1270 | rval &= ~RIO_IPWMR_PWE; | |
1271 | ||
1272 | out_be32(&priv->msg_regs->pwmr, rval); | |
1273 | ||
1274 | return 0; | |
1275 | } | |
1276 | ||
1277 | /** | |
1278 | * fsl_rio_port_write_init - MPC85xx port write interface init | |
1279 | * @mport: Master port implementing the port write unit | |
1280 | * | |
1281 | * Initializes port write unit hardware and DMA buffer | |
1282 | * ring. Called from fsl_rio_setup(). Returns %0 on success | |
1283 | * or %-ENOMEM on failure. | |
1284 | */ | |
1285 | static int fsl_rio_port_write_init(struct rio_mport *mport) | |
1286 | { | |
1287 | struct rio_priv *priv = mport->priv; | |
1288 | int rc = 0; | |
1289 | ||
1290 | /* Following configurations require a disabled port write controller */ | |
1291 | out_be32(&priv->msg_regs->pwmr, | |
1292 | in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE); | |
1293 | ||
1294 | /* Initialize port write */ | |
1295 | priv->port_write_msg.virt = dma_alloc_coherent(priv->dev, | |
1296 | RIO_PW_MSG_SIZE, | |
1297 | &priv->port_write_msg.phys, GFP_KERNEL); | |
1298 | if (!priv->port_write_msg.virt) { | |
1299 | pr_err("RIO: unable allocate port write queue\n"); | |
1300 | return -ENOMEM; | |
1301 | } | |
1302 | ||
1303 | priv->port_write_msg.err_count = 0; | |
1304 | priv->port_write_msg.discard_count = 0; | |
1305 | ||
1306 | /* Point dequeue/enqueue pointers at first entry */ | |
1307 | out_be32(&priv->msg_regs->epwqbar, 0); | |
1308 | out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys); | |
1309 | ||
1310 | pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n", | |
1311 | in_be32(&priv->msg_regs->epwqbar), | |
1312 | in_be32(&priv->msg_regs->pwqbar)); | |
1313 | ||
1314 | /* Clear interrupt status IPWSR */ | |
1315 | out_be32(&priv->msg_regs->pwsr, | |
1316 | (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD)); | |
1317 | ||
1318 | /* Configure port write contoller for snooping enable all reporting, | |
1319 | clear queue full */ | |
1320 | out_be32(&priv->msg_regs->pwmr, | |
1321 | RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ); | |
1322 | ||
1323 | ||
1324 | /* Hook up port-write handler */ | |
6ff31453 SX |
1325 | rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, |
1326 | IRQF_SHARED, "port-write", (void *)mport); | |
5b2074ae AB |
1327 | if (rc < 0) { |
1328 | pr_err("MPC85xx RIO: unable to request inbound doorbell irq"); | |
1329 | goto err_out; | |
1330 | } | |
6ff31453 SX |
1331 | /* Enable Error Interrupt */ |
1332 | out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL); | |
5b2074ae AB |
1333 | |
1334 | INIT_WORK(&priv->pw_work, fsl_pw_dpc); | |
1335 | spin_lock_init(&priv->pw_fifo_lock); | |
1336 | if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) { | |
1337 | pr_err("FIFO allocation failed\n"); | |
1338 | rc = -ENOMEM; | |
1339 | goto err_out_irq; | |
1340 | } | |
1341 | ||
1342 | pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n", | |
1343 | in_be32(&priv->msg_regs->pwmr), | |
1344 | in_be32(&priv->msg_regs->pwsr)); | |
1345 | ||
1346 | return rc; | |
1347 | ||
1348 | err_out_irq: | |
1349 | free_irq(IRQ_RIO_PW(mport), (void *)mport); | |
1350 | err_out: | |
1351 | dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE, | |
1352 | priv->port_write_msg.virt, | |
1353 | priv->port_write_msg.phys); | |
1354 | return rc; | |
1355 | } | |
1356 | ||
7f620df8 ZW |
1357 | static inline void fsl_rio_info(struct device *dev, u32 ccsr) |
1358 | { | |
1359 | const char *str; | |
1360 | if (ccsr & 1) { | |
1361 | /* Serial phy */ | |
1362 | switch (ccsr >> 30) { | |
1363 | case 0: | |
1364 | str = "1"; | |
1365 | break; | |
1366 | case 1: | |
1367 | str = "4"; | |
1368 | break; | |
1369 | default: | |
1370 | str = "Unknown"; | |
d258e64e | 1371 | break; |
7f620df8 ZW |
1372 | } |
1373 | dev_info(dev, "Hardware port width: %s\n", str); | |
1374 | ||
1375 | switch ((ccsr >> 27) & 7) { | |
1376 | case 0: | |
1377 | str = "Single-lane 0"; | |
1378 | break; | |
1379 | case 1: | |
1380 | str = "Single-lane 2"; | |
1381 | break; | |
1382 | case 2: | |
1383 | str = "Four-lane"; | |
1384 | break; | |
1385 | default: | |
1386 | str = "Unknown"; | |
1387 | break; | |
1388 | } | |
1389 | dev_info(dev, "Training connection status: %s\n", str); | |
1390 | } else { | |
1391 | /* Parallel phy */ | |
1392 | if (!(ccsr & 0x80000000)) | |
1393 | dev_info(dev, "Output port operating in 8-bit mode\n"); | |
1394 | if (!(ccsr & 0x08000000)) | |
1395 | dev_info(dev, "Input port operating in 8-bit mode\n"); | |
1396 | } | |
1397 | } | |
1398 | ||
2b0c28d7 | 1399 | /** |
9941d945 | 1400 | * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface |
2dc11581 | 1401 | * @dev: platform_device pointer |
2b0c28d7 MP |
1402 | * |
1403 | * Initializes MPC85xx RapidIO hardware interface, configures | |
1404 | * master port with system-specific info, and registers the | |
1405 | * master port with the RapidIO subsystem. | |
1406 | */ | |
a454dc50 | 1407 | int fsl_rio_setup(struct platform_device *dev) |
2b0c28d7 MP |
1408 | { |
1409 | struct rio_ops *ops; | |
1410 | struct rio_mport *port; | |
cc2bb696 ZW |
1411 | struct rio_priv *priv; |
1412 | int rc = 0; | |
1413 | const u32 *dt_range, *cell; | |
1414 | struct resource regs; | |
1415 | int rlen; | |
61b26917 | 1416 | u32 ccsr; |
cc2bb696 ZW |
1417 | u64 law_start, law_size; |
1418 | int paw, aw, sw; | |
1419 | ||
61c7a080 | 1420 | if (!dev->dev.of_node) { |
cc2bb696 ZW |
1421 | dev_err(&dev->dev, "Device OF-Node is NULL"); |
1422 | return -EFAULT; | |
1423 | } | |
1424 | ||
61c7a080 | 1425 | rc = of_address_to_resource(dev->dev.of_node, 0, ®s); |
cc2bb696 ZW |
1426 | if (rc) { |
1427 | dev_err(&dev->dev, "Can't get %s property 'reg'\n", | |
61c7a080 | 1428 | dev->dev.of_node->full_name); |
cc2bb696 ZW |
1429 | return -EFAULT; |
1430 | } | |
61c7a080 | 1431 | dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name); |
fc274a15 | 1432 | dev_info(&dev->dev, "Regs: %pR\n", ®s); |
cc2bb696 | 1433 | |
61c7a080 | 1434 | dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen); |
cc2bb696 ZW |
1435 | if (!dt_range) { |
1436 | dev_err(&dev->dev, "Can't get %s property 'ranges'\n", | |
61c7a080 | 1437 | dev->dev.of_node->full_name); |
cc2bb696 ZW |
1438 | return -EFAULT; |
1439 | } | |
1440 | ||
1441 | /* Get node address wide */ | |
61c7a080 | 1442 | cell = of_get_property(dev->dev.of_node, "#address-cells", NULL); |
cc2bb696 ZW |
1443 | if (cell) |
1444 | aw = *cell; | |
1445 | else | |
61c7a080 | 1446 | aw = of_n_addr_cells(dev->dev.of_node); |
cc2bb696 | 1447 | /* Get node size wide */ |
61c7a080 | 1448 | cell = of_get_property(dev->dev.of_node, "#size-cells", NULL); |
cc2bb696 ZW |
1449 | if (cell) |
1450 | sw = *cell; | |
1451 | else | |
61c7a080 | 1452 | sw = of_n_size_cells(dev->dev.of_node); |
cc2bb696 | 1453 | /* Get parent address wide wide */ |
61c7a080 | 1454 | paw = of_n_addr_cells(dev->dev.of_node); |
cc2bb696 ZW |
1455 | |
1456 | law_start = of_read_number(dt_range + aw, paw); | |
1457 | law_size = of_read_number(dt_range + aw + paw, sw); | |
1458 | ||
1459 | dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n", | |
1460 | law_start, law_size); | |
2b0c28d7 | 1461 | |
e5cabeb3 | 1462 | ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL); |
6c75933c JL |
1463 | if (!ops) { |
1464 | rc = -ENOMEM; | |
1465 | goto err_ops; | |
1466 | } | |
d02443a6 ZW |
1467 | ops->lcread = fsl_local_config_read; |
1468 | ops->lcwrite = fsl_local_config_write; | |
1469 | ops->cread = fsl_rio_config_read; | |
1470 | ops->cwrite = fsl_rio_config_write; | |
1471 | ops->dsend = fsl_rio_doorbell_send; | |
5b2074ae | 1472 | ops->pwenable = fsl_rio_pw_enable; |
f8f06269 AB |
1473 | ops->open_outb_mbox = fsl_open_outb_mbox; |
1474 | ops->open_inb_mbox = fsl_open_inb_mbox; | |
1475 | ops->close_outb_mbox = fsl_close_outb_mbox; | |
1476 | ops->close_inb_mbox = fsl_close_inb_mbox; | |
1477 | ops->add_outb_message = fsl_add_outb_message; | |
1478 | ops->add_inb_buffer = fsl_add_inb_buffer; | |
1479 | ops->get_inb_message = fsl_get_inb_message; | |
2b0c28d7 | 1480 | |
ad1e9380 | 1481 | port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); |
6c75933c JL |
1482 | if (!port) { |
1483 | rc = -ENOMEM; | |
1484 | goto err_port; | |
1485 | } | |
2b0c28d7 | 1486 | port->index = 0; |
ad1e9380 ZW |
1487 | |
1488 | priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL); | |
1489 | if (!priv) { | |
1490 | printk(KERN_ERR "Can't alloc memory for 'priv'\n"); | |
1491 | rc = -ENOMEM; | |
6c75933c | 1492 | goto err_priv; |
ad1e9380 ZW |
1493 | } |
1494 | ||
2b0c28d7 MP |
1495 | INIT_LIST_HEAD(&port->dbells); |
1496 | port->iores.start = law_start; | |
186e74b9 | 1497 | port->iores.end = law_start + law_size - 1; |
2b0c28d7 | 1498 | port->iores.flags = IORESOURCE_MEM; |
186e74b9 | 1499 | port->iores.name = "rio_io_win"; |
2b0c28d7 | 1500 | |
c1256ebe AB |
1501 | if (request_resource(&iomem_resource, &port->iores) < 0) { |
1502 | dev_err(&dev->dev, "RIO: Error requesting master port region" | |
1503 | " 0x%016llx-0x%016llx\n", | |
1504 | (u64)port->iores.start, (u64)port->iores.end); | |
1505 | rc = -ENOMEM; | |
1506 | goto err_res; | |
1507 | } | |
1508 | ||
45fdf00d | 1509 | priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0); |
61c7a080 GL |
1510 | priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2); |
1511 | priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3); | |
1512 | priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4); | |
5b2074ae AB |
1513 | dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n", |
1514 | priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq); | |
cc2bb696 | 1515 | |
2b0c28d7 MP |
1516 | rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); |
1517 | rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0); | |
1518 | rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); | |
1519 | strcpy(port->name, "RIO0 mport"); | |
1520 | ||
0dbbbf1a AV |
1521 | priv->dev = &dev->dev; |
1522 | ||
2b0c28d7 | 1523 | port->ops = ops; |
ad1e9380 | 1524 | port->priv = priv; |
af84ca38 | 1525 | port->phys_efptr = 0x100; |
2b0c28d7 | 1526 | |
28f65c11 | 1527 | priv->regs_win = ioremap(regs.start, resource_size(®s)); |
a52c8f52 | 1528 | rio_regs_win = priv->regs_win; |
e0423236 | 1529 | |
61b26917 ZW |
1530 | /* Probe the master port phy type */ |
1531 | ccsr = in_be32(priv->regs_win + RIO_CCSR); | |
1532 | port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL; | |
1533 | dev_info(&dev->dev, "RapidIO PHY type: %s\n", | |
1534 | (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" : | |
1535 | ((port->phy_type == RIO_PHY_SERIAL) ? "serial" : | |
1536 | "unknown")); | |
7f620df8 ZW |
1537 | /* Checking the port training status */ |
1538 | if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { | |
1539 | dev_err(&dev->dev, "Port is not ready. " | |
1540 | "Try to restart connection...\n"); | |
1541 | switch (port->phy_type) { | |
1542 | case RIO_PHY_SERIAL: | |
1543 | /* Disable ports */ | |
1544 | out_be32(priv->regs_win + RIO_CCSR, 0); | |
1545 | /* Set 1x lane */ | |
1546 | setbits32(priv->regs_win + RIO_CCSR, 0x02000000); | |
1547 | /* Enable ports */ | |
1548 | setbits32(priv->regs_win + RIO_CCSR, 0x00600000); | |
1549 | break; | |
1550 | case RIO_PHY_PARALLEL: | |
1551 | /* Disable ports */ | |
1552 | out_be32(priv->regs_win + RIO_CCSR, 0x22000000); | |
1553 | /* Enable ports */ | |
1554 | out_be32(priv->regs_win + RIO_CCSR, 0x44000000); | |
1555 | break; | |
1556 | } | |
1557 | msleep(100); | |
1558 | if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { | |
1559 | dev_err(&dev->dev, "Port restart failed.\n"); | |
1560 | rc = -ENOLINK; | |
1561 | goto err; | |
1562 | } | |
1563 | dev_info(&dev->dev, "Port restart success!\n"); | |
1564 | } | |
1565 | fsl_rio_info(&dev->dev, ccsr); | |
61b26917 | 1566 | |
e0423236 ZW |
1567 | port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR)) |
1568 | & RIO_PEF_CTLS) >> 4; | |
1569 | dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", | |
1570 | port->sys_size ? 65536 : 256); | |
1571 | ||
59f99965 AB |
1572 | if (rio_register_mport(port)) |
1573 | goto err; | |
1574 | ||
af84ca38 AB |
1575 | if (port->host_deviceid >= 0) |
1576 | out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST | | |
1577 | RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED); | |
1578 | else | |
1579 | out_be32(priv->regs_win + RIO_GCCSR, 0x00000000); | |
1580 | ||
ad1e9380 ZW |
1581 | priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win |
1582 | + RIO_ATMU_REGS_OFFSET); | |
1583 | priv->maint_atmu_regs = priv->atmu_regs + 1; | |
1584 | priv->dbell_atmu_regs = priv->atmu_regs + 2; | |
61b26917 ZW |
1585 | priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win + |
1586 | ((port->phy_type == RIO_PHY_SERIAL) ? | |
1587 | RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET)); | |
1588 | ||
1589 | /* Set to receive any dist ID for serial RapidIO controller. */ | |
1590 | if (port->phy_type == RIO_PHY_SERIAL) | |
1591 | out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA); | |
2b0c28d7 MP |
1592 | |
1593 | /* Configure maintenance transaction window */ | |
186e74b9 | 1594 | out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12); |
bd4fb654 TM |
1595 | out_be32(&priv->maint_atmu_regs->rowar, |
1596 | 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1)); | |
2b0c28d7 | 1597 | |
ad1e9380 | 1598 | priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE); |
2b0c28d7 MP |
1599 | |
1600 | /* Configure outbound doorbell window */ | |
186e74b9 LY |
1601 | out_be32(&priv->dbell_atmu_regs->rowbar, |
1602 | (law_start + RIO_MAINT_WIN_SIZE) >> 12); | |
1603 | out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */ | |
d02443a6 | 1604 | fsl_rio_doorbell_init(port); |
5b2074ae | 1605 | fsl_rio_port_write_init(port); |
ad1e9380 | 1606 | |
cc2bb696 | 1607 | return 0; |
ad1e9380 | 1608 | err: |
6c75933c | 1609 | iounmap(priv->regs_win); |
c1256ebe | 1610 | err_res: |
ad1e9380 | 1611 | kfree(priv); |
6c75933c | 1612 | err_priv: |
ad1e9380 | 1613 | kfree(port); |
6c75933c JL |
1614 | err_port: |
1615 | kfree(ops); | |
1616 | err_ops: | |
cc2bb696 | 1617 | return rc; |
2b0c28d7 | 1618 | } |
cc2bb696 ZW |
1619 | |
1620 | /* The probe function for RapidIO peer-to-peer network. | |
1621 | */ | |
00006124 | 1622 | static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev) |
cc2bb696 | 1623 | { |
cc2bb696 | 1624 | printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n", |
61c7a080 | 1625 | dev->dev.of_node->full_name); |
cc2bb696 | 1626 | |
2f809985 | 1627 | return fsl_rio_setup(dev); |
cc2bb696 ZW |
1628 | }; |
1629 | ||
1630 | static const struct of_device_id fsl_of_rio_rpn_ids[] = { | |
1631 | { | |
1632 | .compatible = "fsl,rapidio-delta", | |
1633 | }, | |
1634 | {}, | |
1635 | }; | |
1636 | ||
00006124 | 1637 | static struct platform_driver fsl_of_rio_rpn_driver = { |
4018294b GL |
1638 | .driver = { |
1639 | .name = "fsl-of-rio", | |
1640 | .owner = THIS_MODULE, | |
1641 | .of_match_table = fsl_of_rio_rpn_ids, | |
1642 | }, | |
cc2bb696 ZW |
1643 | .probe = fsl_of_rio_rpn_probe, |
1644 | }; | |
1645 | ||
1646 | static __init int fsl_of_rio_rpn_init(void) | |
1647 | { | |
00006124 | 1648 | return platform_driver_register(&fsl_of_rio_rpn_driver); |
cc2bb696 ZW |
1649 | } |
1650 | ||
1651 | subsys_initcall(fsl_of_rio_rpn_init); |