[deliverable/linux.git] / arch / powerpc / sysdev / fsl_soc.c

/*
 * FSL SoC setup code
 *
 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
 *
 * 2006 (c) MontaVista Software, Inc.
 * Vitaly Bordug <vbordug@ru.mvista.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/major.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
#include <linux/phy_fixed.h>
#include <linux/spi/spi.h>
#include <linux/fsl_devices.h>
#include <linux/fs_enet_pd.h>
#include <linux/fs_uart_pd.h>

#include <asm/system.h>
#include <asm/atomic.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/time.h>
#include <asm/prom.h>
#include <sysdev/fsl_soc.h>
#include <mm/mmu_decl.h>
#include <asm/cpm2.h>

extern void init_fcc_ioports(struct fs_platform_info*);
extern void init_fec_ioports(struct fs_platform_info*);
extern void init_smc_ioports(struct fs_uart_platform_info*);
static phys_addr_t immrbase = -1;

phys_addr_t get_immrbase(void)
{
	struct device_node *soc;

	if (immrbase != -1)
		return immrbase;

	soc = of_find_node_by_type(NULL, "soc");
	if (soc) {
		int size;
		u32 naddr;
		const u32 *prop = of_get_property(soc, "#address-cells", &size);

		if (prop && size == 4)
			naddr = *prop;
		else
			naddr = 2;

		prop = of_get_property(soc, "ranges", &size);
		if (prop)
			immrbase = of_translate_address(soc, prop + naddr);

		of_node_put(soc);
	}

	return immrbase;
}

EXPORT_SYMBOL(get_immrbase);

static u32 sysfreq = -1;

u32 fsl_get_sys_freq(void)
{
	struct device_node *soc;
	const u32 *prop;
	int size;

	if (sysfreq != -1)
		return sysfreq;

	soc = of_find_node_by_type(NULL, "soc");
	if (!soc)
		return -1;

	prop = of_get_property(soc, "clock-frequency", &size);
	if (!prop || size != sizeof(*prop) || *prop == 0)
		prop = of_get_property(soc, "bus-frequency", &size);

	if (prop && size == sizeof(*prop))
		sysfreq = *prop;

	of_node_put(soc);
	return sysfreq;
}
EXPORT_SYMBOL(fsl_get_sys_freq);

#if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx)

static u32 brgfreq = -1;

u32 get_brgfreq(void)
{
	struct device_node *node;
	const unsigned int *prop;
	int size;

	if (brgfreq != -1)
		return brgfreq;

	node = of_find_compatible_node(NULL, NULL, "fsl,cpm-brg");
	if (node) {
		prop = of_get_property(node, "clock-frequency", &size);
		if (prop && size == 4)
			brgfreq = *prop;

		of_node_put(node);
		return brgfreq;
	}

	/* Legacy device binding -- will go away when no users are left. */
	node = of_find_node_by_type(NULL, "cpm");
	if (!node)
		node = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!node)
		node = of_find_node_by_type(NULL, "qe");

	if (node) {
		prop = of_get_property(node, "brg-frequency", &size);
		if (prop && size == 4)
			brgfreq = *prop;

		if (brgfreq == -1 || brgfreq == 0) {
			prop = of_get_property(node, "bus-frequency", &size);
			if (prop && size == 4)
				brgfreq = *prop / 2;
		}
		of_node_put(node);
	}

	return brgfreq;
}

EXPORT_SYMBOL(get_brgfreq);

static u32 fs_baudrate = -1;

u32 get_baudrate(void)
{
	struct device_node *node;

	if (fs_baudrate != -1)
		return fs_baudrate;

	node = of_find_node_by_type(NULL, "serial");
	if (node) {
		int size;
		const unsigned int *prop = of_get_property(node,
				"current-speed", &size);

		if (prop)
			fs_baudrate = *prop;
		of_node_put(node);
	}

	return fs_baudrate;
}

EXPORT_SYMBOL(get_baudrate);
#endif /* CONFIG_CPM2 */

#ifdef CONFIG_FIXED_PHY
static int __init of_add_fixed_phys(void)
{
	int ret;
	struct device_node *np;
	u32 *fixed_link;
	struct fixed_phy_status status = {};

	for_each_node_by_name(np, "ethernet") {
		fixed_link  = (u32 *)of_get_property(np, "fixed-link", NULL);
		if (!fixed_link)
			continue;

		status.link = 1;
		status.duplex = fixed_link[1];
		status.speed = fixed_link[2];
		status.pause = fixed_link[3];
		status.asym_pause = fixed_link[4];

		ret = fixed_phy_add(PHY_POLL, fixed_link[0], &status);
		if (ret) {
			of_node_put(np);
			return ret;
		}
	}

	return 0;
}
arch_initcall(of_add_fixed_phys);
#endif /* CONFIG_FIXED_PHY */

#ifdef CONFIG_PPC_83xx
static int __init mpc83xx_wdt_init(void)
{
	struct resource r;
	struct device_node *np;
	struct platform_device *dev;
	u32 freq = fsl_get_sys_freq();
	int ret;

	np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt");

	if (!np) {
		ret = -ENODEV;
		goto nodev;
	}

	memset(&r, 0, sizeof(r));

	ret = of_address_to_resource(np, 0, &r);
	if (ret)
		goto err;

	dev = platform_device_register_simple("mpc83xx_wdt", 0, &r, 1);
	if (IS_ERR(dev)) {
		ret = PTR_ERR(dev);
		goto err;
	}

	ret = platform_device_add_data(dev, &freq, sizeof(freq));
	if (ret)
		goto unreg;

	of_node_put(np);
	return 0;

unreg:
	platform_device_unregister(dev);
err:
	of_node_put(np);
nodev:
	return ret;
}

arch_initcall(mpc83xx_wdt_init);
#endif

static enum fsl_usb2_phy_modes determine_usb_phy(const char *phy_type)
{
	if (!phy_type)
		return FSL_USB2_PHY_NONE;
	if (!strcasecmp(phy_type, "ulpi"))
		return FSL_USB2_PHY_ULPI;
	if (!strcasecmp(phy_type, "utmi"))
		return FSL_USB2_PHY_UTMI;
	if (!strcasecmp(phy_type, "utmi_wide"))
		return FSL_USB2_PHY_UTMI_WIDE;
	if (!strcasecmp(phy_type, "serial"))
		return FSL_USB2_PHY_SERIAL;

	return FSL_USB2_PHY_NONE;
}

static int __init fsl_usb_of_init(void)
{
	struct device_node *np;
	unsigned int i = 0;
	struct platform_device *usb_dev_mph = NULL, *usb_dev_dr_host = NULL,
		*usb_dev_dr_client = NULL;
	int ret;

	for_each_compatible_node(np, NULL, "fsl-usb2-mph") {
		struct resource r[2];
		struct fsl_usb2_platform_data usb_data;
		const unsigned char *prop = NULL;

		memset(&r, 0, sizeof(r));
		memset(&usb_data, 0, sizeof(usb_data));

		ret = of_address_to_resource(np, 0, &r[0]);
		if (ret)
			goto err;

		of_irq_to_resource(np, 0, &r[1]);

		usb_dev_mph =
		    platform_device_register_simple("fsl-ehci", i, r, 2);
		if (IS_ERR(usb_dev_mph)) {
			ret = PTR_ERR(usb_dev_mph);
			goto err;
		}

		usb_dev_mph->dev.coherent_dma_mask = 0xffffffffUL;
		usb_dev_mph->dev.dma_mask = &usb_dev_mph->dev.coherent_dma_mask;

		usb_data.operating_mode = FSL_USB2_MPH_HOST;

		prop = of_get_property(np, "port0", NULL);
		if (prop)
			usb_data.port_enables |= FSL_USB2_PORT0_ENABLED;

		prop = of_get_property(np, "port1", NULL);
		if (prop)
			usb_data.port_enables |= FSL_USB2_PORT1_ENABLED;

		prop = of_get_property(np, "phy_type", NULL);
		usb_data.phy_mode = determine_usb_phy(prop);

		ret =
		    platform_device_add_data(usb_dev_mph, &usb_data,
					     sizeof(struct
						    fsl_usb2_platform_data));
		if (ret)
			goto unreg_mph;
		i++;
	}

	for_each_compatible_node(np, NULL, "fsl-usb2-dr") {
		struct resource r[2];
		struct fsl_usb2_platform_data usb_data;
		const unsigned char *prop = NULL;

		if (!of_device_is_available(np))
			continue;

		memset(&r, 0, sizeof(r));
		memset(&usb_data, 0, sizeof(usb_data));

		ret = of_address_to_resource(np, 0, &r[0]);
		if (ret)
			goto unreg_mph;

		of_irq_to_resource(np, 0, &r[1]);

		prop = of_get_property(np, "dr_mode", NULL);

		if (!prop || !strcmp(prop, "host")) {
			usb_data.operating_mode = FSL_USB2_DR_HOST;
			usb_dev_dr_host = platform_device_register_simple(
					"fsl-ehci", i, r, 2);
			if (IS_ERR(usb_dev_dr_host)) {
				ret = PTR_ERR(usb_dev_dr_host);
				goto err;
			}
		} else if (prop && !strcmp(prop, "peripheral")) {
			usb_data.operating_mode = FSL_USB2_DR_DEVICE;
			usb_dev_dr_client = platform_device_register_simple(
					"fsl-usb2-udc", i, r, 2);
			if (IS_ERR(usb_dev_dr_client)) {
				ret = PTR_ERR(usb_dev_dr_client);
				goto err;
			}
		} else if (prop && !strcmp(prop, "otg")) {
			usb_data.operating_mode = FSL_USB2_DR_OTG;
			usb_dev_dr_host = platform_device_register_simple(
					"fsl-ehci", i, r, 2);
			if (IS_ERR(usb_dev_dr_host)) {
				ret = PTR_ERR(usb_dev_dr_host);
				goto err;
			}
			usb_dev_dr_client = platform_device_register_simple(
					"fsl-usb2-udc", i, r, 2);
			if (IS_ERR(usb_dev_dr_client)) {
				ret = PTR_ERR(usb_dev_dr_client);
				goto err;
			}
		} else {
			ret = -EINVAL;
			goto err;
		}

		prop = of_get_property(np, "phy_type", NULL);
		usb_data.phy_mode = determine_usb_phy(prop);

		if (usb_dev_dr_host) {
			usb_dev_dr_host->dev.coherent_dma_mask = 0xffffffffUL;
			usb_dev_dr_host->dev.dma_mask = &usb_dev_dr_host->
				dev.coherent_dma_mask;
			if ((ret = platform_device_add_data(usb_dev_dr_host,
						&usb_data, sizeof(struct
						fsl_usb2_platform_data))))
				goto unreg_dr;
		}
		if (usb_dev_dr_client) {
			usb_dev_dr_client->dev.coherent_dma_mask = 0xffffffffUL;
			usb_dev_dr_client->dev.dma_mask = &usb_dev_dr_client->
				dev.coherent_dma_mask;
			if ((ret = platform_device_add_data(usb_dev_dr_client,
						&usb_data, sizeof(struct
						fsl_usb2_platform_data))))
				goto unreg_dr;
		}
		i++;
	}
	return 0;

unreg_dr:
	if (usb_dev_dr_host)
		platform_device_unregister(usb_dev_dr_host);
	if (usb_dev_dr_client)
		platform_device_unregister(usb_dev_dr_client);
unreg_mph:
	if (usb_dev_mph)
		platform_device_unregister(usb_dev_mph);
err:
	return ret;
}

arch_initcall(fsl_usb_of_init);

static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
				   struct spi_board_info *board_infos,
				   unsigned int num_board_infos,
				   void (*activate_cs)(u8 cs, u8 polarity),
				   void (*deactivate_cs)(u8 cs, u8 polarity))
{
	struct device_node *np;
	unsigned int i = 0;

	for_each_compatible_node(np, type, compatible) {
		int ret;
		unsigned int j;
		const void *prop;
		struct resource res[2];
		struct platform_device *pdev;
		struct fsl_spi_platform_data pdata = {
			.activate_cs = activate_cs,
			.deactivate_cs = deactivate_cs,
		};

		memset(res, 0, sizeof(res));

		pdata.sysclk = sysclk;

		prop = of_get_property(np, "reg", NULL);
		if (!prop)
			goto err;
		pdata.bus_num = *(u32 *)prop;

		prop = of_get_property(np, "cell-index", NULL);
		if (prop)
			i = *(u32 *)prop;

		prop = of_get_property(np, "mode", NULL);
		if (prop && !strcmp(prop, "cpu-qe"))
			pdata.qe_mode = 1;

		for (j = 0; j < num_board_infos; j++) {
			if (board_infos[j].bus_num == pdata.bus_num)
				pdata.max_chipselect++;
		}

		if (!pdata.max_chipselect)
			continue;

		ret = of_address_to_resource(np, 0, &res[0]);
		if (ret)
			goto err;

		ret = of_irq_to_resource(np, 0, &res[1]);
		if (ret == NO_IRQ)
			goto err;

		pdev = platform_device_alloc("mpc83xx_spi", i);
		if (!pdev)
			goto err;

		ret = platform_device_add_data(pdev, &pdata, sizeof(pdata));
		if (ret)
			goto unreg;

		ret = platform_device_add_resources(pdev, res,
						    ARRAY_SIZE(res));
		if (ret)
			goto unreg;

		ret = platform_device_add(pdev);
		if (ret)
			goto unreg;

		goto next;
unreg:
		platform_device_del(pdev);
err:
		pr_err("%s: registration failed\n", np->full_name);
next:
		i++;
	}

	return i;
}

int __init fsl_spi_init(struct spi_board_info *board_infos,
			unsigned int num_board_infos,
			void (*activate_cs)(u8 cs, u8 polarity),
			void (*deactivate_cs)(u8 cs, u8 polarity))
{
	u32 sysclk = -1;
	int ret;

#ifdef CONFIG_QUICC_ENGINE
	/* SPI controller is either clocked from QE or SoC clock */
	sysclk = get_brgfreq();
#endif
	if (sysclk == -1) {
		sysclk = fsl_get_sys_freq();
		if (sysclk == -1)
			return -ENODEV;
	}

	ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,
			       num_board_infos, activate_cs, deactivate_cs);
	if (!ret)
		of_fsl_spi_probe("spi", "fsl_spi", sysclk, board_infos,
				 num_board_infos, activate_cs, deactivate_cs);

	return spi_register_board_info(board_infos, num_board_infos);
}

#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
static __be32 __iomem *rstcr;

static int __init setup_rstcr(void)
{
	struct device_node *np;
	np = of_find_node_by_name(NULL, "global-utilities");
	if ((np && of_get_property(np, "fsl,has-rstcr", NULL))) {
		const u32 *prop = of_get_property(np, "reg", NULL);
		if (prop) {
			/* map reset control register
			 * 0xE00B0 is offset of reset control register
			 */
			rstcr = ioremap(get_immrbase() + *prop + 0xB0, 0xff);
			if (!rstcr)
				printk (KERN_EMERG "Error: reset control "
						"register not mapped!\n");
		}
	} else
		printk (KERN_INFO "rstcr compatible register does not exist!\n");
	if (np)
		of_node_put(np);
	return 0;
}

arch_initcall(setup_rstcr);

void fsl_rstcr_restart(char *cmd)
{
	local_irq_disable();
	if (rstcr)
		/* set reset control register */
		out_be32(rstcr, 0x2);	/* HRESET_REQ */

	while (1) ;
}
#endif

#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
struct platform_diu_data_ops diu_ops;
EXPORT_SYMBOL(diu_ops);
#endif
Commit	Line	Data
eed32001 KG	1	/*
	2	* FSL SoC setup code
	3	*
	4	* Maintained by Kumar Gala (see MAINTAINERS for contact information)
	5	*
fba43665 VB	6	* 2006 (c) MontaVista Software, Inc.
	7	* Vitaly Bordug <vbordug@ru.mvista.com>
	8	*
eed32001 KG	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*/
	14
eed32001 KG	15	#include <linux/stddef.h>
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
	18	#include <linux/errno.h>
	19	#include <linux/major.h>
	20	#include <linux/delay.h>
	21	#include <linux/irq.h>
	22	#include <linux/module.h>
	23	#include <linux/device.h>
	24	#include <linux/platform_device.h>
c026c987	25	#include <linux/of.h>
0af666fa	26	#include <linux/of_platform.h>
a9b14973	27	#include <linux/phy.h>
a21e282a	28	#include <linux/phy_fixed.h>
26f6cb99	29	#include <linux/spi/spi.h>
eed32001	30	#include <linux/fsl_devices.h>
fba43665 VB	31	#include <linux/fs_enet_pd.h>
fba43665 VB	32	#include <linux/fs_uart_pd.h>
eed32001 KG	33
	34	#include <asm/system.h>
	35	#include <asm/atomic.h>
	36	#include <asm/io.h>
	37	#include <asm/irq.h>
fba43665	38	#include <asm/time.h>
eed32001 KG	39	#include <asm/prom.h>
	40	#include <sysdev/fsl_soc.h>
	41	#include <mm/mmu_decl.h>
fba43665	42	#include <asm/cpm2.h>
eed32001	43
d3465c92	44	extern void init_fcc_ioports(struct fs_platform_info*);
88bdc6f0 VB	45	extern void init_fec_ioports(struct fs_platform_info*);
88bdc6f0 VB	46	extern void init_smc_ioports(struct fs_uart_platform_info*);
eed32001 KG	47	static phys_addr_t immrbase = -1;
	48
	49	phys_addr_t get_immrbase(void)
	50	{
	51	struct device_node *soc;
	52
	53	if (immrbase != -1)
	54	return immrbase;
	55
	56	soc = of_find_node_by_type(NULL, "soc");
2fb07d77	57	if (soc) {
f9234736	58	int size;
6c7e072b SW	59	u32 naddr;
6c7e072b SW	60	const u32 *prop = of_get_property(soc, "#address-cells", &size);
fba43665	61
6c7e072b SW	62	if (prop && size == 4)
	63	naddr = *prop;
	64	else
	65	naddr = 2;
	66
	67	prop = of_get_property(soc, "ranges", &size);
fba43665	68	if (prop)
6c7e072b SW	69	immrbase = of_translate_address(soc, prop + naddr);
6c7e072b SW	70
eed32001	71	of_node_put(soc);
f9234736	72	}
eed32001 KG	73
	74	return immrbase;
	75	}
eed32001	76
2fb07d77	77	EXPORT_SYMBOL(get_immrbase);
eed32001	78
38664095 SW	79	static u32 sysfreq = -1;
	80
	81	u32 fsl_get_sys_freq(void)
	82	{
	83	struct device_node *soc;
	84	const u32 *prop;
	85	int size;
	86
	87	if (sysfreq != -1)
	88	return sysfreq;
	89
	90	soc = of_find_node_by_type(NULL, "soc");
	91	if (!soc)
	92	return -1;
	93
	94	prop = of_get_property(soc, "clock-frequency", &size);
	95	if (!prop \|\| size != sizeof(prop) \|\| prop == 0)
	96	prop = of_get_property(soc, "bus-frequency", &size);
	97
	98	if (prop && size == sizeof(*prop))
	99	sysfreq = *prop;
	100
	101	of_node_put(soc);
	102	return sysfreq;
	103	}
	104	EXPORT_SYMBOL(fsl_get_sys_freq);
	105
59a0ea50	106	#if defined(CONFIG_CPM2) \|\| defined(CONFIG_QUICC_ENGINE) \|\| defined(CONFIG_8xx)
fba43665 VB	107
	108	static u32 brgfreq = -1;
	109
	110	u32 get_brgfreq(void)
	111	{
	112	struct device_node *node;
6d817aa7 SW	113	const unsigned int *prop;
6d817aa7 SW	114	int size;
fba43665 VB	115
	116	if (brgfreq != -1)
	117	return brgfreq;
	118
6d817aa7	119	node = of_find_compatible_node(NULL, NULL, "fsl,cpm-brg");
fba43665	120	if (node) {
6d817aa7 SW	121	prop = of_get_property(node, "clock-frequency", &size);
	122	if (prop && size == 4)
	123	brgfreq = *prop;
	124
	125	of_node_put(node);
	126	return brgfreq;
	127	}
fba43665	128
6d817aa7 SW	129	/* Legacy device binding -- will go away when no users are left. */
6d817aa7 SW	130	node = of_find_node_by_type(NULL, "cpm");
59a0ea50 AV	131	if (!node)
	132	node = of_find_compatible_node(NULL, NULL, "fsl,qe");
	133	if (!node)
	134	node = of_find_node_by_type(NULL, "qe");
	135
6d817aa7 SW	136	if (node) {
6d817aa7 SW	137	prop = of_get_property(node, "brg-frequency", &size);
f9234736	138	if (prop && size == 4)
fba43665	139	brgfreq = *prop;
f9234736	140
59a0ea50 AV	141	if (brgfreq == -1 \|\| brgfreq == 0) {
	142	prop = of_get_property(node, "bus-frequency", &size);
	143	if (prop && size == 4)
	144	brgfreq = *prop / 2;
	145	}
fba43665	146	of_node_put(node);
f9234736	147	}
fba43665 VB	148
	149	return brgfreq;
	150	}
	151
	152	EXPORT_SYMBOL(get_brgfreq);
	153
	154	static u32 fs_baudrate = -1;
	155
	156	u32 get_baudrate(void)
	157	{
	158	struct device_node *node;
	159
	160	if (fs_baudrate != -1)
	161	return fs_baudrate;
	162
	163	node = of_find_node_by_type(NULL, "serial");
	164	if (node) {
f9234736	165	int size;
e2eb6392 SR	166	const unsigned int *prop = of_get_property(node,
e2eb6392 SR	167	"current-speed", &size);
fba43665 VB	168
	169	if (prop)
	170	fs_baudrate = *prop;
	171	of_node_put(node);
f9234736	172	}
fba43665 VB	173
	174	return fs_baudrate;
	175	}
	176
	177	EXPORT_SYMBOL(get_baudrate);
	178	#endif /* CONFIG_CPM2 */
	179
a21e282a VB	180	#ifdef CONFIG_FIXED_PHY
	181	static int __init of_add_fixed_phys(void)
	182	{
	183	int ret;
	184	struct device_node *np;
	185	u32 *fixed_link;
	186	struct fixed_phy_status status = {};
	187
	188	for_each_node_by_name(np, "ethernet") {
	189	fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
	190	if (!fixed_link)
	191	continue;
	192
	193	status.link = 1;
	194	status.duplex = fixed_link[1];
	195	status.speed = fixed_link[2];
	196	status.pause = fixed_link[3];
	197	status.asym_pause = fixed_link[4];
	198
	199	ret = fixed_phy_add(PHY_POLL, fixed_link[0], &status);
	200	if (ret) {
	201	of_node_put(np);
	202	return ret;
	203	}
	204	}
	205
	206	return 0;
	207	}
	208	arch_initcall(of_add_fixed_phys);
	209	#endif /* CONFIG_FIXED_PHY */
	210
b31a1d8b AF	211	#ifdef CONFIG_PPC_83xx
b31a1d8b AF	212	static int __init mpc83xx_wdt_init(void)
2fb07d77	213	{
b31a1d8b	214	struct resource r;
2fb07d77	215	struct device_node *np;
b31a1d8b AF	216	struct platform_device *dev;
b31a1d8b AF	217	u32 freq = fsl_get_sys_freq();
2fb07d77 KG	218	int ret;
2fb07d77 KG	219
b31a1d8b	220	np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt");
eed32001	221
b31a1d8b AF	222	if (!np) {
	223	ret = -ENODEV;
	224	goto nodev;
	225	}
eed32001	226
b31a1d8b	227	memset(&r, 0, sizeof(r));
eed32001	228
b31a1d8b AF	229	ret = of_address_to_resource(np, 0, &r);
	230	if (ret)
	231	goto err;
c132419e	232
b31a1d8b AF	233	dev = platform_device_register_simple("mpc83xx_wdt", 0, &r, 1);
	234	if (IS_ERR(dev)) {
	235	ret = PTR_ERR(dev);
	236	goto err;
eed32001 KG	237	}
eed32001 KG	238
b31a1d8b AF	239	ret = platform_device_add_data(dev, &freq, sizeof(freq));
	240	if (ret)
	241	goto unreg;
	242
	243	of_node_put(np);
eed32001 KG	244	return 0;
eed32001 KG	245
2fb07d77	246	unreg:
b31a1d8b	247	platform_device_unregister(dev);
2fb07d77	248	err:
b31a1d8b AF	249	of_node_put(np);
b31a1d8b AF	250	nodev:
eed32001 KG	251	return ret;
eed32001 KG	252	}
2fb07d77	253
b31a1d8b AF	254	arch_initcall(mpc83xx_wdt_init);
b31a1d8b AF	255	#endif
eed32001	256
a7f67bdf	257	static enum fsl_usb2_phy_modes determine_usb_phy(const char *phy_type)
4b10cfd4 KG	258	{
	259	if (!phy_type)
	260	return FSL_USB2_PHY_NONE;
	261	if (!strcasecmp(phy_type, "ulpi"))
	262	return FSL_USB2_PHY_ULPI;
	263	if (!strcasecmp(phy_type, "utmi"))
	264	return FSL_USB2_PHY_UTMI;
	265	if (!strcasecmp(phy_type, "utmi_wide"))
	266	return FSL_USB2_PHY_UTMI_WIDE;
	267	if (!strcasecmp(phy_type, "serial"))
	268	return FSL_USB2_PHY_SERIAL;
	269
	270	return FSL_USB2_PHY_NONE;
	271	}
	272
	273	static int __init fsl_usb_of_init(void)
	274	{
	275	struct device_node *np;
866b6ddd	276	unsigned int i = 0;
97c5a20a LY	277	struct platform_device usb_dev_mph = NULL, usb_dev_dr_host = NULL,
97c5a20a LY	278	*usb_dev_dr_client = NULL;
4b10cfd4 KG	279	int ret;
4b10cfd4 KG	280
866b6ddd	281	for_each_compatible_node(np, NULL, "fsl-usb2-mph") {
4b10cfd4 KG	282	struct resource r[2];
4b10cfd4 KG	283	struct fsl_usb2_platform_data usb_data;
a7f67bdf	284	const unsigned char *prop = NULL;
4b10cfd4 KG	285
	286	memset(&r, 0, sizeof(r));
	287	memset(&usb_data, 0, sizeof(usb_data));
	288
	289	ret = of_address_to_resource(np, 0, &r[0]);
	290	if (ret)
	291	goto err;
	292
a9b14973	293	of_irq_to_resource(np, 0, &r[1]);
4b10cfd4	294
01cced25 KG	295	usb_dev_mph =
	296	platform_device_register_simple("fsl-ehci", i, r, 2);
	297	if (IS_ERR(usb_dev_mph)) {
	298	ret = PTR_ERR(usb_dev_mph);
4b10cfd4 KG	299	goto err;
	300	}
	301
01cced25 KG	302	usb_dev_mph->dev.coherent_dma_mask = 0xffffffffUL;
01cced25 KG	303	usb_dev_mph->dev.dma_mask = &usb_dev_mph->dev.coherent_dma_mask;
4b10cfd4 KG	304
	305	usb_data.operating_mode = FSL_USB2_MPH_HOST;
	306
e2eb6392	307	prop = of_get_property(np, "port0", NULL);
4b10cfd4 KG	308	if (prop)
	309	usb_data.port_enables \|= FSL_USB2_PORT0_ENABLED;
	310
e2eb6392	311	prop = of_get_property(np, "port1", NULL);
4b10cfd4 KG	312	if (prop)
	313	usb_data.port_enables \|= FSL_USB2_PORT1_ENABLED;
	314
e2eb6392	315	prop = of_get_property(np, "phy_type", NULL);
4b10cfd4 KG	316	usb_data.phy_mode = determine_usb_phy(prop);
	317
	318	ret =
01cced25	319	platform_device_add_data(usb_dev_mph, &usb_data,
4b10cfd4 KG	320	sizeof(struct
	321	fsl_usb2_platform_data));
	322	if (ret)
01cced25	323	goto unreg_mph;
866b6ddd	324	i++;
4b10cfd4 KG	325	}
4b10cfd4 KG	326
866b6ddd	327	for_each_compatible_node(np, NULL, "fsl-usb2-dr") {
4b10cfd4 KG	328	struct resource r[2];
4b10cfd4 KG	329	struct fsl_usb2_platform_data usb_data;
a7f67bdf	330	const unsigned char *prop = NULL;
4b10cfd4	331
c026c987 AV	332	if (!of_device_is_available(np))
	333	continue;
	334
4b10cfd4 KG	335	memset(&r, 0, sizeof(r));
	336	memset(&usb_data, 0, sizeof(usb_data));
	337
	338	ret = of_address_to_resource(np, 0, &r[0]);
	339	if (ret)
01cced25	340	goto unreg_mph;
4b10cfd4	341
a9b14973	342	of_irq_to_resource(np, 0, &r[1]);
4b10cfd4	343
e2eb6392	344	prop = of_get_property(np, "dr_mode", NULL);
97c5a20a LY	345
	346	if (!prop \|\| !strcmp(prop, "host")) {
	347	usb_data.operating_mode = FSL_USB2_DR_HOST;
	348	usb_dev_dr_host = platform_device_register_simple(
	349	"fsl-ehci", i, r, 2);
	350	if (IS_ERR(usb_dev_dr_host)) {
	351	ret = PTR_ERR(usb_dev_dr_host);
	352	goto err;
	353	}
	354	} else if (prop && !strcmp(prop, "peripheral")) {
	355	usb_data.operating_mode = FSL_USB2_DR_DEVICE;
	356	usb_dev_dr_client = platform_device_register_simple(
	357	"fsl-usb2-udc", i, r, 2);
	358	if (IS_ERR(usb_dev_dr_client)) {
	359	ret = PTR_ERR(usb_dev_dr_client);
	360	goto err;
	361	}
	362	} else if (prop && !strcmp(prop, "otg")) {
	363	usb_data.operating_mode = FSL_USB2_DR_OTG;
	364	usb_dev_dr_host = platform_device_register_simple(
	365	"fsl-ehci", i, r, 2);
	366	if (IS_ERR(usb_dev_dr_host)) {
	367	ret = PTR_ERR(usb_dev_dr_host);
	368	goto err;
	369	}
	370	usb_dev_dr_client = platform_device_register_simple(
	371	"fsl-usb2-udc", i, r, 2);
	372	if (IS_ERR(usb_dev_dr_client)) {
	373	ret = PTR_ERR(usb_dev_dr_client);
	374	goto err;
	375	}
	376	} else {
	377	ret = -EINVAL;
4b10cfd4 KG	378	goto err;
	379	}
	380
e2eb6392	381	prop = of_get_property(np, "phy_type", NULL);
4b10cfd4 KG	382	usb_data.phy_mode = determine_usb_phy(prop);
4b10cfd4 KG	383
97c5a20a LY	384	if (usb_dev_dr_host) {
	385	usb_dev_dr_host->dev.coherent_dma_mask = 0xffffffffUL;
	386	usb_dev_dr_host->dev.dma_mask = &usb_dev_dr_host->
	387	dev.coherent_dma_mask;
	388	if ((ret = platform_device_add_data(usb_dev_dr_host,
	389	&usb_data, sizeof(struct
	390	fsl_usb2_platform_data))))
	391	goto unreg_dr;
	392	}
	393	if (usb_dev_dr_client) {
	394	usb_dev_dr_client->dev.coherent_dma_mask = 0xffffffffUL;
	395	usb_dev_dr_client->dev.dma_mask = &usb_dev_dr_client->
	396	dev.coherent_dma_mask;
	397	if ((ret = platform_device_add_data(usb_dev_dr_client,
	398	&usb_data, sizeof(struct
	399	fsl_usb2_platform_data))))
	400	goto unreg_dr;
	401	}
866b6ddd	402	i++;
4b10cfd4	403	}
4b10cfd4 KG	404	return 0;
4b10cfd4 KG	405
01cced25	406	unreg_dr:
97c5a20a LY	407	if (usb_dev_dr_host)
	408	platform_device_unregister(usb_dev_dr_host);
	409	if (usb_dev_dr_client)
	410	platform_device_unregister(usb_dev_dr_client);
01cced25 KG	411	unreg_mph:
	412	if (usb_dev_mph)
	413	platform_device_unregister(usb_dev_mph);
4b10cfd4 KG	414	err:
	415	return ret;
	416	}
	417
01cced25	418	arch_initcall(fsl_usb_of_init);
fba43665	419
f3a2b29d AV	420	static int __init of_fsl_spi_probe(char type, char compatible, u32 sysclk,
	421	struct spi_board_info *board_infos,
	422	unsigned int num_board_infos,
	423	void (*activate_cs)(u8 cs, u8 polarity),
	424	void (*deactivate_cs)(u8 cs, u8 polarity))
26f6cb99 AV	425	{
26f6cb99 AV	426	struct device_node *np;
f3a2b29d	427	unsigned int i = 0;
26f6cb99	428
f3a2b29d AV	429	for_each_compatible_node(np, type, compatible) {
f3a2b29d AV	430	int ret;
26f6cb99 AV	431	unsigned int j;
	432	const void *prop;
	433	struct resource res[2];
	434	struct platform_device *pdev;
	435	struct fsl_spi_platform_data pdata = {
	436	.activate_cs = activate_cs,
	437	.deactivate_cs = deactivate_cs,
	438	};
	439
	440	memset(res, 0, sizeof(res));
	441
59a0ea50	442	pdata.sysclk = sysclk;
26f6cb99 AV	443
	444	prop = of_get_property(np, "reg", NULL);
	445	if (!prop)
	446	goto err;
	447	pdata.bus_num = (u32 )prop;
	448
f3a2b29d AV	449	prop = of_get_property(np, "cell-index", NULL);
	450	if (prop)
	451	i = (u32 )prop;
	452
26f6cb99 AV	453	prop = of_get_property(np, "mode", NULL);
	454	if (prop && !strcmp(prop, "cpu-qe"))
	455	pdata.qe_mode = 1;
	456
	457	for (j = 0; j < num_board_infos; j++) {
	458	if (board_infos[j].bus_num == pdata.bus_num)
	459	pdata.max_chipselect++;
	460	}
	461
	462	if (!pdata.max_chipselect)
f3a2b29d	463	continue;
26f6cb99 AV	464
	465	ret = of_address_to_resource(np, 0, &res[0]);
	466	if (ret)
	467	goto err;
	468
	469	ret = of_irq_to_resource(np, 0, &res[1]);
	470	if (ret == NO_IRQ)
	471	goto err;
	472
	473	pdev = platform_device_alloc("mpc83xx_spi", i);
	474	if (!pdev)
	475	goto err;
	476
	477	ret = platform_device_add_data(pdev, &pdata, sizeof(pdata));
	478	if (ret)
	479	goto unreg;
	480
	481	ret = platform_device_add_resources(pdev, res,
	482	ARRAY_SIZE(res));
	483	if (ret)
	484	goto unreg;
	485
dc4e4207	486	ret = platform_device_add(pdev);
26f6cb99 AV	487	if (ret)
	488	goto unreg;
	489
f3a2b29d	490	goto next;
26f6cb99 AV	491	unreg:
	492	platform_device_del(pdev);
	493	err:
f3a2b29d AV	494	pr_err("%s: registration failed\n", np->full_name);
	495	next:
	496	i++;
26f6cb99 AV	497	}
26f6cb99 AV	498
f3a2b29d AV	499	return i;
	500	}
	501
	502	int __init fsl_spi_init(struct spi_board_info *board_infos,
	503	unsigned int num_board_infos,
	504	void (*activate_cs)(u8 cs, u8 polarity),
	505	void (*deactivate_cs)(u8 cs, u8 polarity))
	506	{
	507	u32 sysclk = -1;
	508	int ret;
	509
	510	#ifdef CONFIG_QUICC_ENGINE
	511	/* SPI controller is either clocked from QE or SoC clock */
	512	sysclk = get_brgfreq();
	513	#endif
	514	if (sysclk == -1) {
38664095 SW	515	sysclk = fsl_get_sys_freq();
38664095 SW	516	if (sysclk == -1)
f3a2b29d	517	return -ENODEV;
f3a2b29d AV	518	}
	519
	520	ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,
	521	num_board_infos, activate_cs, deactivate_cs);
	522	if (!ret)
	523	of_fsl_spi_probe("spi", "fsl_spi", sysclk, board_infos,
	524	num_board_infos, activate_cs, deactivate_cs);
	525
26f6cb99 AV	526	return spi_register_board_info(board_infos, num_board_infos);
26f6cb99 AV	527	}
e1c1575f KG	528
	529	#if defined(CONFIG_PPC_85xx) \|\| defined(CONFIG_PPC_86xx)
	530	static __be32 __iomem *rstcr;
	531
	532	static int __init setup_rstcr(void)
	533	{
	534	struct device_node *np;
	535	np = of_find_node_by_name(NULL, "global-utilities");
	536	if ((np && of_get_property(np, "fsl,has-rstcr", NULL))) {
	537	const u32 *prop = of_get_property(np, "reg", NULL);
	538	if (prop) {
	539	/* map reset control register
	540	* 0xE00B0 is offset of reset control register
	541	*/
	542	rstcr = ioremap(get_immrbase() + *prop + 0xB0, 0xff);
	543	if (!rstcr)
	544	printk (KERN_EMERG "Error: reset control "
	545	"register not mapped!\n");
	546	}
	547	} else
	548	printk (KERN_INFO "rstcr compatible register does not exist!\n");
	549	if (np)
	550	of_node_put(np);
	551	return 0;
	552	}
	553
	554	arch_initcall(setup_rstcr);
	555
	556	void fsl_rstcr_restart(char *cmd)
	557	{
	558	local_irq_disable();
	559	if (rstcr)
	560	/* set reset control register */
	561	out_be32(rstcr, 0x2); /* HRESET_REQ */
	562
	563	while (1) ;
	564	}
	565	#endif
6f90a8bd YS	566
6f90a8bd YS	567	#if defined(CONFIG_FB_FSL_DIU) \|\| defined(CONFIG_FB_FSL_DIU_MODULE)
43c9f434	568	struct platform_diu_data_ops diu_ops;
6f90a8bd	569	EXPORT_SYMBOL(diu_ops);
6f90a8bd	570	#endif