projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| daec962e PM |
1 | /* |
| 2 | * Support for indirect PCI bridges. | |
| 3 | * | |
| 4 | * Copyright (C) 1998 Gabriel Paubert. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License | |
| 8 | * as published by the Free Software Foundation; either version | |
| 9 | * 2 of the License, or (at your option) any later version. | |
| 10 | */ | |
| 11 | ||
| 12 | #include <linux/kernel.h> | |
| 13 | #include <linux/pci.h> | |
| 14 | #include <linux/delay.h> | |
| 15 | #include <linux/string.h> | |
| 16 | #include <linux/init.h> | |
| 17 | ||
| 18 | #include <asm/io.h> | |
| 19 | #include <asm/prom.h> | |
| 20 | #include <asm/pci-bridge.h> | |
| 21 | #include <asm/machdep.h> | |
| 22 | ||
| 23 | #ifdef CONFIG_PPC_INDIRECT_PCI_BE | |
| 24 | #define PCI_CFG_OUT out_be32 | |
| 25 | #else | |
| 26 | #define PCI_CFG_OUT out_le32 | |
| 27 | #endif | |
| 28 | ||
| 29 | static int | |
| 30 | indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
| 31 | int len, u32 *val) | |
| 32 | { | |
| 33 | struct pci_controller *hose = bus->sysdata; | |
| 34 | volatile void __iomem *cfg_data; | |
| 35 | u8 cfg_type = 0; | |
| 5ab65ecd | 36 | u32 bus_no; |
| daec962e PM |
37 | |
| 38 | if (ppc_md.pci_exclude_device) | |
| 7d52c7b0 | 39 | if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) |
| daec962e PM |
40 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 41 | ||
| 42 | if (hose->set_cfg_type) | |
| 43 | if (bus->number != hose->first_busno) | |
| 44 | cfg_type = 1; | |
| 45 | ||
| 5ab65ecd | 46 | bus_no = (bus->number == hose->first_busno) ? |
| 0a3786c5 | 47 | hose->self_busno : bus->number; |
| 5ab65ecd | 48 | |
| 7d52c7b0 | 49 | PCI_CFG_OUT(hose->cfg_addr, |
| 5ab65ecd | 50 | (0x80000000 | (bus_no << 16) |
| daec962e PM |
51 | | (devfn << 8) | ((offset & 0xfc) | cfg_type))); |
| 52 | ||
| 53 | /* | |
| 54 | * Note: the caller has already checked that offset is | |
| 55 | * suitably aligned and that len is 1, 2 or 4. | |
| 56 | */ | |
| 57 | cfg_data = hose->cfg_data + (offset & 3); | |
| 58 | switch (len) { | |
| 59 | case 1: | |
| 60 | *val = in_8(cfg_data); | |
| 61 | break; | |
| 62 | case 2: | |
| 63 | *val = in_le16(cfg_data); | |
| 64 | break; | |
| 65 | default: | |
| 66 | *val = in_le32(cfg_data); | |
| 67 | break; | |
| 68 | } | |
| 69 | return PCIBIOS_SUCCESSFUL; | |
| 70 | } | |
| 71 | ||
| 72 | static int | |
| 73 | indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
| 74 | int len, u32 val) | |
| 75 | { | |
| 76 | struct pci_controller *hose = bus->sysdata; | |
| 77 | volatile void __iomem *cfg_data; | |
| 78 | u8 cfg_type = 0; | |
| 5ab65ecd | 79 | u32 bus_no; |
| daec962e PM |
80 | |
| 81 | if (ppc_md.pci_exclude_device) | |
| 7d52c7b0 | 82 | if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) |
| daec962e PM |
83 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 84 | ||
| 85 | if (hose->set_cfg_type) | |
| 86 | if (bus->number != hose->first_busno) | |
| 87 | cfg_type = 1; | |
| 88 | ||
| 5ab65ecd | 89 | bus_no = (bus->number == hose->first_busno) ? |
| 0a3786c5 | 90 | hose->self_busno : bus->number; |
| 5ab65ecd | 91 | |
| 7d52c7b0 | 92 | PCI_CFG_OUT(hose->cfg_addr, |
| 5ab65ecd | 93 | (0x80000000 | (bus_no << 16) |
| daec962e PM |
94 | | (devfn << 8) | ((offset & 0xfc) | cfg_type))); |
| 95 | ||
| 96 | /* | |
| 97 | * Note: the caller has already checked that offset is | |
| 98 | * suitably aligned and that len is 1, 2 or 4. | |
| 99 | */ | |
| 100 | cfg_data = hose->cfg_data + (offset & 3); | |
| 101 | switch (len) { | |
| 102 | case 1: | |
| 103 | out_8(cfg_data, val); | |
| 104 | break; | |
| 105 | case 2: | |
| 106 | out_le16(cfg_data, val); | |
| 107 | break; | |
| 108 | default: | |
| 109 | out_le32(cfg_data, val); | |
| 110 | break; | |
| 111 | } | |
| 112 | return PCIBIOS_SUCCESSFUL; | |
| 113 | } | |
| 114 | ||
| 115 | static struct pci_ops indirect_pci_ops = | |
| 116 | { | |
| 117 | indirect_read_config, | |
| 118 | indirect_write_config | |
| 119 | }; | |
| 120 | ||
| 121 | void __init | |
| 122 | setup_indirect_pci_nomap(struct pci_controller* hose, void __iomem * cfg_addr, | |
| 123 | void __iomem * cfg_data) | |
| 124 | { | |
| 125 | hose->cfg_addr = cfg_addr; | |
| 126 | hose->cfg_data = cfg_data; | |
| 127 | hose->ops = &indirect_pci_ops; | |
| 128 | } | |
| 129 | ||
| 130 | void __init | |
| 131 | setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) | |
| 132 | { | |
| 133 | unsigned long base = cfg_addr & PAGE_MASK; | |
| 134 | void __iomem *mbase, *addr, *data; | |
| 135 | ||
| 136 | mbase = ioremap(base, PAGE_SIZE); | |
| 137 | addr = mbase + (cfg_addr & ~PAGE_MASK); | |
| 138 | if ((cfg_data & PAGE_MASK) != base) | |
| 139 | mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE); | |
| 140 | data = mbase + (cfg_data & ~PAGE_MASK); | |
| 141 | setup_indirect_pci_nomap(hose, addr, data); | |
| 142 | } |