Commit | Line | Data |
---|---|---|
f2a0bd37 | 1 | #include <linux/kernel.h> |
f2a0bd37 VB |
2 | #include <linux/stddef.h> |
3 | #include <linux/init.h> | |
4 | #include <linux/sched.h> | |
5 | #include <linux/signal.h> | |
6 | #include <linux/irq.h> | |
7 | #include <linux/dma-mapping.h> | |
8 | #include <asm/prom.h> | |
9 | #include <asm/irq.h> | |
10 | #include <asm/io.h> | |
11 | #include <asm/8xx_immap.h> | |
f2a0bd37 VB |
12 | |
13 | #include "mpc8xx_pic.h" | |
14 | ||
15 | ||
16 | #define PIC_VEC_SPURRIOUS 15 | |
17 | ||
18 | extern int cpm_get_irq(struct pt_regs *regs); | |
19 | ||
bae1d8f1 | 20 | static struct irq_domain *mpc8xx_pic_host; |
8751ed14 | 21 | static unsigned long mpc8xx_cached_irq_mask; |
fb533d0c | 22 | static sysconf8xx_t __iomem *siu_reg; |
f2a0bd37 | 23 | |
8751ed14 GL |
24 | static inline unsigned long mpc8xx_irqd_to_bit(struct irq_data *d) |
25 | { | |
26 | return 0x80000000 >> irqd_to_hwirq(d); | |
27 | } | |
f2a0bd37 | 28 | |
febd4017 | 29 | static void mpc8xx_unmask_irq(struct irq_data *d) |
f2a0bd37 | 30 | { |
8751ed14 GL |
31 | mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d); |
32 | out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); | |
f2a0bd37 VB |
33 | } |
34 | ||
febd4017 | 35 | static void mpc8xx_mask_irq(struct irq_data *d) |
f2a0bd37 | 36 | { |
8751ed14 GL |
37 | mpc8xx_cached_irq_mask &= ~mpc8xx_irqd_to_bit(d); |
38 | out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); | |
f2a0bd37 VB |
39 | } |
40 | ||
febd4017 | 41 | static void mpc8xx_ack(struct irq_data *d) |
f2a0bd37 | 42 | { |
8751ed14 | 43 | out_be32(&siu_reg->sc_sipend, mpc8xx_irqd_to_bit(d)); |
f2a0bd37 VB |
44 | } |
45 | ||
febd4017 | 46 | static void mpc8xx_end_irq(struct irq_data *d) |
f2a0bd37 | 47 | { |
8751ed14 GL |
48 | mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d); |
49 | out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); | |
f2a0bd37 VB |
50 | } |
51 | ||
febd4017 | 52 | static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) |
f2a0bd37 | 53 | { |
8751ed14 GL |
54 | /* only external IRQ senses are programmable */ |
55 | if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !(irqd_to_hwirq(d) & 1)) { | |
f2a0bd37 | 56 | unsigned int siel = in_be32(&siu_reg->sc_siel); |
8751ed14 GL |
57 | siel |= mpc8xx_irqd_to_bit(d); |
58 | out_be32(&siu_reg->sc_siel, siel); | |
59 | __irq_set_handler_locked(d->irq, handle_edge_irq); | |
f2a0bd37 VB |
60 | } |
61 | return 0; | |
62 | } | |
63 | ||
64 | static struct irq_chip mpc8xx_pic = { | |
fc380c0c | 65 | .name = "MPC8XX SIU", |
febd4017 LB |
66 | .irq_unmask = mpc8xx_unmask_irq, |
67 | .irq_mask = mpc8xx_mask_irq, | |
68 | .irq_ack = mpc8xx_ack, | |
69 | .irq_eoi = mpc8xx_end_irq, | |
70 | .irq_set_type = mpc8xx_set_irq_type, | |
f2a0bd37 VB |
71 | }; |
72 | ||
73 | unsigned int mpc8xx_get_irq(void) | |
74 | { | |
75 | int irq; | |
76 | ||
77 | /* For MPC8xx, read the SIVEC register and shift the bits down | |
78 | * to get the irq number. | |
79 | */ | |
80 | irq = in_be32(&siu_reg->sc_sivec) >> 26; | |
81 | ||
82 | if (irq == PIC_VEC_SPURRIOUS) | |
83 | irq = NO_IRQ; | |
84 | ||
85 | return irq_linear_revmap(mpc8xx_pic_host, irq); | |
86 | ||
87 | } | |
88 | ||
bae1d8f1 | 89 | static int mpc8xx_pic_host_map(struct irq_domain *h, unsigned int virq, |
f2a0bd37 VB |
90 | irq_hw_number_t hw) |
91 | { | |
92 | pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw); | |
93 | ||
94 | /* Set default irq handle */ | |
ec775d0e | 95 | irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq); |
f2a0bd37 VB |
96 | return 0; |
97 | } | |
98 | ||
99 | ||
bae1d8f1 | 100 | static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct, |
40d50cf7 | 101 | const u32 *intspec, unsigned int intsize, |
f2a0bd37 VB |
102 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
103 | { | |
104 | static unsigned char map_pic_senses[4] = { | |
105 | IRQ_TYPE_EDGE_RISING, | |
106 | IRQ_TYPE_LEVEL_LOW, | |
107 | IRQ_TYPE_LEVEL_HIGH, | |
108 | IRQ_TYPE_EDGE_FALLING, | |
109 | }; | |
110 | ||
8751ed14 GL |
111 | if (intspec[0] > 0x1f) |
112 | return 0; | |
113 | ||
f2a0bd37 VB |
114 | *out_hwirq = intspec[0]; |
115 | if (intsize > 1 && intspec[1] < 4) | |
116 | *out_flags = map_pic_senses[intspec[1]]; | |
117 | else | |
118 | *out_flags = IRQ_TYPE_NONE; | |
119 | ||
120 | return 0; | |
121 | } | |
122 | ||
123 | ||
bae1d8f1 | 124 | static struct irq_domain_ops mpc8xx_pic_host_ops = { |
f2a0bd37 VB |
125 | .map = mpc8xx_pic_host_map, |
126 | .xlate = mpc8xx_pic_host_xlate, | |
127 | }; | |
128 | ||
129 | int mpc8xx_pic_init(void) | |
130 | { | |
131 | struct resource res; | |
fb533d0c | 132 | struct device_node *np; |
f2a0bd37 VB |
133 | int ret; |
134 | ||
fb533d0c SW |
135 | np = of_find_compatible_node(NULL, NULL, "fsl,pq1-pic"); |
136 | if (np == NULL) | |
137 | np = of_find_node_by_type(NULL, "mpc8xx-pic"); | |
f2a0bd37 | 138 | if (np == NULL) { |
fb533d0c | 139 | printk(KERN_ERR "Could not find fsl,pq1-pic node\n"); |
f2a0bd37 VB |
140 | return -ENOMEM; |
141 | } | |
142 | ||
f2a0bd37 | 143 | ret = of_address_to_resource(np, 0, &res); |
f2a0bd37 | 144 | if (ret) |
52964f87 | 145 | goto out; |
f2a0bd37 | 146 | |
28f65c11 | 147 | siu_reg = ioremap(res.start, resource_size(&res)); |
b1725c93 JL |
148 | if (siu_reg == NULL) { |
149 | ret = -EINVAL; | |
150 | goto out; | |
151 | } | |
f2a0bd37 | 152 | |
a8db8cf0 | 153 | mpc8xx_pic_host = irq_domain_add_linear(np, 64, &mpc8xx_pic_host_ops, NULL); |
f2a0bd37 VB |
154 | if (mpc8xx_pic_host == NULL) { |
155 | printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n"); | |
156 | ret = -ENOMEM; | |
b1725c93 | 157 | goto out; |
f2a0bd37 | 158 | } |
b1725c93 | 159 | return 0; |
f2a0bd37 | 160 | |
52964f87 ME |
161 | out: |
162 | of_node_put(np); | |
f2a0bd37 VB |
163 | return ret; |
164 | } |