Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * arch/powerpc/kernel/mpic.c | |
3 | * | |
4 | * Driver for interrupt controllers following the OpenPIC standard, the | |
446957ba | 5 | * common implementation being IBM's MPIC. This driver also can deal |
14cf11af PM |
6 | * with various broken implementations of this HW. |
7 | * | |
8 | * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. | |
03bcb7e3 | 9 | * Copyright 2010-2012 Freescale Semiconductor, Inc. |
14cf11af PM |
10 | * |
11 | * This file is subject to the terms and conditions of the GNU General Public | |
12 | * License. See the file COPYING in the main directory of this archive | |
13 | * for more details. | |
14 | */ | |
15 | ||
16 | #undef DEBUG | |
1beb6a7d BH |
17 | #undef DEBUG_IPI |
18 | #undef DEBUG_IRQ | |
19 | #undef DEBUG_LOW | |
14cf11af | 20 | |
14cf11af PM |
21 | #include <linux/types.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/smp.h> | |
26 | #include <linux/interrupt.h> | |
14cf11af PM |
27 | #include <linux/spinlock.h> |
28 | #include <linux/pci.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
f5a592f7 | 30 | #include <linux/syscore_ops.h> |
76462232 | 31 | #include <linux/ratelimit.h> |
14cf11af PM |
32 | |
33 | #include <asm/ptrace.h> | |
34 | #include <asm/signal.h> | |
35 | #include <asm/io.h> | |
36 | #include <asm/pgtable.h> | |
37 | #include <asm/irq.h> | |
38 | #include <asm/machdep.h> | |
39 | #include <asm/mpic.h> | |
40 | #include <asm/smp.h> | |
41 | ||
a7de7c74 ME |
42 | #include "mpic.h" |
43 | ||
14cf11af PM |
44 | #ifdef DEBUG |
45 | #define DBG(fmt...) printk(fmt) | |
46 | #else | |
47 | #define DBG(fmt...) | |
48 | #endif | |
49 | ||
9e6f31a9 D |
50 | struct bus_type mpic_subsys = { |
51 | .name = "mpic", | |
52 | .dev_name = "mpic", | |
53 | }; | |
54 | EXPORT_SYMBOL_GPL(mpic_subsys); | |
55 | ||
14cf11af PM |
56 | static struct mpic *mpics; |
57 | static struct mpic *mpic_primary; | |
203041ad | 58 | static DEFINE_RAW_SPINLOCK(mpic_lock); |
14cf11af | 59 | |
c0c0d996 | 60 | #ifdef CONFIG_PPC32 /* XXX for now */ |
e40c7f02 | 61 | #ifdef CONFIG_IRQ_ALL_CPUS |
e242114a | 62 | #define distribute_irqs (1) |
e40c7f02 AW |
63 | #else |
64 | #define distribute_irqs (0) | |
65 | #endif | |
c0c0d996 | 66 | #endif |
14cf11af | 67 | |
7233593b ZR |
68 | #ifdef CONFIG_MPIC_WEIRD |
69 | static u32 mpic_infos[][MPIC_IDX_END] = { | |
70 | [0] = { /* Original OpenPIC compatible MPIC */ | |
71 | MPIC_GREG_BASE, | |
72 | MPIC_GREG_FEATURE_0, | |
73 | MPIC_GREG_GLOBAL_CONF_0, | |
74 | MPIC_GREG_VENDOR_ID, | |
75 | MPIC_GREG_IPI_VECTOR_PRI_0, | |
76 | MPIC_GREG_IPI_STRIDE, | |
77 | MPIC_GREG_SPURIOUS, | |
78 | MPIC_GREG_TIMER_FREQ, | |
79 | ||
80 | MPIC_TIMER_BASE, | |
81 | MPIC_TIMER_STRIDE, | |
82 | MPIC_TIMER_CURRENT_CNT, | |
83 | MPIC_TIMER_BASE_CNT, | |
84 | MPIC_TIMER_VECTOR_PRI, | |
85 | MPIC_TIMER_DESTINATION, | |
86 | ||
87 | MPIC_CPU_BASE, | |
88 | MPIC_CPU_STRIDE, | |
89 | MPIC_CPU_IPI_DISPATCH_0, | |
90 | MPIC_CPU_IPI_DISPATCH_STRIDE, | |
91 | MPIC_CPU_CURRENT_TASK_PRI, | |
92 | MPIC_CPU_WHOAMI, | |
93 | MPIC_CPU_INTACK, | |
94 | MPIC_CPU_EOI, | |
f365355e | 95 | MPIC_CPU_MCACK, |
7233593b ZR |
96 | |
97 | MPIC_IRQ_BASE, | |
98 | MPIC_IRQ_STRIDE, | |
99 | MPIC_IRQ_VECTOR_PRI, | |
100 | MPIC_VECPRI_VECTOR_MASK, | |
101 | MPIC_VECPRI_POLARITY_POSITIVE, | |
102 | MPIC_VECPRI_POLARITY_NEGATIVE, | |
103 | MPIC_VECPRI_SENSE_LEVEL, | |
104 | MPIC_VECPRI_SENSE_EDGE, | |
105 | MPIC_VECPRI_POLARITY_MASK, | |
106 | MPIC_VECPRI_SENSE_MASK, | |
107 | MPIC_IRQ_DESTINATION | |
108 | }, | |
109 | [1] = { /* Tsi108/109 PIC */ | |
110 | TSI108_GREG_BASE, | |
111 | TSI108_GREG_FEATURE_0, | |
112 | TSI108_GREG_GLOBAL_CONF_0, | |
113 | TSI108_GREG_VENDOR_ID, | |
114 | TSI108_GREG_IPI_VECTOR_PRI_0, | |
115 | TSI108_GREG_IPI_STRIDE, | |
116 | TSI108_GREG_SPURIOUS, | |
117 | TSI108_GREG_TIMER_FREQ, | |
118 | ||
119 | TSI108_TIMER_BASE, | |
120 | TSI108_TIMER_STRIDE, | |
121 | TSI108_TIMER_CURRENT_CNT, | |
122 | TSI108_TIMER_BASE_CNT, | |
123 | TSI108_TIMER_VECTOR_PRI, | |
124 | TSI108_TIMER_DESTINATION, | |
125 | ||
126 | TSI108_CPU_BASE, | |
127 | TSI108_CPU_STRIDE, | |
128 | TSI108_CPU_IPI_DISPATCH_0, | |
129 | TSI108_CPU_IPI_DISPATCH_STRIDE, | |
130 | TSI108_CPU_CURRENT_TASK_PRI, | |
131 | TSI108_CPU_WHOAMI, | |
132 | TSI108_CPU_INTACK, | |
133 | TSI108_CPU_EOI, | |
f365355e | 134 | TSI108_CPU_MCACK, |
7233593b ZR |
135 | |
136 | TSI108_IRQ_BASE, | |
137 | TSI108_IRQ_STRIDE, | |
138 | TSI108_IRQ_VECTOR_PRI, | |
139 | TSI108_VECPRI_VECTOR_MASK, | |
140 | TSI108_VECPRI_POLARITY_POSITIVE, | |
141 | TSI108_VECPRI_POLARITY_NEGATIVE, | |
142 | TSI108_VECPRI_SENSE_LEVEL, | |
143 | TSI108_VECPRI_SENSE_EDGE, | |
144 | TSI108_VECPRI_POLARITY_MASK, | |
145 | TSI108_VECPRI_SENSE_MASK, | |
146 | TSI108_IRQ_DESTINATION | |
147 | }, | |
148 | }; | |
149 | ||
150 | #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] | |
151 | ||
152 | #else /* CONFIG_MPIC_WEIRD */ | |
153 | ||
154 | #define MPIC_INFO(name) MPIC_##name | |
155 | ||
156 | #endif /* CONFIG_MPIC_WEIRD */ | |
157 | ||
d6a2639b MI |
158 | static inline unsigned int mpic_processor_id(struct mpic *mpic) |
159 | { | |
160 | unsigned int cpu = 0; | |
161 | ||
be8bec56 | 162 | if (!(mpic->flags & MPIC_SECONDARY)) |
d6a2639b MI |
163 | cpu = hard_smp_processor_id(); |
164 | ||
165 | return cpu; | |
166 | } | |
167 | ||
14cf11af PM |
168 | /* |
169 | * Register accessor functions | |
170 | */ | |
171 | ||
172 | ||
fbf0274e BH |
173 | static inline u32 _mpic_read(enum mpic_reg_type type, |
174 | struct mpic_reg_bank *rb, | |
175 | unsigned int reg) | |
14cf11af | 176 | { |
fbf0274e BH |
177 | switch(type) { |
178 | #ifdef CONFIG_PPC_DCR | |
179 | case mpic_access_dcr: | |
83f34df4 | 180 | return dcr_read(rb->dhost, reg); |
fbf0274e BH |
181 | #endif |
182 | case mpic_access_mmio_be: | |
183 | return in_be32(rb->base + (reg >> 2)); | |
184 | case mpic_access_mmio_le: | |
185 | default: | |
186 | return in_le32(rb->base + (reg >> 2)); | |
187 | } | |
14cf11af PM |
188 | } |
189 | ||
fbf0274e BH |
190 | static inline void _mpic_write(enum mpic_reg_type type, |
191 | struct mpic_reg_bank *rb, | |
192 | unsigned int reg, u32 value) | |
14cf11af | 193 | { |
fbf0274e BH |
194 | switch(type) { |
195 | #ifdef CONFIG_PPC_DCR | |
196 | case mpic_access_dcr: | |
d9d1063d JB |
197 | dcr_write(rb->dhost, reg, value); |
198 | break; | |
fbf0274e BH |
199 | #endif |
200 | case mpic_access_mmio_be: | |
d9d1063d JB |
201 | out_be32(rb->base + (reg >> 2), value); |
202 | break; | |
fbf0274e BH |
203 | case mpic_access_mmio_le: |
204 | default: | |
d9d1063d JB |
205 | out_le32(rb->base + (reg >> 2), value); |
206 | break; | |
fbf0274e | 207 | } |
14cf11af PM |
208 | } |
209 | ||
210 | static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) | |
211 | { | |
fbf0274e | 212 | enum mpic_reg_type type = mpic->reg_type; |
7233593b ZR |
213 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
214 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 215 | |
fbf0274e BH |
216 | if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) |
217 | type = mpic_access_mmio_be; | |
218 | return _mpic_read(type, &mpic->gregs, offset); | |
14cf11af PM |
219 | } |
220 | ||
221 | static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) | |
222 | { | |
7233593b ZR |
223 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
224 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 225 | |
fbf0274e | 226 | _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); |
14cf11af PM |
227 | } |
228 | ||
03bcb7e3 | 229 | static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm) |
ea94187f | 230 | { |
03bcb7e3 VS |
231 | return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE + |
232 | (tm & 3) * MPIC_INFO(TIMER_STRIDE); | |
233 | } | |
ea94187f | 234 | |
03bcb7e3 VS |
235 | static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm) |
236 | { | |
237 | unsigned int offset = mpic_tm_offset(mpic, tm) + | |
238 | MPIC_INFO(TIMER_VECTOR_PRI); | |
ea94187f SW |
239 | |
240 | return _mpic_read(mpic->reg_type, &mpic->tmregs, offset); | |
241 | } | |
242 | ||
243 | static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value) | |
244 | { | |
03bcb7e3 VS |
245 | unsigned int offset = mpic_tm_offset(mpic, tm) + |
246 | MPIC_INFO(TIMER_VECTOR_PRI); | |
ea94187f SW |
247 | |
248 | _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value); | |
249 | } | |
250 | ||
14cf11af PM |
251 | static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) |
252 | { | |
d6a2639b | 253 | unsigned int cpu = mpic_processor_id(mpic); |
14cf11af | 254 | |
fbf0274e | 255 | return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); |
14cf11af PM |
256 | } |
257 | ||
258 | static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) | |
259 | { | |
d6a2639b | 260 | unsigned int cpu = mpic_processor_id(mpic); |
14cf11af | 261 | |
fbf0274e | 262 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); |
14cf11af PM |
263 | } |
264 | ||
265 | static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) | |
266 | { | |
267 | unsigned int isu = src_no >> mpic->isu_shift; | |
268 | unsigned int idx = src_no & mpic->isu_mask; | |
11a6b292 | 269 | unsigned int val; |
14cf11af | 270 | |
11a6b292 ME |
271 | val = _mpic_read(mpic->reg_type, &mpic->isus[isu], |
272 | reg + (idx * MPIC_INFO(IRQ_STRIDE))); | |
0d72ba93 OJ |
273 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
274 | if (reg == 0) | |
11a6b292 ME |
275 | val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | |
276 | mpic->isu_reg0_shadow[src_no]; | |
0d72ba93 | 277 | #endif |
11a6b292 | 278 | return val; |
14cf11af PM |
279 | } |
280 | ||
281 | static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, | |
282 | unsigned int reg, u32 value) | |
283 | { | |
284 | unsigned int isu = src_no >> mpic->isu_shift; | |
285 | unsigned int idx = src_no & mpic->isu_mask; | |
286 | ||
fbf0274e | 287 | _mpic_write(mpic->reg_type, &mpic->isus[isu], |
7233593b | 288 | reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); |
0d72ba93 OJ |
289 | |
290 | #ifdef CONFIG_MPIC_BROKEN_REGREAD | |
291 | if (reg == 0) | |
11a6b292 ME |
292 | mpic->isu_reg0_shadow[src_no] = |
293 | value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY); | |
0d72ba93 | 294 | #endif |
14cf11af PM |
295 | } |
296 | ||
fbf0274e BH |
297 | #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) |
298 | #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) | |
14cf11af PM |
299 | #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) |
300 | #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) | |
ea94187f SW |
301 | #define mpic_tm_read(i) _mpic_tm_read(mpic,(i)) |
302 | #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v)) | |
14cf11af PM |
303 | #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) |
304 | #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) | |
305 | #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) | |
306 | #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) | |
307 | ||
308 | ||
309 | /* | |
310 | * Low level utility functions | |
311 | */ | |
312 | ||
313 | ||
c51a3fdc | 314 | static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, |
fbf0274e BH |
315 | struct mpic_reg_bank *rb, unsigned int offset, |
316 | unsigned int size) | |
317 | { | |
318 | rb->base = ioremap(phys_addr + offset, size); | |
319 | BUG_ON(rb->base == NULL); | |
320 | } | |
321 | ||
322 | #ifdef CONFIG_PPC_DCR | |
c51242e7 | 323 | static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, |
fbf0274e BH |
324 | unsigned int offset, unsigned int size) |
325 | { | |
c51242e7 | 326 | phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0); |
e62b7601 | 327 | rb->dhost = dcr_map(mpic->node, phys_addr + offset, size); |
fbf0274e BH |
328 | BUG_ON(!DCR_MAP_OK(rb->dhost)); |
329 | } | |
330 | ||
c51242e7 | 331 | static inline void mpic_map(struct mpic *mpic, |
5a2642f6 BH |
332 | phys_addr_t phys_addr, struct mpic_reg_bank *rb, |
333 | unsigned int offset, unsigned int size) | |
fbf0274e BH |
334 | { |
335 | if (mpic->flags & MPIC_USES_DCR) | |
c51242e7 | 336 | _mpic_map_dcr(mpic, rb, offset, size); |
fbf0274e BH |
337 | else |
338 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); | |
339 | } | |
340 | #else /* CONFIG_PPC_DCR */ | |
c51242e7 | 341 | #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) |
fbf0274e BH |
342 | #endif /* !CONFIG_PPC_DCR */ |
343 | ||
344 | ||
14cf11af PM |
345 | |
346 | /* Check if we have one of those nice broken MPICs with a flipped endian on | |
347 | * reads from IPI registers | |
348 | */ | |
349 | static void __init mpic_test_broken_ipi(struct mpic *mpic) | |
350 | { | |
351 | u32 r; | |
352 | ||
7233593b ZR |
353 | mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); |
354 | r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); | |
14cf11af PM |
355 | |
356 | if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { | |
357 | printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); | |
358 | mpic->flags |= MPIC_BROKEN_IPI; | |
359 | } | |
360 | } | |
361 | ||
6cfef5b2 | 362 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
14cf11af PM |
363 | |
364 | /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) | |
365 | * to force the edge setting on the MPIC and do the ack workaround. | |
366 | */ | |
1beb6a7d | 367 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) |
14cf11af | 368 | { |
1beb6a7d | 369 | if (source >= 128 || !mpic->fixups) |
14cf11af | 370 | return 0; |
1beb6a7d | 371 | return mpic->fixups[source].base != NULL; |
14cf11af PM |
372 | } |
373 | ||
c4b22f26 | 374 | |
1beb6a7d | 375 | static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) |
14cf11af | 376 | { |
1beb6a7d | 377 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
14cf11af | 378 | |
1beb6a7d BH |
379 | if (fixup->applebase) { |
380 | unsigned int soff = (fixup->index >> 3) & ~3; | |
381 | unsigned int mask = 1U << (fixup->index & 0x1f); | |
382 | writel(mask, fixup->applebase + soff); | |
383 | } else { | |
203041ad | 384 | raw_spin_lock(&mpic->fixup_lock); |
1beb6a7d BH |
385 | writeb(0x11 + 2 * fixup->index, fixup->base + 2); |
386 | writel(fixup->data, fixup->base + 4); | |
203041ad | 387 | raw_spin_unlock(&mpic->fixup_lock); |
1beb6a7d | 388 | } |
14cf11af PM |
389 | } |
390 | ||
1beb6a7d | 391 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, |
24a3f2e8 | 392 | bool level) |
1beb6a7d BH |
393 | { |
394 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
395 | unsigned long flags; | |
396 | u32 tmp; | |
397 | ||
398 | if (fixup->base == NULL) | |
399 | return; | |
400 | ||
24a3f2e8 TG |
401 | DBG("startup_ht_interrupt(0x%x) index: %d\n", |
402 | source, fixup->index); | |
203041ad | 403 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
1beb6a7d BH |
404 | /* Enable and configure */ |
405 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
406 | tmp = readl(fixup->base + 4); | |
407 | tmp &= ~(0x23U); | |
24a3f2e8 | 408 | if (level) |
1beb6a7d BH |
409 | tmp |= 0x22; |
410 | writel(tmp, fixup->base + 4); | |
203041ad | 411 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
3669e930 JB |
412 | |
413 | #ifdef CONFIG_PM | |
414 | /* use the lowest bit inverted to the actual HW, | |
415 | * set if this fixup was enabled, clear otherwise */ | |
416 | mpic->save_data[source].fixup_data = tmp | 1; | |
417 | #endif | |
1beb6a7d BH |
418 | } |
419 | ||
24a3f2e8 | 420 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source) |
1beb6a7d BH |
421 | { |
422 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
423 | unsigned long flags; | |
424 | u32 tmp; | |
425 | ||
426 | if (fixup->base == NULL) | |
427 | return; | |
428 | ||
24a3f2e8 | 429 | DBG("shutdown_ht_interrupt(0x%x)\n", source); |
1beb6a7d BH |
430 | |
431 | /* Disable */ | |
203041ad | 432 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
1beb6a7d BH |
433 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
434 | tmp = readl(fixup->base + 4); | |
72b13819 | 435 | tmp |= 1; |
1beb6a7d | 436 | writel(tmp, fixup->base + 4); |
203041ad | 437 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
3669e930 JB |
438 | |
439 | #ifdef CONFIG_PM | |
440 | /* use the lowest bit inverted to the actual HW, | |
441 | * set if this fixup was enabled, clear otherwise */ | |
442 | mpic->save_data[source].fixup_data = tmp & ~1; | |
443 | #endif | |
1beb6a7d | 444 | } |
14cf11af | 445 | |
812fd1fd ME |
446 | #ifdef CONFIG_PCI_MSI |
447 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, | |
448 | unsigned int devfn) | |
449 | { | |
450 | u8 __iomem *base; | |
451 | u8 pos, flags; | |
452 | u64 addr = 0; | |
453 | ||
454 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; | |
455 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
456 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
457 | if (id == PCI_CAP_ID_HT) { | |
458 | id = readb(devbase + pos + 3); | |
459 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) | |
460 | break; | |
461 | } | |
462 | } | |
463 | ||
464 | if (pos == 0) | |
465 | return; | |
466 | ||
467 | base = devbase + pos; | |
468 | ||
469 | flags = readb(base + HT_MSI_FLAGS); | |
470 | if (!(flags & HT_MSI_FLAGS_FIXED)) { | |
471 | addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; | |
472 | addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); | |
473 | } | |
474 | ||
fe333321 | 475 | printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", |
812fd1fd ME |
476 | PCI_SLOT(devfn), PCI_FUNC(devfn), |
477 | flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); | |
478 | ||
479 | if (!(flags & HT_MSI_FLAGS_ENABLE)) | |
480 | writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); | |
481 | } | |
482 | #else | |
483 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, | |
484 | unsigned int devfn) | |
485 | { | |
486 | return; | |
487 | } | |
488 | #endif | |
489 | ||
1beb6a7d BH |
490 | static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, |
491 | unsigned int devfn, u32 vdid) | |
14cf11af | 492 | { |
c4b22f26 | 493 | int i, irq, n; |
1beb6a7d | 494 | u8 __iomem *base; |
14cf11af | 495 | u32 tmp; |
c4b22f26 | 496 | u8 pos; |
14cf11af | 497 | |
1beb6a7d BH |
498 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; |
499 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
500 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
46ff3463 | 501 | if (id == PCI_CAP_ID_HT) { |
c4b22f26 | 502 | id = readb(devbase + pos + 3); |
beb7cc82 | 503 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) |
c4b22f26 SB |
504 | break; |
505 | } | |
14cf11af | 506 | } |
c4b22f26 SB |
507 | if (pos == 0) |
508 | return; | |
509 | ||
1beb6a7d BH |
510 | base = devbase + pos; |
511 | writeb(0x01, base + 2); | |
512 | n = (readl(base + 4) >> 16) & 0xff; | |
14cf11af | 513 | |
1beb6a7d BH |
514 | printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" |
515 | " has %d irqs\n", | |
516 | devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); | |
c4b22f26 SB |
517 | |
518 | for (i = 0; i <= n; i++) { | |
1beb6a7d BH |
519 | writeb(0x10 + 2 * i, base + 2); |
520 | tmp = readl(base + 4); | |
14cf11af | 521 | irq = (tmp >> 16) & 0xff; |
1beb6a7d BH |
522 | DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); |
523 | /* mask it , will be unmasked later */ | |
524 | tmp |= 0x1; | |
525 | writel(tmp, base + 4); | |
526 | mpic->fixups[irq].index = i; | |
527 | mpic->fixups[irq].base = base; | |
528 | /* Apple HT PIC has a non-standard way of doing EOIs */ | |
529 | if ((vdid & 0xffff) == 0x106b) | |
530 | mpic->fixups[irq].applebase = devbase + 0x60; | |
531 | else | |
532 | mpic->fixups[irq].applebase = NULL; | |
533 | writeb(0x11 + 2 * i, base + 2); | |
534 | mpic->fixups[irq].data = readl(base + 4) | 0x80000000; | |
14cf11af PM |
535 | } |
536 | } | |
26a2056e | 537 | |
c4b22f26 | 538 | |
1beb6a7d | 539 | static void __init mpic_scan_ht_pics(struct mpic *mpic) |
14cf11af PM |
540 | { |
541 | unsigned int devfn; | |
542 | u8 __iomem *cfgspace; | |
543 | ||
1beb6a7d | 544 | printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); |
14cf11af PM |
545 | |
546 | /* Allocate fixups array */ | |
ea96025a | 547 | mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL); |
14cf11af | 548 | BUG_ON(mpic->fixups == NULL); |
14cf11af PM |
549 | |
550 | /* Init spinlock */ | |
203041ad | 551 | raw_spin_lock_init(&mpic->fixup_lock); |
14cf11af | 552 | |
c4b22f26 SB |
553 | /* Map U3 config space. We assume all IO-APICs are on the primary bus |
554 | * so we only need to map 64kB. | |
14cf11af | 555 | */ |
c4b22f26 | 556 | cfgspace = ioremap(0xf2000000, 0x10000); |
14cf11af PM |
557 | BUG_ON(cfgspace == NULL); |
558 | ||
1beb6a7d BH |
559 | /* Now we scan all slots. We do a very quick scan, we read the header |
560 | * type, vendor ID and device ID only, that's plenty enough | |
14cf11af | 561 | */ |
c4b22f26 | 562 | for (devfn = 0; devfn < 0x100; devfn++) { |
14cf11af PM |
563 | u8 __iomem *devbase = cfgspace + (devfn << 8); |
564 | u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); | |
565 | u32 l = readl(devbase + PCI_VENDOR_ID); | |
1beb6a7d | 566 | u16 s; |
14cf11af PM |
567 | |
568 | DBG("devfn %x, l: %x\n", devfn, l); | |
569 | ||
570 | /* If no device, skip */ | |
571 | if (l == 0xffffffff || l == 0x00000000 || | |
572 | l == 0x0000ffff || l == 0xffff0000) | |
573 | goto next; | |
1beb6a7d BH |
574 | /* Check if is supports capability lists */ |
575 | s = readw(devbase + PCI_STATUS); | |
576 | if (!(s & PCI_STATUS_CAP_LIST)) | |
577 | goto next; | |
14cf11af | 578 | |
1beb6a7d | 579 | mpic_scan_ht_pic(mpic, devbase, devfn, l); |
812fd1fd | 580 | mpic_scan_ht_msi(mpic, devbase, devfn); |
c4b22f26 | 581 | |
14cf11af PM |
582 | next: |
583 | /* next device, if function 0 */ | |
c4b22f26 | 584 | if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) |
14cf11af PM |
585 | devfn += 7; |
586 | } | |
587 | } | |
588 | ||
6cfef5b2 | 589 | #else /* CONFIG_MPIC_U3_HT_IRQS */ |
6e99e458 BH |
590 | |
591 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) | |
592 | { | |
593 | return 0; | |
594 | } | |
595 | ||
596 | static void __init mpic_scan_ht_pics(struct mpic *mpic) | |
597 | { | |
598 | } | |
599 | ||
6cfef5b2 | 600 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
14cf11af | 601 | |
14cf11af | 602 | /* Find an mpic associated with a given linux interrupt */ |
d69a78d7 | 603 | static struct mpic *mpic_find(unsigned int irq) |
14cf11af | 604 | { |
0ebfff14 BH |
605 | if (irq < NUM_ISA_INTERRUPTS) |
606 | return NULL; | |
7df2457d | 607 | |
ec775d0e | 608 | return irq_get_chip_data(irq); |
d69a78d7 | 609 | } |
7df2457d | 610 | |
d69a78d7 | 611 | /* Determine if the linux irq is an IPI */ |
3a2b4f7c | 612 | static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src) |
d69a78d7 | 613 | { |
d69a78d7 | 614 | return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); |
14cf11af PM |
615 | } |
616 | ||
ea94187f | 617 | /* Determine if the linux irq is a timer */ |
3a2b4f7c | 618 | static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src) |
ea94187f | 619 | { |
ea94187f SW |
620 | return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]); |
621 | } | |
d69a78d7 | 622 | |
14cf11af PM |
623 | /* Convert a cpu mask from logical to physical cpu numbers. */ |
624 | static inline u32 mpic_physmask(u32 cpumask) | |
625 | { | |
626 | int i; | |
627 | u32 mask = 0; | |
628 | ||
ebc04215 | 629 | for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1) |
14cf11af PM |
630 | mask |= (cpumask & 1) << get_hard_smp_processor_id(i); |
631 | return mask; | |
632 | } | |
633 | ||
634 | #ifdef CONFIG_SMP | |
635 | /* Get the mpic structure from the IPI number */ | |
835c0553 | 636 | static inline struct mpic * mpic_from_ipi(struct irq_data *d) |
14cf11af | 637 | { |
835c0553 | 638 | return irq_data_get_irq_chip_data(d); |
14cf11af PM |
639 | } |
640 | #endif | |
641 | ||
642 | /* Get the mpic structure from the irq number */ | |
643 | static inline struct mpic * mpic_from_irq(unsigned int irq) | |
644 | { | |
ec775d0e | 645 | return irq_get_chip_data(irq); |
835c0553 LB |
646 | } |
647 | ||
648 | /* Get the mpic structure from the irq data */ | |
649 | static inline struct mpic * mpic_from_irq_data(struct irq_data *d) | |
650 | { | |
651 | return irq_data_get_irq_chip_data(d); | |
14cf11af PM |
652 | } |
653 | ||
654 | /* Send an EOI */ | |
655 | static inline void mpic_eoi(struct mpic *mpic) | |
656 | { | |
7233593b | 657 | mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); |
14cf11af PM |
658 | } |
659 | ||
14cf11af PM |
660 | /* |
661 | * Linux descriptor level callbacks | |
662 | */ | |
663 | ||
664 | ||
835c0553 | 665 | void mpic_unmask_irq(struct irq_data *d) |
14cf11af PM |
666 | { |
667 | unsigned int loops = 100000; | |
835c0553 | 668 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 669 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 670 | |
835c0553 | 671 | DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); |
14cf11af | 672 | |
7233593b ZR |
673 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
674 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & | |
e5356640 | 675 | ~MPIC_VECPRI_MASK); |
14cf11af PM |
676 | /* make sure mask gets to controller before we return to user */ |
677 | do { | |
678 | if (!loops--) { | |
8bfc5e36 SW |
679 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
680 | __func__, src); | |
14cf11af PM |
681 | break; |
682 | } | |
7233593b | 683 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); |
14cf11af PM |
684 | } |
685 | ||
835c0553 | 686 | void mpic_mask_irq(struct irq_data *d) |
14cf11af PM |
687 | { |
688 | unsigned int loops = 100000; | |
835c0553 | 689 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 690 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 691 | |
835c0553 | 692 | DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); |
14cf11af | 693 | |
7233593b ZR |
694 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
695 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | | |
e5356640 | 696 | MPIC_VECPRI_MASK); |
14cf11af PM |
697 | |
698 | /* make sure mask gets to controller before we return to user */ | |
699 | do { | |
700 | if (!loops--) { | |
8bfc5e36 SW |
701 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
702 | __func__, src); | |
14cf11af PM |
703 | break; |
704 | } | |
7233593b | 705 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); |
14cf11af PM |
706 | } |
707 | ||
835c0553 | 708 | void mpic_end_irq(struct irq_data *d) |
1beb6a7d | 709 | { |
835c0553 | 710 | struct mpic *mpic = mpic_from_irq_data(d); |
b9e5b4e6 BH |
711 | |
712 | #ifdef DEBUG_IRQ | |
835c0553 | 713 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
b9e5b4e6 BH |
714 | #endif |
715 | /* We always EOI on end_irq() even for edge interrupts since that | |
716 | * should only lower the priority, the MPIC should have properly | |
717 | * latched another edge interrupt coming in anyway | |
718 | */ | |
719 | ||
720 | mpic_eoi(mpic); | |
721 | } | |
722 | ||
6cfef5b2 | 723 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 724 | |
835c0553 | 725 | static void mpic_unmask_ht_irq(struct irq_data *d) |
b9e5b4e6 | 726 | { |
835c0553 | 727 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 728 | unsigned int src = irqd_to_hwirq(d); |
1beb6a7d | 729 | |
835c0553 | 730 | mpic_unmask_irq(d); |
1beb6a7d | 731 | |
24a3f2e8 | 732 | if (irqd_is_level_type(d)) |
b9e5b4e6 BH |
733 | mpic_ht_end_irq(mpic, src); |
734 | } | |
735 | ||
835c0553 | 736 | static unsigned int mpic_startup_ht_irq(struct irq_data *d) |
b9e5b4e6 | 737 | { |
835c0553 | 738 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 739 | unsigned int src = irqd_to_hwirq(d); |
1beb6a7d | 740 | |
835c0553 | 741 | mpic_unmask_irq(d); |
24a3f2e8 | 742 | mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d)); |
b9e5b4e6 BH |
743 | |
744 | return 0; | |
1beb6a7d BH |
745 | } |
746 | ||
835c0553 | 747 | static void mpic_shutdown_ht_irq(struct irq_data *d) |
b9e5b4e6 | 748 | { |
835c0553 | 749 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 750 | unsigned int src = irqd_to_hwirq(d); |
b9e5b4e6 | 751 | |
24a3f2e8 | 752 | mpic_shutdown_ht_interrupt(mpic, src); |
835c0553 | 753 | mpic_mask_irq(d); |
b9e5b4e6 BH |
754 | } |
755 | ||
835c0553 | 756 | static void mpic_end_ht_irq(struct irq_data *d) |
14cf11af | 757 | { |
835c0553 | 758 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 759 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 760 | |
1beb6a7d | 761 | #ifdef DEBUG_IRQ |
835c0553 | 762 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
1beb6a7d | 763 | #endif |
14cf11af PM |
764 | /* We always EOI on end_irq() even for edge interrupts since that |
765 | * should only lower the priority, the MPIC should have properly | |
766 | * latched another edge interrupt coming in anyway | |
767 | */ | |
768 | ||
24a3f2e8 | 769 | if (irqd_is_level_type(d)) |
b9e5b4e6 | 770 | mpic_ht_end_irq(mpic, src); |
14cf11af PM |
771 | mpic_eoi(mpic); |
772 | } | |
6cfef5b2 | 773 | #endif /* !CONFIG_MPIC_U3_HT_IRQS */ |
b9e5b4e6 | 774 | |
14cf11af PM |
775 | #ifdef CONFIG_SMP |
776 | ||
835c0553 | 777 | static void mpic_unmask_ipi(struct irq_data *d) |
14cf11af | 778 | { |
835c0553 | 779 | struct mpic *mpic = mpic_from_ipi(d); |
476eb491 | 780 | unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0]; |
14cf11af | 781 | |
835c0553 | 782 | DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); |
14cf11af PM |
783 | mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); |
784 | } | |
785 | ||
835c0553 | 786 | static void mpic_mask_ipi(struct irq_data *d) |
14cf11af PM |
787 | { |
788 | /* NEVER disable an IPI... that's just plain wrong! */ | |
789 | } | |
790 | ||
835c0553 | 791 | static void mpic_end_ipi(struct irq_data *d) |
14cf11af | 792 | { |
835c0553 | 793 | struct mpic *mpic = mpic_from_ipi(d); |
14cf11af PM |
794 | |
795 | /* | |
796 | * IPIs are marked IRQ_PER_CPU. This has the side effect of | |
797 | * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from | |
798 | * applying to them. We EOI them late to avoid re-entering. | |
14cf11af PM |
799 | */ |
800 | mpic_eoi(mpic); | |
801 | } | |
802 | ||
803 | #endif /* CONFIG_SMP */ | |
804 | ||
ea94187f SW |
805 | static void mpic_unmask_tm(struct irq_data *d) |
806 | { | |
807 | struct mpic *mpic = mpic_from_irq_data(d); | |
808 | unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; | |
809 | ||
77ef4899 | 810 | DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src); |
ea94187f SW |
811 | mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK); |
812 | mpic_tm_read(src); | |
813 | } | |
814 | ||
815 | static void mpic_mask_tm(struct irq_data *d) | |
816 | { | |
817 | struct mpic *mpic = mpic_from_irq_data(d); | |
818 | unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; | |
819 | ||
820 | mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK); | |
821 | mpic_tm_read(src); | |
822 | } | |
823 | ||
835c0553 LB |
824 | int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
825 | bool force) | |
14cf11af | 826 | { |
835c0553 | 827 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 828 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 829 | |
3c10c9c4 | 830 | if (mpic->flags & MPIC_SINGLE_DEST_CPU) { |
38e1313f | 831 | int cpuid = irq_choose_cpu(cpumask); |
14cf11af | 832 | |
3c10c9c4 KG |
833 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); |
834 | } else { | |
2a116f3d | 835 | u32 mask = cpumask_bits(cpumask)[0]; |
14cf11af | 836 | |
2a116f3d | 837 | mask &= cpumask_bits(cpu_online_mask)[0]; |
3c10c9c4 KG |
838 | |
839 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), | |
2a116f3d | 840 | mpic_physmask(mask)); |
3c10c9c4 | 841 | } |
d5dedd45 | 842 | |
dcb615ae | 843 | return IRQ_SET_MASK_OK; |
14cf11af PM |
844 | } |
845 | ||
7233593b | 846 | static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) |
0ebfff14 | 847 | { |
0ebfff14 | 848 | /* Now convert sense value */ |
6e99e458 | 849 | switch(type & IRQ_TYPE_SENSE_MASK) { |
0ebfff14 | 850 | case IRQ_TYPE_EDGE_RISING: |
7233593b ZR |
851 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
852 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 | 853 | case IRQ_TYPE_EDGE_FALLING: |
6e99e458 | 854 | case IRQ_TYPE_EDGE_BOTH: |
7233593b ZR |
855 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
856 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 857 | case IRQ_TYPE_LEVEL_HIGH: |
7233593b ZR |
858 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
859 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 BH |
860 | case IRQ_TYPE_LEVEL_LOW: |
861 | default: | |
7233593b ZR |
862 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
863 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 864 | } |
6e99e458 BH |
865 | } |
866 | ||
835c0553 | 867 | int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
6e99e458 | 868 | { |
835c0553 | 869 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 870 | unsigned int src = irqd_to_hwirq(d); |
6e99e458 BH |
871 | unsigned int vecpri, vold, vnew; |
872 | ||
06fe98e6 | 873 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", |
835c0553 | 874 | mpic, d->irq, src, flow_type); |
6e99e458 | 875 | |
5019609f | 876 | if (src >= mpic->num_sources) |
6e99e458 BH |
877 | return -EINVAL; |
878 | ||
446f6d06 BH |
879 | vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
880 | ||
881 | /* We don't support "none" type */ | |
6e99e458 | 882 | if (flow_type == IRQ_TYPE_NONE) |
446f6d06 BH |
883 | flow_type = IRQ_TYPE_DEFAULT; |
884 | ||
885 | /* Default: read HW settings */ | |
886 | if (flow_type == IRQ_TYPE_DEFAULT) { | |
0215b4aa PG |
887 | int vold_ps; |
888 | ||
889 | vold_ps = vold & (MPIC_INFO(VECPRI_POLARITY_MASK) | | |
890 | MPIC_INFO(VECPRI_SENSE_MASK)); | |
891 | ||
892 | if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) | | |
893 | MPIC_INFO(VECPRI_POLARITY_POSITIVE))) | |
894 | flow_type = IRQ_TYPE_EDGE_RISING; | |
895 | else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) | | |
896 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE))) | |
897 | flow_type = IRQ_TYPE_EDGE_FALLING; | |
898 | else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) | | |
899 | MPIC_INFO(VECPRI_POLARITY_POSITIVE))) | |
900 | flow_type = IRQ_TYPE_LEVEL_HIGH; | |
901 | else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) | | |
902 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE))) | |
903 | flow_type = IRQ_TYPE_LEVEL_LOW; | |
904 | else | |
905 | WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold); | |
446f6d06 | 906 | } |
6e99e458 | 907 | |
446f6d06 | 908 | /* Apply to irq desc */ |
24a3f2e8 | 909 | irqd_set_trigger_type(d, flow_type); |
6e99e458 | 910 | |
446f6d06 | 911 | /* Apply to HW */ |
6e99e458 BH |
912 | if (mpic_is_ht_interrupt(mpic, src)) |
913 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | | |
914 | MPIC_VECPRI_SENSE_EDGE; | |
915 | else | |
7233593b | 916 | vecpri = mpic_type_to_vecpri(mpic, flow_type); |
6e99e458 | 917 | |
7233593b ZR |
918 | vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | |
919 | MPIC_INFO(VECPRI_SENSE_MASK)); | |
6e99e458 BH |
920 | vnew |= vecpri; |
921 | if (vold != vnew) | |
7233593b | 922 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); |
6e99e458 | 923 | |
e075cd70 | 924 | return IRQ_SET_MASK_OK_NOCOPY; |
0ebfff14 BH |
925 | } |
926 | ||
38958dd9 OJ |
927 | void mpic_set_vector(unsigned int virq, unsigned int vector) |
928 | { | |
929 | struct mpic *mpic = mpic_from_irq(virq); | |
476eb491 | 930 | unsigned int src = virq_to_hw(virq); |
38958dd9 OJ |
931 | unsigned int vecpri; |
932 | ||
933 | DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", | |
934 | mpic, virq, src, vector); | |
935 | ||
5019609f | 936 | if (src >= mpic->num_sources) |
38958dd9 OJ |
937 | return; |
938 | ||
939 | vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); | |
940 | vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); | |
941 | vecpri |= vector; | |
942 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); | |
943 | } | |
944 | ||
e51df2c1 | 945 | static void mpic_set_destination(unsigned int virq, unsigned int cpuid) |
dfec2202 MI |
946 | { |
947 | struct mpic *mpic = mpic_from_irq(virq); | |
476eb491 | 948 | unsigned int src = virq_to_hw(virq); |
dfec2202 MI |
949 | |
950 | DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", | |
951 | mpic, virq, src, cpuid); | |
952 | ||
5019609f | 953 | if (src >= mpic->num_sources) |
dfec2202 MI |
954 | return; |
955 | ||
956 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); | |
957 | } | |
958 | ||
b9e5b4e6 | 959 | static struct irq_chip mpic_irq_chip = { |
835c0553 LB |
960 | .irq_mask = mpic_mask_irq, |
961 | .irq_unmask = mpic_unmask_irq, | |
962 | .irq_eoi = mpic_end_irq, | |
963 | .irq_set_type = mpic_set_irq_type, | |
b9e5b4e6 BH |
964 | }; |
965 | ||
966 | #ifdef CONFIG_SMP | |
967 | static struct irq_chip mpic_ipi_chip = { | |
835c0553 LB |
968 | .irq_mask = mpic_mask_ipi, |
969 | .irq_unmask = mpic_unmask_ipi, | |
970 | .irq_eoi = mpic_end_ipi, | |
b9e5b4e6 BH |
971 | }; |
972 | #endif /* CONFIG_SMP */ | |
973 | ||
ea94187f SW |
974 | static struct irq_chip mpic_tm_chip = { |
975 | .irq_mask = mpic_mask_tm, | |
976 | .irq_unmask = mpic_unmask_tm, | |
977 | .irq_eoi = mpic_end_irq, | |
978 | }; | |
979 | ||
6cfef5b2 | 980 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 981 | static struct irq_chip mpic_irq_ht_chip = { |
835c0553 LB |
982 | .irq_startup = mpic_startup_ht_irq, |
983 | .irq_shutdown = mpic_shutdown_ht_irq, | |
984 | .irq_mask = mpic_mask_irq, | |
985 | .irq_unmask = mpic_unmask_ht_irq, | |
986 | .irq_eoi = mpic_end_ht_irq, | |
987 | .irq_set_type = mpic_set_irq_type, | |
b9e5b4e6 | 988 | }; |
6cfef5b2 | 989 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
b9e5b4e6 | 990 | |
14cf11af | 991 | |
ad3aedfb MZ |
992 | static int mpic_host_match(struct irq_domain *h, struct device_node *node, |
993 | enum irq_domain_bus_token bus_token) | |
0ebfff14 | 994 | { |
0ebfff14 | 995 | /* Exact match, unless mpic node is NULL */ |
5d4c9bc7 MZ |
996 | struct device_node *of_node = irq_domain_get_of_node(h); |
997 | return of_node == NULL || of_node == node; | |
0ebfff14 BH |
998 | } |
999 | ||
bae1d8f1 | 1000 | static int mpic_host_map(struct irq_domain *h, unsigned int virq, |
6e99e458 | 1001 | irq_hw_number_t hw) |
0ebfff14 | 1002 | { |
0ebfff14 | 1003 | struct mpic *mpic = h->host_data; |
6e99e458 | 1004 | struct irq_chip *chip; |
0ebfff14 | 1005 | |
06fe98e6 | 1006 | DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); |
0ebfff14 | 1007 | |
7df2457d | 1008 | if (hw == mpic->spurious_vec) |
0ebfff14 | 1009 | return -EINVAL; |
5fe0c1f2 BH |
1010 | if (mpic->protected && test_bit(hw, mpic->protected)) { |
1011 | pr_warning("mpic: Mapping of source 0x%x failed, " | |
1012 | "source protected by firmware !\n",\ | |
1013 | (unsigned int)hw); | |
1014 | return -EPERM; | |
1015 | } | |
06fe98e6 | 1016 | |
0ebfff14 | 1017 | #ifdef CONFIG_SMP |
7df2457d | 1018 | else if (hw >= mpic->ipi_vecs[0]) { |
be8bec56 | 1019 | WARN_ON(mpic->flags & MPIC_SECONDARY); |
0ebfff14 | 1020 | |
06fe98e6 | 1021 | DBG("mpic: mapping as IPI\n"); |
ec775d0e TG |
1022 | irq_set_chip_data(virq, mpic); |
1023 | irq_set_chip_and_handler(virq, &mpic->hc_ipi, | |
0ebfff14 BH |
1024 | handle_percpu_irq); |
1025 | return 0; | |
1026 | } | |
1027 | #endif /* CONFIG_SMP */ | |
1028 | ||
ea94187f | 1029 | if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) { |
be8bec56 | 1030 | WARN_ON(mpic->flags & MPIC_SECONDARY); |
ea94187f SW |
1031 | |
1032 | DBG("mpic: mapping as timer\n"); | |
1033 | irq_set_chip_data(virq, mpic); | |
1034 | irq_set_chip_and_handler(virq, &mpic->hc_tm, | |
1035 | handle_fasteoi_irq); | |
1036 | return 0; | |
1037 | } | |
1038 | ||
0a408164 VS |
1039 | if (mpic_map_error_int(mpic, virq, hw)) |
1040 | return 0; | |
1041 | ||
5fe0c1f2 BH |
1042 | if (hw >= mpic->num_sources) { |
1043 | pr_warning("mpic: Mapping of source 0x%x failed, " | |
1044 | "source out of range !\n",\ | |
1045 | (unsigned int)hw); | |
0ebfff14 | 1046 | return -EINVAL; |
5fe0c1f2 | 1047 | } |
0ebfff14 | 1048 | |
a7de7c74 ME |
1049 | mpic_msi_reserve_hwirq(mpic, hw); |
1050 | ||
6e99e458 | 1051 | /* Default chip */ |
0ebfff14 BH |
1052 | chip = &mpic->hc_irq; |
1053 | ||
6cfef5b2 | 1054 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
0ebfff14 | 1055 | /* Check for HT interrupts, override vecpri */ |
6e99e458 | 1056 | if (mpic_is_ht_interrupt(mpic, hw)) |
0ebfff14 | 1057 | chip = &mpic->hc_ht_irq; |
6cfef5b2 | 1058 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
0ebfff14 | 1059 | |
06fe98e6 | 1060 | DBG("mpic: mapping to irq chip @%p\n", chip); |
0ebfff14 | 1061 | |
ec775d0e TG |
1062 | irq_set_chip_data(virq, mpic); |
1063 | irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); | |
6e99e458 BH |
1064 | |
1065 | /* Set default irq type */ | |
446f6d06 | 1066 | irq_set_irq_type(virq, IRQ_TYPE_DEFAULT); |
6e99e458 | 1067 | |
dfec2202 MI |
1068 | /* If the MPIC was reset, then all vectors have already been |
1069 | * initialized. Otherwise, a per source lazy initialization | |
1070 | * is done here. | |
1071 | */ | |
1072 | if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { | |
32dda05f SW |
1073 | int cpu; |
1074 | ||
1075 | preempt_disable(); | |
1076 | cpu = mpic_processor_id(mpic); | |
1077 | preempt_enable(); | |
1078 | ||
dfec2202 | 1079 | mpic_set_vector(virq, hw); |
32dda05f | 1080 | mpic_set_destination(virq, cpu); |
dfec2202 MI |
1081 | mpic_irq_set_priority(virq, 8); |
1082 | } | |
1083 | ||
0ebfff14 BH |
1084 | return 0; |
1085 | } | |
1086 | ||
bae1d8f1 | 1087 | static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct, |
40d50cf7 | 1088 | const u32 *intspec, unsigned int intsize, |
0ebfff14 BH |
1089 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
1090 | ||
1091 | { | |
22d168ce | 1092 | struct mpic *mpic = h->host_data; |
0ebfff14 BH |
1093 | static unsigned char map_mpic_senses[4] = { |
1094 | IRQ_TYPE_EDGE_RISING, | |
1095 | IRQ_TYPE_LEVEL_LOW, | |
1096 | IRQ_TYPE_LEVEL_HIGH, | |
1097 | IRQ_TYPE_EDGE_FALLING, | |
1098 | }; | |
1099 | ||
1100 | *out_hwirq = intspec[0]; | |
22d168ce SW |
1101 | if (intsize >= 4 && (mpic->flags & MPIC_FSL)) { |
1102 | /* | |
1103 | * Freescale MPIC with extended intspec: | |
1104 | * First two cells are as usual. Third specifies | |
1105 | * an "interrupt type". Fourth is type-specific data. | |
1106 | * | |
1107 | * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt | |
1108 | */ | |
1109 | switch (intspec[2]) { | |
1110 | case 0: | |
0a408164 VS |
1111 | break; |
1112 | case 1: | |
1113 | if (!(mpic->flags & MPIC_FSL_HAS_EIMR)) | |
1114 | break; | |
1115 | ||
1116 | if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs)) | |
1117 | return -EINVAL; | |
1118 | ||
1119 | *out_hwirq = mpic->err_int_vecs[intspec[3]]; | |
1120 | ||
22d168ce SW |
1121 | break; |
1122 | case 2: | |
1123 | if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs)) | |
1124 | return -EINVAL; | |
1125 | ||
1126 | *out_hwirq = mpic->ipi_vecs[intspec[0]]; | |
1127 | break; | |
1128 | case 3: | |
1129 | if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs)) | |
1130 | return -EINVAL; | |
1131 | ||
1132 | *out_hwirq = mpic->timer_vecs[intspec[0]]; | |
1133 | break; | |
1134 | default: | |
1135 | pr_debug("%s: unknown irq type %u\n", | |
1136 | __func__, intspec[2]); | |
1137 | return -EINVAL; | |
1138 | } | |
1139 | ||
1140 | *out_flags = map_mpic_senses[intspec[1] & 3]; | |
1141 | } else if (intsize > 1) { | |
06fe98e6 BH |
1142 | u32 mask = 0x3; |
1143 | ||
1144 | /* Apple invented a new race of encoding on machines with | |
1145 | * an HT APIC. They encode, among others, the index within | |
1146 | * the HT APIC. We don't care about it here since thankfully, | |
1147 | * it appears that they have the APIC already properly | |
1148 | * configured, and thus our current fixup code that reads the | |
1149 | * APIC config works fine. However, we still need to mask out | |
1150 | * bits in the specifier to make sure we only get bit 0 which | |
1151 | * is the level/edge bit (the only sense bit exposed by Apple), | |
1152 | * as their bit 1 means something else. | |
1153 | */ | |
1154 | if (machine_is(powermac)) | |
1155 | mask = 0x1; | |
1156 | *out_flags = map_mpic_senses[intspec[1] & mask]; | |
1157 | } else | |
0ebfff14 BH |
1158 | *out_flags = IRQ_TYPE_NONE; |
1159 | ||
06fe98e6 BH |
1160 | DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", |
1161 | intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); | |
1162 | ||
0ebfff14 BH |
1163 | return 0; |
1164 | } | |
1165 | ||
09dc34a9 | 1166 | /* IRQ handler for a secondary MPIC cascaded from another IRQ controller */ |
bd0b9ac4 | 1167 | static void mpic_cascade(struct irq_desc *desc) |
09dc34a9 KM |
1168 | { |
1169 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
1170 | struct mpic *mpic = irq_desc_get_handler_data(desc); | |
1171 | unsigned int virq; | |
1172 | ||
1173 | BUG_ON(!(mpic->flags & MPIC_SECONDARY)); | |
1174 | ||
1175 | virq = mpic_get_one_irq(mpic); | |
bae1d8f1 | 1176 | if (virq) |
09dc34a9 KM |
1177 | generic_handle_irq(virq); |
1178 | ||
1179 | chip->irq_eoi(&desc->irq_data); | |
1180 | } | |
1181 | ||
202648a6 | 1182 | static const struct irq_domain_ops mpic_host_ops = { |
0ebfff14 BH |
1183 | .match = mpic_host_match, |
1184 | .map = mpic_host_map, | |
1185 | .xlate = mpic_host_xlate, | |
1186 | }; | |
1187 | ||
86d37969 HJ |
1188 | static u32 fsl_mpic_get_version(struct mpic *mpic) |
1189 | { | |
1190 | u32 brr1; | |
1191 | ||
1192 | if (!(mpic->flags & MPIC_FSL)) | |
1193 | return 0; | |
1194 | ||
1195 | brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs, | |
1196 | MPIC_FSL_BRR1); | |
1197 | ||
1198 | return brr1 & MPIC_FSL_BRR1_VER; | |
1199 | } | |
1200 | ||
14cf11af PM |
1201 | /* |
1202 | * Exported functions | |
1203 | */ | |
1204 | ||
807d38b7 HJ |
1205 | u32 fsl_mpic_primary_get_version(void) |
1206 | { | |
1207 | struct mpic *mpic = mpic_primary; | |
1208 | ||
1209 | if (mpic) | |
1210 | return fsl_mpic_get_version(mpic); | |
1211 | ||
1212 | return 0; | |
1213 | } | |
1214 | ||
0ebfff14 | 1215 | struct mpic * __init mpic_alloc(struct device_node *node, |
a959ff56 | 1216 | phys_addr_t phys_addr, |
14cf11af PM |
1217 | unsigned int flags, |
1218 | unsigned int isu_size, | |
14cf11af | 1219 | unsigned int irq_count, |
14cf11af PM |
1220 | const char *name) |
1221 | { | |
5bdb6f2e KM |
1222 | int i, psize, intvec_top; |
1223 | struct mpic *mpic; | |
1224 | u32 greg_feature; | |
1225 | const char *vers; | |
1226 | const u32 *psrc; | |
c1b8d45d | 1227 | u32 last_irq; |
7c509ee0 | 1228 | u32 fsl_version = 0; |
8bf41568 | 1229 | |
996983b7 KM |
1230 | /* Default MPIC search parameters */ |
1231 | static const struct of_device_id __initconst mpic_device_id[] = { | |
1232 | { .type = "open-pic", }, | |
1233 | { .compatible = "open-pic", }, | |
1234 | {}, | |
1235 | }; | |
1236 | ||
1237 | /* | |
1238 | * If we were not passed a device-tree node, then perform the default | |
1239 | * search for standardized a standardized OpenPIC. | |
1240 | */ | |
1241 | if (node) { | |
1242 | node = of_node_get(node); | |
1243 | } else { | |
1244 | node = of_find_matching_node(NULL, mpic_device_id); | |
1245 | if (!node) | |
1246 | return NULL; | |
1247 | } | |
8bf41568 | 1248 | |
5bdb6f2e KM |
1249 | /* Pick the physical address from the device tree if unspecified */ |
1250 | if (!phys_addr) { | |
8bf41568 KM |
1251 | /* Check if it is DCR-based */ |
1252 | if (of_get_property(node, "dcr-reg", NULL)) { | |
1253 | flags |= MPIC_USES_DCR; | |
1254 | } else { | |
1255 | struct resource r; | |
1256 | if (of_address_to_resource(node, 0, &r)) | |
996983b7 | 1257 | goto err_of_node_put; |
8bf41568 KM |
1258 | phys_addr = r.start; |
1259 | } | |
1260 | } | |
14cf11af | 1261 | |
3a7a7176 KM |
1262 | /* Read extra device-tree properties into the flags variable */ |
1263 | if (of_get_property(node, "big-endian", NULL)) | |
1264 | flags |= MPIC_BIG_ENDIAN; | |
1265 | if (of_get_property(node, "pic-no-reset", NULL)) | |
1266 | flags |= MPIC_NO_RESET; | |
9ca163c8 KM |
1267 | if (of_get_property(node, "single-cpu-affinity", NULL)) |
1268 | flags |= MPIC_SINGLE_DEST_CPU; | |
9100d20c | 1269 | if (of_device_is_compatible(node, "fsl,mpic")) { |
5a271fe7 | 1270 | flags |= MPIC_FSL | MPIC_LARGE_VECTORS; |
9100d20c SH |
1271 | mpic_irq_chip.flags |= IRQCHIP_SKIP_SET_WAKE; |
1272 | mpic_tm_chip.flags |= IRQCHIP_SKIP_SET_WAKE; | |
1273 | } | |
3a7a7176 | 1274 | |
85355bb2 | 1275 | mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); |
14cf11af | 1276 | if (mpic == NULL) |
996983b7 | 1277 | goto err_of_node_put; |
85355bb2 | 1278 | |
14cf11af | 1279 | mpic->name = name; |
c51242e7 | 1280 | mpic->node = node; |
e7a98675 | 1281 | mpic->paddr = phys_addr; |
3a7a7176 | 1282 | mpic->flags = flags; |
14cf11af | 1283 | |
b9e5b4e6 | 1284 | mpic->hc_irq = mpic_irq_chip; |
b27df672 | 1285 | mpic->hc_irq.name = name; |
3a7a7176 | 1286 | if (!(mpic->flags & MPIC_SECONDARY)) |
835c0553 | 1287 | mpic->hc_irq.irq_set_affinity = mpic_set_affinity; |
6cfef5b2 | 1288 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 1289 | mpic->hc_ht_irq = mpic_irq_ht_chip; |
b27df672 | 1290 | mpic->hc_ht_irq.name = name; |
3a7a7176 | 1291 | if (!(mpic->flags & MPIC_SECONDARY)) |
835c0553 | 1292 | mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; |
6cfef5b2 | 1293 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
fbf0274e | 1294 | |
14cf11af | 1295 | #ifdef CONFIG_SMP |
b9e5b4e6 | 1296 | mpic->hc_ipi = mpic_ipi_chip; |
b27df672 | 1297 | mpic->hc_ipi.name = name; |
14cf11af PM |
1298 | #endif /* CONFIG_SMP */ |
1299 | ||
ea94187f SW |
1300 | mpic->hc_tm = mpic_tm_chip; |
1301 | mpic->hc_tm.name = name; | |
1302 | ||
14cf11af | 1303 | mpic->num_sources = 0; /* so far */ |
14cf11af | 1304 | |
3a7a7176 | 1305 | if (mpic->flags & MPIC_LARGE_VECTORS) |
7df2457d OJ |
1306 | intvec_top = 2047; |
1307 | else | |
1308 | intvec_top = 255; | |
1309 | ||
ea94187f SW |
1310 | mpic->timer_vecs[0] = intvec_top - 12; |
1311 | mpic->timer_vecs[1] = intvec_top - 11; | |
1312 | mpic->timer_vecs[2] = intvec_top - 10; | |
1313 | mpic->timer_vecs[3] = intvec_top - 9; | |
1314 | mpic->timer_vecs[4] = intvec_top - 8; | |
1315 | mpic->timer_vecs[5] = intvec_top - 7; | |
1316 | mpic->timer_vecs[6] = intvec_top - 6; | |
1317 | mpic->timer_vecs[7] = intvec_top - 5; | |
7df2457d OJ |
1318 | mpic->ipi_vecs[0] = intvec_top - 4; |
1319 | mpic->ipi_vecs[1] = intvec_top - 3; | |
1320 | mpic->ipi_vecs[2] = intvec_top - 2; | |
1321 | mpic->ipi_vecs[3] = intvec_top - 1; | |
1322 | mpic->spurious_vec = intvec_top; | |
1323 | ||
7fd72186 | 1324 | /* Look for protected sources */ |
c51242e7 | 1325 | psrc = of_get_property(mpic->node, "protected-sources", &psize); |
5bdb6f2e KM |
1326 | if (psrc) { |
1327 | /* Allocate a bitmap with one bit per interrupt */ | |
1328 | unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1); | |
1329 | mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL); | |
1330 | BUG_ON(mpic->protected == NULL); | |
1331 | for (i = 0; i < psize/sizeof(u32); i++) { | |
1332 | if (psrc[i] > intvec_top) | |
1333 | continue; | |
1334 | __set_bit(psrc[i], mpic->protected); | |
7fd72186 BH |
1335 | } |
1336 | } | |
a959ff56 | 1337 | |
7233593b | 1338 | #ifdef CONFIG_MPIC_WEIRD |
3a7a7176 | 1339 | mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)]; |
7233593b ZR |
1340 | #endif |
1341 | ||
fbf0274e | 1342 | /* default register type */ |
3a7a7176 | 1343 | if (mpic->flags & MPIC_BIG_ENDIAN) |
8bf41568 KM |
1344 | mpic->reg_type = mpic_access_mmio_be; |
1345 | else | |
1346 | mpic->reg_type = mpic_access_mmio_le; | |
a959ff56 | 1347 | |
8bf41568 KM |
1348 | /* |
1349 | * An MPIC with a "dcr-reg" property must be accessed that way, but | |
1350 | * only if the kernel includes DCR support. | |
1351 | */ | |
fbf0274e | 1352 | #ifdef CONFIG_PPC_DCR |
3a7a7176 | 1353 | if (mpic->flags & MPIC_USES_DCR) |
fbf0274e | 1354 | mpic->reg_type = mpic_access_dcr; |
fbf0274e | 1355 | #else |
3a7a7176 | 1356 | BUG_ON(mpic->flags & MPIC_USES_DCR); |
8bf41568 | 1357 | #endif |
a959ff56 | 1358 | |
14cf11af | 1359 | /* Map the global registers */ |
c51242e7 KM |
1360 | mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); |
1361 | mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); | |
14cf11af | 1362 | |
03bcb7e3 | 1363 | if (mpic->flags & MPIC_FSL) { |
0a408164 VS |
1364 | int ret; |
1365 | ||
03bcb7e3 VS |
1366 | /* |
1367 | * Yes, Freescale really did put global registers in the | |
1368 | * magic per-cpu area -- and they don't even show up in the | |
1369 | * non-magic per-cpu copies that this driver normally uses. | |
1370 | */ | |
1371 | mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs, | |
1372 | MPIC_CPU_THISBASE, 0x1000); | |
0a408164 | 1373 | |
86d37969 | 1374 | fsl_version = fsl_mpic_get_version(mpic); |
0a408164 VS |
1375 | |
1376 | /* Error interrupt mask register (EIMR) is required for | |
1377 | * handling individual device error interrupts. EIMR | |
1378 | * was added in MPIC version 4.1. | |
1379 | * | |
1380 | * Over here we reserve vector number space for error | |
1381 | * interrupt vectors. This space is stolen from the | |
1382 | * global vector number space, as in case of ipis | |
1383 | * and timer interrupts. | |
1384 | * | |
1385 | * Available vector space = intvec_top - 12, where 12 | |
1386 | * is the number of vectors which have been consumed by | |
1387 | * ipis and timer interrupts. | |
1388 | */ | |
7c509ee0 | 1389 | if (fsl_version >= 0x401) { |
0a408164 VS |
1390 | ret = mpic_setup_error_int(mpic, intvec_top - 12); |
1391 | if (ret) | |
1392 | return NULL; | |
1393 | } | |
7c509ee0 SW |
1394 | |
1395 | } | |
1396 | ||
1397 | /* | |
1398 | * EPR is only available starting with v4.0. To support | |
1399 | * platforms that don't know the MPIC version at compile-time, | |
1400 | * such as qemu-e500, turn off coreint if this MPIC doesn't | |
1401 | * support it. Note that we never enable it if it wasn't | |
1402 | * requested in the first place. | |
1403 | * | |
1404 | * This is done outside the MPIC_FSL check, so that we | |
1405 | * also disable coreint if the MPIC node doesn't have | |
1406 | * an "fsl,mpic" compatible at all. This will be the case | |
1407 | * with device trees generated by older versions of QEMU. | |
1408 | * fsl_version will be zero if MPIC_FSL is not set. | |
1409 | */ | |
1410 | if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT)) { | |
1411 | WARN_ON(ppc_md.get_irq != mpic_get_coreint_irq); | |
1412 | ppc_md.get_irq = mpic_get_irq; | |
03bcb7e3 VS |
1413 | } |
1414 | ||
14cf11af | 1415 | /* Reset */ |
dfec2202 MI |
1416 | |
1417 | /* When using a device-node, reset requests are only honored if the MPIC | |
1418 | * is allowed to reset. | |
1419 | */ | |
e55d7f73 | 1420 | if (!(mpic->flags & MPIC_NO_RESET)) { |
dfec2202 | 1421 | printk(KERN_DEBUG "mpic: Resetting\n"); |
7233593b ZR |
1422 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
1423 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
14cf11af | 1424 | | MPIC_GREG_GCONF_RESET); |
7233593b | 1425 | while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
14cf11af PM |
1426 | & MPIC_GREG_GCONF_RESET) |
1427 | mb(); | |
1428 | } | |
1429 | ||
d91e4ea7 | 1430 | /* CoreInt */ |
3a7a7176 | 1431 | if (mpic->flags & MPIC_ENABLE_COREINT) |
d91e4ea7 KG |
1432 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
1433 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1434 | | MPIC_GREG_GCONF_COREINT); | |
1435 | ||
3a7a7176 | 1436 | if (mpic->flags & MPIC_ENABLE_MCK) |
f365355e OJ |
1437 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
1438 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1439 | | MPIC_GREG_GCONF_MCK); | |
1440 | ||
14b92470 TT |
1441 | /* |
1442 | * The MPIC driver will crash if there are more cores than we | |
1443 | * can initialize, so we may as well catch that problem here. | |
1444 | */ | |
1445 | BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS); | |
1446 | ||
14cf11af | 1447 | /* Map the per-CPU registers */ |
14b92470 TT |
1448 | for_each_possible_cpu(i) { |
1449 | unsigned int cpu = get_hard_smp_processor_id(i); | |
1450 | ||
c51242e7 | 1451 | mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu], |
14b92470 | 1452 | MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE), |
fbf0274e | 1453 | 0x1000); |
14cf11af PM |
1454 | } |
1455 | ||
c1b8d45d KM |
1456 | /* |
1457 | * Read feature register. For non-ISU MPICs, num sources as well. On | |
1458 | * ISU MPICs, sources are counted as ISUs are added | |
1459 | */ | |
1460 | greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); | |
1461 | ||
1462 | /* | |
1463 | * By default, the last source number comes from the MPIC, but the | |
1464 | * device-tree and board support code can override it on buggy hw. | |
fe83364f BH |
1465 | * If we get passed an isu_size (multi-isu MPIC) then we use that |
1466 | * as a default instead of the value read from the HW. | |
c1b8d45d KM |
1467 | */ |
1468 | last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) | |
26a2056e | 1469 | >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT; |
fe83364f BH |
1470 | if (isu_size) |
1471 | last_irq = isu_size * MPIC_MAX_ISU - 1; | |
c1b8d45d KM |
1472 | of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq); |
1473 | if (irq_count) | |
1474 | last_irq = irq_count - 1; | |
1475 | ||
14cf11af | 1476 | /* Initialize main ISU if none provided */ |
c1b8d45d KM |
1477 | if (!isu_size) { |
1478 | isu_size = last_irq + 1; | |
1479 | mpic->num_sources = isu_size; | |
c51242e7 | 1480 | mpic_map(mpic, mpic->paddr, &mpic->isus[0], |
c1b8d45d KM |
1481 | MPIC_INFO(IRQ_BASE), |
1482 | MPIC_INFO(IRQ_STRIDE) * isu_size); | |
14cf11af | 1483 | } |
c1b8d45d KM |
1484 | |
1485 | mpic->isu_size = isu_size; | |
14cf11af PM |
1486 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); |
1487 | mpic->isu_mask = (1 << mpic->isu_shift) - 1; | |
1488 | ||
a8db8cf0 | 1489 | mpic->irqhost = irq_domain_add_linear(mpic->node, |
574ce79c | 1490 | intvec_top, |
a8db8cf0 | 1491 | &mpic_host_ops, mpic); |
996983b7 KM |
1492 | |
1493 | /* | |
1494 | * FIXME: The code leaks the MPIC object and mappings here; this | |
1495 | * is very unlikely to fail but it ought to be fixed anyways. | |
1496 | */ | |
31207dab KG |
1497 | if (mpic->irqhost == NULL) |
1498 | return NULL; | |
1499 | ||
14cf11af | 1500 | /* Display version */ |
d9d1063d | 1501 | switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { |
14cf11af PM |
1502 | case 1: |
1503 | vers = "1.0"; | |
1504 | break; | |
1505 | case 2: | |
1506 | vers = "1.2"; | |
1507 | break; | |
1508 | case 3: | |
1509 | vers = "1.3"; | |
1510 | break; | |
1511 | default: | |
1512 | vers = "<unknown>"; | |
1513 | break; | |
1514 | } | |
a959ff56 BH |
1515 | printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," |
1516 | " max %d CPUs\n", | |
e7a98675 | 1517 | name, vers, (unsigned long long)mpic->paddr, num_possible_cpus()); |
a959ff56 BH |
1518 | printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", |
1519 | mpic->isu_size, mpic->isu_shift, mpic->isu_mask); | |
14cf11af PM |
1520 | |
1521 | mpic->next = mpics; | |
1522 | mpics = mpic; | |
1523 | ||
3a7a7176 | 1524 | if (!(mpic->flags & MPIC_SECONDARY)) { |
14cf11af | 1525 | mpic_primary = mpic; |
0ebfff14 BH |
1526 | irq_set_default_host(mpic->irqhost); |
1527 | } | |
14cf11af PM |
1528 | |
1529 | return mpic; | |
996983b7 KM |
1530 | |
1531 | err_of_node_put: | |
1532 | of_node_put(node); | |
1533 | return NULL; | |
14cf11af PM |
1534 | } |
1535 | ||
1536 | void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, | |
a959ff56 | 1537 | phys_addr_t paddr) |
14cf11af PM |
1538 | { |
1539 | unsigned int isu_first = isu_num * mpic->isu_size; | |
1540 | ||
1541 | BUG_ON(isu_num >= MPIC_MAX_ISU); | |
1542 | ||
c51242e7 | 1543 | mpic_map(mpic, |
5a2642f6 | 1544 | paddr, &mpic->isus[isu_num], 0, |
fbf0274e | 1545 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
5a2642f6 | 1546 | |
14cf11af PM |
1547 | if ((isu_first + mpic->isu_size) > mpic->num_sources) |
1548 | mpic->num_sources = isu_first + mpic->isu_size; | |
1549 | } | |
1550 | ||
14cf11af PM |
1551 | void __init mpic_init(struct mpic *mpic) |
1552 | { | |
09dc34a9 | 1553 | int i, cpu; |
03bcb7e3 | 1554 | int num_timers = 4; |
14cf11af PM |
1555 | |
1556 | BUG_ON(mpic->num_sources == 0); | |
1557 | ||
1558 | printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); | |
1559 | ||
1560 | /* Set current processor priority to max */ | |
7233593b | 1561 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
14cf11af | 1562 | |
03bcb7e3 | 1563 | if (mpic->flags & MPIC_FSL) { |
86d37969 | 1564 | u32 version = fsl_mpic_get_version(mpic); |
03bcb7e3 VS |
1565 | |
1566 | /* | |
1567 | * Timer group B is present at the latest in MPIC 3.1 (e.g. | |
1568 | * mpc8536). It is not present in MPIC 2.0 (e.g. mpc8544). | |
1569 | * I don't know about the status of intermediate versions (or | |
1570 | * whether they even exist). | |
1571 | */ | |
1572 | if (version >= 0x0301) | |
1573 | num_timers = 8; | |
1574 | } | |
1575 | ||
ea94187f | 1576 | /* Initialize timers to our reserved vectors and mask them for now */ |
03bcb7e3 VS |
1577 | for (i = 0; i < num_timers; i++) { |
1578 | unsigned int offset = mpic_tm_offset(mpic, i); | |
1579 | ||
14cf11af | 1580 | mpic_write(mpic->tmregs, |
03bcb7e3 | 1581 | offset + MPIC_INFO(TIMER_DESTINATION), |
ea94187f | 1582 | 1 << hard_smp_processor_id()); |
14cf11af | 1583 | mpic_write(mpic->tmregs, |
03bcb7e3 | 1584 | offset + MPIC_INFO(TIMER_VECTOR_PRI), |
14cf11af | 1585 | MPIC_VECPRI_MASK | |
ea94187f | 1586 | (9 << MPIC_VECPRI_PRIORITY_SHIFT) | |
7df2457d | 1587 | (mpic->timer_vecs[0] + i)); |
14cf11af PM |
1588 | } |
1589 | ||
1590 | /* Initialize IPIs to our reserved vectors and mark them disabled for now */ | |
1591 | mpic_test_broken_ipi(mpic); | |
1592 | for (i = 0; i < 4; i++) { | |
1593 | mpic_ipi_write(i, | |
1594 | MPIC_VECPRI_MASK | | |
1595 | (10 << MPIC_VECPRI_PRIORITY_SHIFT) | | |
7df2457d | 1596 | (mpic->ipi_vecs[0] + i)); |
14cf11af PM |
1597 | } |
1598 | ||
1beb6a7d | 1599 | /* Do the HT PIC fixups on U3 broken mpic */ |
14cf11af | 1600 | DBG("MPIC flags: %x\n", mpic->flags); |
be8bec56 | 1601 | if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) { |
3669e930 | 1602 | mpic_scan_ht_pics(mpic); |
05af7bd2 ME |
1603 | mpic_u3msi_init(mpic); |
1604 | } | |
14cf11af | 1605 | |
38958dd9 OJ |
1606 | mpic_pasemi_msi_init(mpic); |
1607 | ||
d6a2639b | 1608 | cpu = mpic_processor_id(mpic); |
cc353c30 | 1609 | |
dfec2202 MI |
1610 | if (!(mpic->flags & MPIC_NO_RESET)) { |
1611 | for (i = 0; i < mpic->num_sources; i++) { | |
1612 | /* start with vector = source number, and masked */ | |
1613 | u32 vecpri = MPIC_VECPRI_MASK | i | | |
1614 | (8 << MPIC_VECPRI_PRIORITY_SHIFT); | |
26a2056e | 1615 | |
dfec2202 MI |
1616 | /* check if protected */ |
1617 | if (mpic->protected && test_bit(i, mpic->protected)) | |
1618 | continue; | |
1619 | /* init hw */ | |
1620 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); | |
1621 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); | |
1622 | } | |
14cf11af | 1623 | } |
26a2056e | 1624 | |
7df2457d OJ |
1625 | /* Init spurious vector */ |
1626 | mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); | |
14cf11af | 1627 | |
7233593b ZR |
1628 | /* Disable 8259 passthrough, if supported */ |
1629 | if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) | |
1630 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1631 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1632 | | MPIC_GREG_GCONF_8259_PTHROU_DIS); | |
14cf11af | 1633 | |
d87bf3be OJ |
1634 | if (mpic->flags & MPIC_NO_BIAS) |
1635 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1636 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1637 | | MPIC_GREG_GCONF_NO_BIAS); | |
1638 | ||
14cf11af | 1639 | /* Set current processor priority to 0 */ |
7233593b | 1640 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
3669e930 JB |
1641 | |
1642 | #ifdef CONFIG_PM | |
1643 | /* allocate memory to save mpic state */ | |
ea96025a AV |
1644 | mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data), |
1645 | GFP_KERNEL); | |
3669e930 JB |
1646 | BUG_ON(mpic->save_data == NULL); |
1647 | #endif | |
09dc34a9 KM |
1648 | |
1649 | /* Check if this MPIC is chained from a parent interrupt controller */ | |
1650 | if (mpic->flags & MPIC_SECONDARY) { | |
1651 | int virq = irq_of_parse_and_map(mpic->node, 0); | |
1652 | if (virq != NO_IRQ) { | |
1653 | printk(KERN_INFO "%s: hooking up to IRQ %d\n", | |
1654 | mpic->node->full_name, virq); | |
1655 | irq_set_handler_data(virq, mpic); | |
1656 | irq_set_chained_handler(virq, &mpic_cascade); | |
1657 | } | |
1658 | } | |
aa80581d | 1659 | |
446957ba | 1660 | /* FSL mpic error interrupt initialization */ |
aa80581d SW |
1661 | if (mpic->flags & MPIC_FSL_HAS_EIMR) |
1662 | mpic_err_int_init(mpic, MPIC_FSL_ERR_INT); | |
14cf11af PM |
1663 | } |
1664 | ||
14cf11af PM |
1665 | void mpic_irq_set_priority(unsigned int irq, unsigned int pri) |
1666 | { | |
d69a78d7 | 1667 | struct mpic *mpic = mpic_find(irq); |
476eb491 | 1668 | unsigned int src = virq_to_hw(irq); |
14cf11af PM |
1669 | unsigned long flags; |
1670 | u32 reg; | |
1671 | ||
06a901c5 SR |
1672 | if (!mpic) |
1673 | return; | |
1674 | ||
203041ad | 1675 | raw_spin_lock_irqsave(&mpic_lock, flags); |
3a2b4f7c | 1676 | if (mpic_is_ipi(mpic, src)) { |
7df2457d | 1677 | reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & |
e5356640 | 1678 | ~MPIC_VECPRI_PRIORITY_MASK; |
7df2457d | 1679 | mpic_ipi_write(src - mpic->ipi_vecs[0], |
14cf11af | 1680 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
3a2b4f7c | 1681 | } else if (mpic_is_tm(mpic, src)) { |
ea94187f SW |
1682 | reg = mpic_tm_read(src - mpic->timer_vecs[0]) & |
1683 | ~MPIC_VECPRI_PRIORITY_MASK; | |
1684 | mpic_tm_write(src - mpic->timer_vecs[0], | |
1685 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); | |
14cf11af | 1686 | } else { |
7233593b | 1687 | reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
e5356640 | 1688 | & ~MPIC_VECPRI_PRIORITY_MASK; |
7233593b | 1689 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
14cf11af PM |
1690 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
1691 | } | |
203041ad | 1692 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1693 | } |
1694 | ||
14cf11af PM |
1695 | void mpic_setup_this_cpu(void) |
1696 | { | |
1697 | #ifdef CONFIG_SMP | |
1698 | struct mpic *mpic = mpic_primary; | |
1699 | unsigned long flags; | |
1700 | u32 msk = 1 << hard_smp_processor_id(); | |
1701 | unsigned int i; | |
1702 | ||
1703 | BUG_ON(mpic == NULL); | |
1704 | ||
1705 | DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
1706 | ||
203041ad | 1707 | raw_spin_lock_irqsave(&mpic_lock, flags); |
14cf11af PM |
1708 | |
1709 | /* let the mpic know we want intrs. default affinity is 0xffffffff | |
1710 | * until changed via /proc. That's how it's done on x86. If we want | |
1711 | * it differently, then we should make sure we also change the default | |
a53da52f | 1712 | * values of irq_desc[].affinity in irq.c. |
14cf11af | 1713 | */ |
e242114a | 1714 | if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) { |
14cf11af | 1715 | for (i = 0; i < mpic->num_sources ; i++) |
7233593b ZR |
1716 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1717 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); | |
14cf11af PM |
1718 | } |
1719 | ||
1720 | /* Set current processor priority to 0 */ | |
7233593b | 1721 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
14cf11af | 1722 | |
203041ad | 1723 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1724 | #endif /* CONFIG_SMP */ |
1725 | } | |
1726 | ||
1727 | int mpic_cpu_get_priority(void) | |
1728 | { | |
1729 | struct mpic *mpic = mpic_primary; | |
1730 | ||
7233593b | 1731 | return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); |
14cf11af PM |
1732 | } |
1733 | ||
1734 | void mpic_cpu_set_priority(int prio) | |
1735 | { | |
1736 | struct mpic *mpic = mpic_primary; | |
1737 | ||
1738 | prio &= MPIC_CPU_TASKPRI_MASK; | |
7233593b | 1739 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); |
14cf11af PM |
1740 | } |
1741 | ||
14cf11af PM |
1742 | void mpic_teardown_this_cpu(int secondary) |
1743 | { | |
1744 | struct mpic *mpic = mpic_primary; | |
1745 | unsigned long flags; | |
1746 | u32 msk = 1 << hard_smp_processor_id(); | |
1747 | unsigned int i; | |
1748 | ||
1749 | BUG_ON(mpic == NULL); | |
1750 | ||
1751 | DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
203041ad | 1752 | raw_spin_lock_irqsave(&mpic_lock, flags); |
14cf11af PM |
1753 | |
1754 | /* let the mpic know we don't want intrs. */ | |
1755 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1756 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1757 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); | |
14cf11af PM |
1758 | |
1759 | /* Set current processor priority to max */ | |
7233593b | 1760 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
7132799b VB |
1761 | /* We need to EOI the IPI since not all platforms reset the MPIC |
1762 | * on boot and new interrupts wouldn't get delivered otherwise. | |
1763 | */ | |
1764 | mpic_eoi(mpic); | |
14cf11af | 1765 | |
203041ad | 1766 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1767 | } |
1768 | ||
1769 | ||
f365355e | 1770 | static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) |
14cf11af | 1771 | { |
0ebfff14 | 1772 | u32 src; |
14cf11af | 1773 | |
f365355e | 1774 | src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); |
1beb6a7d | 1775 | #ifdef DEBUG_LOW |
f365355e | 1776 | DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); |
1beb6a7d | 1777 | #endif |
5cddd2e3 JB |
1778 | if (unlikely(src == mpic->spurious_vec)) { |
1779 | if (mpic->flags & MPIC_SPV_EOI) | |
1780 | mpic_eoi(mpic); | |
0ebfff14 | 1781 | return NO_IRQ; |
5cddd2e3 | 1782 | } |
7fd72186 | 1783 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { |
76462232 CD |
1784 | printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n", |
1785 | mpic->name, (int)src); | |
7fd72186 BH |
1786 | mpic_eoi(mpic); |
1787 | return NO_IRQ; | |
1788 | } | |
1789 | ||
0ebfff14 | 1790 | return irq_linear_revmap(mpic->irqhost, src); |
14cf11af PM |
1791 | } |
1792 | ||
f365355e OJ |
1793 | unsigned int mpic_get_one_irq(struct mpic *mpic) |
1794 | { | |
1795 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); | |
1796 | } | |
1797 | ||
35a84c2f | 1798 | unsigned int mpic_get_irq(void) |
14cf11af PM |
1799 | { |
1800 | struct mpic *mpic = mpic_primary; | |
1801 | ||
1802 | BUG_ON(mpic == NULL); | |
1803 | ||
35a84c2f | 1804 | return mpic_get_one_irq(mpic); |
14cf11af PM |
1805 | } |
1806 | ||
d91e4ea7 KG |
1807 | unsigned int mpic_get_coreint_irq(void) |
1808 | { | |
1809 | #ifdef CONFIG_BOOKE | |
1810 | struct mpic *mpic = mpic_primary; | |
1811 | u32 src; | |
1812 | ||
1813 | BUG_ON(mpic == NULL); | |
1814 | ||
1815 | src = mfspr(SPRN_EPR); | |
1816 | ||
1817 | if (unlikely(src == mpic->spurious_vec)) { | |
1818 | if (mpic->flags & MPIC_SPV_EOI) | |
1819 | mpic_eoi(mpic); | |
1820 | return NO_IRQ; | |
1821 | } | |
1822 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { | |
76462232 CD |
1823 | printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n", |
1824 | mpic->name, (int)src); | |
d91e4ea7 KG |
1825 | return NO_IRQ; |
1826 | } | |
1827 | ||
1828 | return irq_linear_revmap(mpic->irqhost, src); | |
1829 | #else | |
1830 | return NO_IRQ; | |
1831 | #endif | |
1832 | } | |
1833 | ||
f365355e OJ |
1834 | unsigned int mpic_get_mcirq(void) |
1835 | { | |
1836 | struct mpic *mpic = mpic_primary; | |
1837 | ||
1838 | BUG_ON(mpic == NULL); | |
1839 | ||
1840 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); | |
1841 | } | |
14cf11af PM |
1842 | |
1843 | #ifdef CONFIG_SMP | |
1844 | void mpic_request_ipis(void) | |
1845 | { | |
1846 | struct mpic *mpic = mpic_primary; | |
78608dd3 | 1847 | int i; |
14cf11af | 1848 | BUG_ON(mpic == NULL); |
14cf11af | 1849 | |
8354be9c | 1850 | printk(KERN_INFO "mpic: requesting IPIs...\n"); |
0ebfff14 BH |
1851 | |
1852 | for (i = 0; i < 4; i++) { | |
1853 | unsigned int vipi = irq_create_mapping(mpic->irqhost, | |
7df2457d | 1854 | mpic->ipi_vecs[0] + i); |
0ebfff14 | 1855 | if (vipi == NO_IRQ) { |
78608dd3 MM |
1856 | printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); |
1857 | continue; | |
d16f1b64 | 1858 | } |
78608dd3 | 1859 | smp_request_message_ipi(vipi, i); |
0ebfff14 | 1860 | } |
14cf11af | 1861 | } |
a9c59264 | 1862 | |
3caba98f | 1863 | void smp_mpic_message_pass(int cpu, int msg) |
2ef613cb BH |
1864 | { |
1865 | struct mpic *mpic = mpic_primary; | |
3caba98f | 1866 | u32 physmask; |
2ef613cb BH |
1867 | |
1868 | BUG_ON(mpic == NULL); | |
1869 | ||
a9c59264 PM |
1870 | /* make sure we're sending something that translates to an IPI */ |
1871 | if ((unsigned int)msg > 3) { | |
1872 | printk("SMP %d: smp_message_pass: unknown msg %d\n", | |
1873 | smp_processor_id(), msg); | |
1874 | return; | |
1875 | } | |
3caba98f MM |
1876 | |
1877 | #ifdef DEBUG_IPI | |
1878 | DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg); | |
1879 | #endif | |
1880 | ||
1881 | physmask = 1 << get_hard_smp_processor_id(cpu); | |
1882 | ||
1883 | mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + | |
1884 | msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask); | |
a9c59264 | 1885 | } |
775aeff4 | 1886 | |
a7f4ee1f | 1887 | void __init smp_mpic_probe(void) |
775aeff4 ME |
1888 | { |
1889 | int nr_cpus; | |
1890 | ||
1891 | DBG("smp_mpic_probe()...\n"); | |
1892 | ||
53a448c3 | 1893 | nr_cpus = num_possible_cpus(); |
775aeff4 ME |
1894 | |
1895 | DBG("nr_cpus: %d\n", nr_cpus); | |
1896 | ||
1897 | if (nr_cpus > 1) | |
1898 | mpic_request_ipis(); | |
775aeff4 ME |
1899 | } |
1900 | ||
cad5cef6 | 1901 | void smp_mpic_setup_cpu(int cpu) |
775aeff4 ME |
1902 | { |
1903 | mpic_setup_this_cpu(); | |
1904 | } | |
66953ebe MM |
1905 | |
1906 | void mpic_reset_core(int cpu) | |
1907 | { | |
1908 | struct mpic *mpic = mpic_primary; | |
1909 | u32 pir; | |
1910 | int cpuid = get_hard_smp_processor_id(cpu); | |
44f16fcf | 1911 | int i; |
66953ebe MM |
1912 | |
1913 | /* Set target bit for core reset */ | |
1914 | pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1915 | pir |= (1 << cpuid); | |
1916 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); | |
1917 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1918 | ||
1919 | /* Restore target bit after reset complete */ | |
1920 | pir &= ~(1 << cpuid); | |
1921 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); | |
1922 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
44f16fcf MM |
1923 | |
1924 | /* Perform 15 EOI on each reset core to clear pending interrupts. | |
1925 | * This is required for FSL CoreNet based devices */ | |
1926 | if (mpic->flags & MPIC_FSL) { | |
1927 | for (i = 0; i < 15; i++) { | |
1928 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid], | |
1929 | MPIC_CPU_EOI, 0); | |
1930 | } | |
1931 | } | |
66953ebe | 1932 | } |
14cf11af | 1933 | #endif /* CONFIG_SMP */ |
3669e930 JB |
1934 | |
1935 | #ifdef CONFIG_PM | |
f5a592f7 | 1936 | static void mpic_suspend_one(struct mpic *mpic) |
3669e930 | 1937 | { |
3669e930 JB |
1938 | int i; |
1939 | ||
1940 | for (i = 0; i < mpic->num_sources; i++) { | |
1941 | mpic->save_data[i].vecprio = | |
1942 | mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); | |
1943 | mpic->save_data[i].dest = | |
1944 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); | |
1945 | } | |
f5a592f7 RW |
1946 | } |
1947 | ||
1948 | static int mpic_suspend(void) | |
1949 | { | |
1950 | struct mpic *mpic = mpics; | |
1951 | ||
1952 | while (mpic) { | |
1953 | mpic_suspend_one(mpic); | |
1954 | mpic = mpic->next; | |
1955 | } | |
3669e930 JB |
1956 | |
1957 | return 0; | |
1958 | } | |
1959 | ||
f5a592f7 | 1960 | static void mpic_resume_one(struct mpic *mpic) |
3669e930 | 1961 | { |
3669e930 JB |
1962 | int i; |
1963 | ||
1964 | for (i = 0; i < mpic->num_sources; i++) { | |
1965 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), | |
1966 | mpic->save_data[i].vecprio); | |
1967 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), | |
1968 | mpic->save_data[i].dest); | |
1969 | ||
1970 | #ifdef CONFIG_MPIC_U3_HT_IRQS | |
7c9d9360 | 1971 | if (mpic->fixups) { |
3669e930 JB |
1972 | struct mpic_irq_fixup *fixup = &mpic->fixups[i]; |
1973 | ||
1974 | if (fixup->base) { | |
1975 | /* we use the lowest bit in an inverted meaning */ | |
1976 | if ((mpic->save_data[i].fixup_data & 1) == 0) | |
1977 | continue; | |
1978 | ||
1979 | /* Enable and configure */ | |
1980 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
1981 | ||
1982 | writel(mpic->save_data[i].fixup_data & ~1, | |
1983 | fixup->base + 4); | |
1984 | } | |
1985 | } | |
1986 | #endif | |
1987 | } /* end for loop */ | |
f5a592f7 | 1988 | } |
3669e930 | 1989 | |
f5a592f7 RW |
1990 | static void mpic_resume(void) |
1991 | { | |
1992 | struct mpic *mpic = mpics; | |
1993 | ||
1994 | while (mpic) { | |
1995 | mpic_resume_one(mpic); | |
1996 | mpic = mpic->next; | |
1997 | } | |
3669e930 | 1998 | } |
3669e930 | 1999 | |
f5a592f7 | 2000 | static struct syscore_ops mpic_syscore_ops = { |
3669e930 JB |
2001 | .resume = mpic_resume, |
2002 | .suspend = mpic_suspend, | |
3669e930 JB |
2003 | }; |
2004 | ||
2005 | static int mpic_init_sys(void) | |
2006 | { | |
4ad5e883 AD |
2007 | int rc; |
2008 | ||
f5a592f7 | 2009 | register_syscore_ops(&mpic_syscore_ops); |
4ad5e883 AD |
2010 | rc = subsys_system_register(&mpic_subsys, NULL); |
2011 | if (rc) { | |
2012 | unregister_syscore_ops(&mpic_syscore_ops); | |
2013 | pr_err("mpic: Failed to register subsystem!\n"); | |
2014 | return rc; | |
2015 | } | |
9e6f31a9 | 2016 | |
f5a592f7 | 2017 | return 0; |
3669e930 JB |
2018 | } |
2019 | ||
2020 | device_initcall(mpic_init_sys); | |
f5a592f7 | 2021 | #endif |