Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * arch/powerpc/kernel/mpic.c | |
3 | * | |
4 | * Driver for interrupt controllers following the OpenPIC standard, the | |
5 | * common implementation beeing IBM's MPIC. This driver also can deal | |
6 | * with various broken implementations of this HW. | |
7 | * | |
8 | * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. | |
9 | * | |
10 | * This file is subject to the terms and conditions of the GNU General Public | |
11 | * License. See the file COPYING in the main directory of this archive | |
12 | * for more details. | |
13 | */ | |
14 | ||
15 | #undef DEBUG | |
1beb6a7d BH |
16 | #undef DEBUG_IPI |
17 | #undef DEBUG_IRQ | |
18 | #undef DEBUG_LOW | |
14cf11af | 19 | |
14cf11af PM |
20 | #include <linux/types.h> |
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/smp.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/bootmem.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/pci.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
f5a592f7 | 30 | #include <linux/syscore_ops.h> |
14cf11af PM |
31 | |
32 | #include <asm/ptrace.h> | |
33 | #include <asm/signal.h> | |
34 | #include <asm/io.h> | |
35 | #include <asm/pgtable.h> | |
36 | #include <asm/irq.h> | |
37 | #include <asm/machdep.h> | |
38 | #include <asm/mpic.h> | |
39 | #include <asm/smp.h> | |
40 | ||
a7de7c74 ME |
41 | #include "mpic.h" |
42 | ||
14cf11af PM |
43 | #ifdef DEBUG |
44 | #define DBG(fmt...) printk(fmt) | |
45 | #else | |
46 | #define DBG(fmt...) | |
47 | #endif | |
48 | ||
49 | static struct mpic *mpics; | |
50 | static struct mpic *mpic_primary; | |
203041ad | 51 | static DEFINE_RAW_SPINLOCK(mpic_lock); |
14cf11af | 52 | |
c0c0d996 | 53 | #ifdef CONFIG_PPC32 /* XXX for now */ |
e40c7f02 AW |
54 | #ifdef CONFIG_IRQ_ALL_CPUS |
55 | #define distribute_irqs (1) | |
56 | #else | |
57 | #define distribute_irqs (0) | |
58 | #endif | |
c0c0d996 | 59 | #endif |
14cf11af | 60 | |
7233593b ZR |
61 | #ifdef CONFIG_MPIC_WEIRD |
62 | static u32 mpic_infos[][MPIC_IDX_END] = { | |
63 | [0] = { /* Original OpenPIC compatible MPIC */ | |
64 | MPIC_GREG_BASE, | |
65 | MPIC_GREG_FEATURE_0, | |
66 | MPIC_GREG_GLOBAL_CONF_0, | |
67 | MPIC_GREG_VENDOR_ID, | |
68 | MPIC_GREG_IPI_VECTOR_PRI_0, | |
69 | MPIC_GREG_IPI_STRIDE, | |
70 | MPIC_GREG_SPURIOUS, | |
71 | MPIC_GREG_TIMER_FREQ, | |
72 | ||
73 | MPIC_TIMER_BASE, | |
74 | MPIC_TIMER_STRIDE, | |
75 | MPIC_TIMER_CURRENT_CNT, | |
76 | MPIC_TIMER_BASE_CNT, | |
77 | MPIC_TIMER_VECTOR_PRI, | |
78 | MPIC_TIMER_DESTINATION, | |
79 | ||
80 | MPIC_CPU_BASE, | |
81 | MPIC_CPU_STRIDE, | |
82 | MPIC_CPU_IPI_DISPATCH_0, | |
83 | MPIC_CPU_IPI_DISPATCH_STRIDE, | |
84 | MPIC_CPU_CURRENT_TASK_PRI, | |
85 | MPIC_CPU_WHOAMI, | |
86 | MPIC_CPU_INTACK, | |
87 | MPIC_CPU_EOI, | |
f365355e | 88 | MPIC_CPU_MCACK, |
7233593b ZR |
89 | |
90 | MPIC_IRQ_BASE, | |
91 | MPIC_IRQ_STRIDE, | |
92 | MPIC_IRQ_VECTOR_PRI, | |
93 | MPIC_VECPRI_VECTOR_MASK, | |
94 | MPIC_VECPRI_POLARITY_POSITIVE, | |
95 | MPIC_VECPRI_POLARITY_NEGATIVE, | |
96 | MPIC_VECPRI_SENSE_LEVEL, | |
97 | MPIC_VECPRI_SENSE_EDGE, | |
98 | MPIC_VECPRI_POLARITY_MASK, | |
99 | MPIC_VECPRI_SENSE_MASK, | |
100 | MPIC_IRQ_DESTINATION | |
101 | }, | |
102 | [1] = { /* Tsi108/109 PIC */ | |
103 | TSI108_GREG_BASE, | |
104 | TSI108_GREG_FEATURE_0, | |
105 | TSI108_GREG_GLOBAL_CONF_0, | |
106 | TSI108_GREG_VENDOR_ID, | |
107 | TSI108_GREG_IPI_VECTOR_PRI_0, | |
108 | TSI108_GREG_IPI_STRIDE, | |
109 | TSI108_GREG_SPURIOUS, | |
110 | TSI108_GREG_TIMER_FREQ, | |
111 | ||
112 | TSI108_TIMER_BASE, | |
113 | TSI108_TIMER_STRIDE, | |
114 | TSI108_TIMER_CURRENT_CNT, | |
115 | TSI108_TIMER_BASE_CNT, | |
116 | TSI108_TIMER_VECTOR_PRI, | |
117 | TSI108_TIMER_DESTINATION, | |
118 | ||
119 | TSI108_CPU_BASE, | |
120 | TSI108_CPU_STRIDE, | |
121 | TSI108_CPU_IPI_DISPATCH_0, | |
122 | TSI108_CPU_IPI_DISPATCH_STRIDE, | |
123 | TSI108_CPU_CURRENT_TASK_PRI, | |
124 | TSI108_CPU_WHOAMI, | |
125 | TSI108_CPU_INTACK, | |
126 | TSI108_CPU_EOI, | |
f365355e | 127 | TSI108_CPU_MCACK, |
7233593b ZR |
128 | |
129 | TSI108_IRQ_BASE, | |
130 | TSI108_IRQ_STRIDE, | |
131 | TSI108_IRQ_VECTOR_PRI, | |
132 | TSI108_VECPRI_VECTOR_MASK, | |
133 | TSI108_VECPRI_POLARITY_POSITIVE, | |
134 | TSI108_VECPRI_POLARITY_NEGATIVE, | |
135 | TSI108_VECPRI_SENSE_LEVEL, | |
136 | TSI108_VECPRI_SENSE_EDGE, | |
137 | TSI108_VECPRI_POLARITY_MASK, | |
138 | TSI108_VECPRI_SENSE_MASK, | |
139 | TSI108_IRQ_DESTINATION | |
140 | }, | |
141 | }; | |
142 | ||
143 | #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] | |
144 | ||
145 | #else /* CONFIG_MPIC_WEIRD */ | |
146 | ||
147 | #define MPIC_INFO(name) MPIC_##name | |
148 | ||
149 | #endif /* CONFIG_MPIC_WEIRD */ | |
150 | ||
d6a2639b MI |
151 | static inline unsigned int mpic_processor_id(struct mpic *mpic) |
152 | { | |
153 | unsigned int cpu = 0; | |
154 | ||
155 | if (mpic->flags & MPIC_PRIMARY) | |
156 | cpu = hard_smp_processor_id(); | |
157 | ||
158 | return cpu; | |
159 | } | |
160 | ||
14cf11af PM |
161 | /* |
162 | * Register accessor functions | |
163 | */ | |
164 | ||
165 | ||
fbf0274e BH |
166 | static inline u32 _mpic_read(enum mpic_reg_type type, |
167 | struct mpic_reg_bank *rb, | |
168 | unsigned int reg) | |
14cf11af | 169 | { |
fbf0274e BH |
170 | switch(type) { |
171 | #ifdef CONFIG_PPC_DCR | |
172 | case mpic_access_dcr: | |
83f34df4 | 173 | return dcr_read(rb->dhost, reg); |
fbf0274e BH |
174 | #endif |
175 | case mpic_access_mmio_be: | |
176 | return in_be32(rb->base + (reg >> 2)); | |
177 | case mpic_access_mmio_le: | |
178 | default: | |
179 | return in_le32(rb->base + (reg >> 2)); | |
180 | } | |
14cf11af PM |
181 | } |
182 | ||
fbf0274e BH |
183 | static inline void _mpic_write(enum mpic_reg_type type, |
184 | struct mpic_reg_bank *rb, | |
185 | unsigned int reg, u32 value) | |
14cf11af | 186 | { |
fbf0274e BH |
187 | switch(type) { |
188 | #ifdef CONFIG_PPC_DCR | |
189 | case mpic_access_dcr: | |
d9d1063d JB |
190 | dcr_write(rb->dhost, reg, value); |
191 | break; | |
fbf0274e BH |
192 | #endif |
193 | case mpic_access_mmio_be: | |
d9d1063d JB |
194 | out_be32(rb->base + (reg >> 2), value); |
195 | break; | |
fbf0274e BH |
196 | case mpic_access_mmio_le: |
197 | default: | |
d9d1063d JB |
198 | out_le32(rb->base + (reg >> 2), value); |
199 | break; | |
fbf0274e | 200 | } |
14cf11af PM |
201 | } |
202 | ||
203 | static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) | |
204 | { | |
fbf0274e | 205 | enum mpic_reg_type type = mpic->reg_type; |
7233593b ZR |
206 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
207 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 208 | |
fbf0274e BH |
209 | if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) |
210 | type = mpic_access_mmio_be; | |
211 | return _mpic_read(type, &mpic->gregs, offset); | |
14cf11af PM |
212 | } |
213 | ||
214 | static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) | |
215 | { | |
7233593b ZR |
216 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
217 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 218 | |
fbf0274e | 219 | _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); |
14cf11af PM |
220 | } |
221 | ||
222 | static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) | |
223 | { | |
d6a2639b | 224 | unsigned int cpu = mpic_processor_id(mpic); |
14cf11af | 225 | |
fbf0274e | 226 | return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); |
14cf11af PM |
227 | } |
228 | ||
229 | static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) | |
230 | { | |
d6a2639b | 231 | unsigned int cpu = mpic_processor_id(mpic); |
14cf11af | 232 | |
fbf0274e | 233 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); |
14cf11af PM |
234 | } |
235 | ||
236 | static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) | |
237 | { | |
238 | unsigned int isu = src_no >> mpic->isu_shift; | |
239 | unsigned int idx = src_no & mpic->isu_mask; | |
11a6b292 | 240 | unsigned int val; |
14cf11af | 241 | |
11a6b292 ME |
242 | val = _mpic_read(mpic->reg_type, &mpic->isus[isu], |
243 | reg + (idx * MPIC_INFO(IRQ_STRIDE))); | |
0d72ba93 OJ |
244 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
245 | if (reg == 0) | |
11a6b292 ME |
246 | val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | |
247 | mpic->isu_reg0_shadow[src_no]; | |
0d72ba93 | 248 | #endif |
11a6b292 | 249 | return val; |
14cf11af PM |
250 | } |
251 | ||
252 | static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, | |
253 | unsigned int reg, u32 value) | |
254 | { | |
255 | unsigned int isu = src_no >> mpic->isu_shift; | |
256 | unsigned int idx = src_no & mpic->isu_mask; | |
257 | ||
fbf0274e | 258 | _mpic_write(mpic->reg_type, &mpic->isus[isu], |
7233593b | 259 | reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); |
0d72ba93 OJ |
260 | |
261 | #ifdef CONFIG_MPIC_BROKEN_REGREAD | |
262 | if (reg == 0) | |
11a6b292 ME |
263 | mpic->isu_reg0_shadow[src_no] = |
264 | value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY); | |
0d72ba93 | 265 | #endif |
14cf11af PM |
266 | } |
267 | ||
fbf0274e BH |
268 | #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) |
269 | #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) | |
14cf11af PM |
270 | #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) |
271 | #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) | |
272 | #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) | |
273 | #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) | |
274 | #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) | |
275 | #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) | |
276 | ||
277 | ||
278 | /* | |
279 | * Low level utility functions | |
280 | */ | |
281 | ||
282 | ||
c51a3fdc | 283 | static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, |
fbf0274e BH |
284 | struct mpic_reg_bank *rb, unsigned int offset, |
285 | unsigned int size) | |
286 | { | |
287 | rb->base = ioremap(phys_addr + offset, size); | |
288 | BUG_ON(rb->base == NULL); | |
289 | } | |
290 | ||
291 | #ifdef CONFIG_PPC_DCR | |
5a2642f6 BH |
292 | static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node, |
293 | struct mpic_reg_bank *rb, | |
fbf0274e BH |
294 | unsigned int offset, unsigned int size) |
295 | { | |
0411a5e2 ME |
296 | const u32 *dbasep; |
297 | ||
5a2642f6 | 298 | dbasep = of_get_property(node, "dcr-reg", NULL); |
0411a5e2 | 299 | |
5a2642f6 | 300 | rb->dhost = dcr_map(node, *dbasep + offset, size); |
fbf0274e BH |
301 | BUG_ON(!DCR_MAP_OK(rb->dhost)); |
302 | } | |
303 | ||
5a2642f6 BH |
304 | static inline void mpic_map(struct mpic *mpic, struct device_node *node, |
305 | phys_addr_t phys_addr, struct mpic_reg_bank *rb, | |
306 | unsigned int offset, unsigned int size) | |
fbf0274e BH |
307 | { |
308 | if (mpic->flags & MPIC_USES_DCR) | |
5a2642f6 | 309 | _mpic_map_dcr(mpic, node, rb, offset, size); |
fbf0274e BH |
310 | else |
311 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); | |
312 | } | |
313 | #else /* CONFIG_PPC_DCR */ | |
5a2642f6 | 314 | #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) |
fbf0274e BH |
315 | #endif /* !CONFIG_PPC_DCR */ |
316 | ||
317 | ||
14cf11af PM |
318 | |
319 | /* Check if we have one of those nice broken MPICs with a flipped endian on | |
320 | * reads from IPI registers | |
321 | */ | |
322 | static void __init mpic_test_broken_ipi(struct mpic *mpic) | |
323 | { | |
324 | u32 r; | |
325 | ||
7233593b ZR |
326 | mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); |
327 | r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); | |
14cf11af PM |
328 | |
329 | if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { | |
330 | printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); | |
331 | mpic->flags |= MPIC_BROKEN_IPI; | |
332 | } | |
333 | } | |
334 | ||
6cfef5b2 | 335 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
14cf11af PM |
336 | |
337 | /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) | |
338 | * to force the edge setting on the MPIC and do the ack workaround. | |
339 | */ | |
1beb6a7d | 340 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) |
14cf11af | 341 | { |
1beb6a7d | 342 | if (source >= 128 || !mpic->fixups) |
14cf11af | 343 | return 0; |
1beb6a7d | 344 | return mpic->fixups[source].base != NULL; |
14cf11af PM |
345 | } |
346 | ||
c4b22f26 | 347 | |
1beb6a7d | 348 | static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) |
14cf11af | 349 | { |
1beb6a7d | 350 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
14cf11af | 351 | |
1beb6a7d BH |
352 | if (fixup->applebase) { |
353 | unsigned int soff = (fixup->index >> 3) & ~3; | |
354 | unsigned int mask = 1U << (fixup->index & 0x1f); | |
355 | writel(mask, fixup->applebase + soff); | |
356 | } else { | |
203041ad | 357 | raw_spin_lock(&mpic->fixup_lock); |
1beb6a7d BH |
358 | writeb(0x11 + 2 * fixup->index, fixup->base + 2); |
359 | writel(fixup->data, fixup->base + 4); | |
203041ad | 360 | raw_spin_unlock(&mpic->fixup_lock); |
1beb6a7d | 361 | } |
14cf11af PM |
362 | } |
363 | ||
1beb6a7d | 364 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, |
24a3f2e8 | 365 | bool level) |
1beb6a7d BH |
366 | { |
367 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
368 | unsigned long flags; | |
369 | u32 tmp; | |
370 | ||
371 | if (fixup->base == NULL) | |
372 | return; | |
373 | ||
24a3f2e8 TG |
374 | DBG("startup_ht_interrupt(0x%x) index: %d\n", |
375 | source, fixup->index); | |
203041ad | 376 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
1beb6a7d BH |
377 | /* Enable and configure */ |
378 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
379 | tmp = readl(fixup->base + 4); | |
380 | tmp &= ~(0x23U); | |
24a3f2e8 | 381 | if (level) |
1beb6a7d BH |
382 | tmp |= 0x22; |
383 | writel(tmp, fixup->base + 4); | |
203041ad | 384 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
3669e930 JB |
385 | |
386 | #ifdef CONFIG_PM | |
387 | /* use the lowest bit inverted to the actual HW, | |
388 | * set if this fixup was enabled, clear otherwise */ | |
389 | mpic->save_data[source].fixup_data = tmp | 1; | |
390 | #endif | |
1beb6a7d BH |
391 | } |
392 | ||
24a3f2e8 | 393 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source) |
1beb6a7d BH |
394 | { |
395 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
396 | unsigned long flags; | |
397 | u32 tmp; | |
398 | ||
399 | if (fixup->base == NULL) | |
400 | return; | |
401 | ||
24a3f2e8 | 402 | DBG("shutdown_ht_interrupt(0x%x)\n", source); |
1beb6a7d BH |
403 | |
404 | /* Disable */ | |
203041ad | 405 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
1beb6a7d BH |
406 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
407 | tmp = readl(fixup->base + 4); | |
72b13819 | 408 | tmp |= 1; |
1beb6a7d | 409 | writel(tmp, fixup->base + 4); |
203041ad | 410 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
3669e930 JB |
411 | |
412 | #ifdef CONFIG_PM | |
413 | /* use the lowest bit inverted to the actual HW, | |
414 | * set if this fixup was enabled, clear otherwise */ | |
415 | mpic->save_data[source].fixup_data = tmp & ~1; | |
416 | #endif | |
1beb6a7d | 417 | } |
14cf11af | 418 | |
812fd1fd ME |
419 | #ifdef CONFIG_PCI_MSI |
420 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, | |
421 | unsigned int devfn) | |
422 | { | |
423 | u8 __iomem *base; | |
424 | u8 pos, flags; | |
425 | u64 addr = 0; | |
426 | ||
427 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; | |
428 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
429 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
430 | if (id == PCI_CAP_ID_HT) { | |
431 | id = readb(devbase + pos + 3); | |
432 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) | |
433 | break; | |
434 | } | |
435 | } | |
436 | ||
437 | if (pos == 0) | |
438 | return; | |
439 | ||
440 | base = devbase + pos; | |
441 | ||
442 | flags = readb(base + HT_MSI_FLAGS); | |
443 | if (!(flags & HT_MSI_FLAGS_FIXED)) { | |
444 | addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; | |
445 | addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); | |
446 | } | |
447 | ||
fe333321 | 448 | printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", |
812fd1fd ME |
449 | PCI_SLOT(devfn), PCI_FUNC(devfn), |
450 | flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); | |
451 | ||
452 | if (!(flags & HT_MSI_FLAGS_ENABLE)) | |
453 | writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); | |
454 | } | |
455 | #else | |
456 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, | |
457 | unsigned int devfn) | |
458 | { | |
459 | return; | |
460 | } | |
461 | #endif | |
462 | ||
1beb6a7d BH |
463 | static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, |
464 | unsigned int devfn, u32 vdid) | |
14cf11af | 465 | { |
c4b22f26 | 466 | int i, irq, n; |
1beb6a7d | 467 | u8 __iomem *base; |
14cf11af | 468 | u32 tmp; |
c4b22f26 | 469 | u8 pos; |
14cf11af | 470 | |
1beb6a7d BH |
471 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; |
472 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
473 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
46ff3463 | 474 | if (id == PCI_CAP_ID_HT) { |
c4b22f26 | 475 | id = readb(devbase + pos + 3); |
beb7cc82 | 476 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) |
c4b22f26 SB |
477 | break; |
478 | } | |
14cf11af | 479 | } |
c4b22f26 SB |
480 | if (pos == 0) |
481 | return; | |
482 | ||
1beb6a7d BH |
483 | base = devbase + pos; |
484 | writeb(0x01, base + 2); | |
485 | n = (readl(base + 4) >> 16) & 0xff; | |
14cf11af | 486 | |
1beb6a7d BH |
487 | printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" |
488 | " has %d irqs\n", | |
489 | devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); | |
c4b22f26 SB |
490 | |
491 | for (i = 0; i <= n; i++) { | |
1beb6a7d BH |
492 | writeb(0x10 + 2 * i, base + 2); |
493 | tmp = readl(base + 4); | |
14cf11af | 494 | irq = (tmp >> 16) & 0xff; |
1beb6a7d BH |
495 | DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); |
496 | /* mask it , will be unmasked later */ | |
497 | tmp |= 0x1; | |
498 | writel(tmp, base + 4); | |
499 | mpic->fixups[irq].index = i; | |
500 | mpic->fixups[irq].base = base; | |
501 | /* Apple HT PIC has a non-standard way of doing EOIs */ | |
502 | if ((vdid & 0xffff) == 0x106b) | |
503 | mpic->fixups[irq].applebase = devbase + 0x60; | |
504 | else | |
505 | mpic->fixups[irq].applebase = NULL; | |
506 | writeb(0x11 + 2 * i, base + 2); | |
507 | mpic->fixups[irq].data = readl(base + 4) | 0x80000000; | |
14cf11af PM |
508 | } |
509 | } | |
510 | ||
c4b22f26 | 511 | |
1beb6a7d | 512 | static void __init mpic_scan_ht_pics(struct mpic *mpic) |
14cf11af PM |
513 | { |
514 | unsigned int devfn; | |
515 | u8 __iomem *cfgspace; | |
516 | ||
1beb6a7d | 517 | printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); |
14cf11af PM |
518 | |
519 | /* Allocate fixups array */ | |
ea96025a | 520 | mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL); |
14cf11af | 521 | BUG_ON(mpic->fixups == NULL); |
14cf11af PM |
522 | |
523 | /* Init spinlock */ | |
203041ad | 524 | raw_spin_lock_init(&mpic->fixup_lock); |
14cf11af | 525 | |
c4b22f26 SB |
526 | /* Map U3 config space. We assume all IO-APICs are on the primary bus |
527 | * so we only need to map 64kB. | |
14cf11af | 528 | */ |
c4b22f26 | 529 | cfgspace = ioremap(0xf2000000, 0x10000); |
14cf11af PM |
530 | BUG_ON(cfgspace == NULL); |
531 | ||
1beb6a7d BH |
532 | /* Now we scan all slots. We do a very quick scan, we read the header |
533 | * type, vendor ID and device ID only, that's plenty enough | |
14cf11af | 534 | */ |
c4b22f26 | 535 | for (devfn = 0; devfn < 0x100; devfn++) { |
14cf11af PM |
536 | u8 __iomem *devbase = cfgspace + (devfn << 8); |
537 | u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); | |
538 | u32 l = readl(devbase + PCI_VENDOR_ID); | |
1beb6a7d | 539 | u16 s; |
14cf11af PM |
540 | |
541 | DBG("devfn %x, l: %x\n", devfn, l); | |
542 | ||
543 | /* If no device, skip */ | |
544 | if (l == 0xffffffff || l == 0x00000000 || | |
545 | l == 0x0000ffff || l == 0xffff0000) | |
546 | goto next; | |
1beb6a7d BH |
547 | /* Check if is supports capability lists */ |
548 | s = readw(devbase + PCI_STATUS); | |
549 | if (!(s & PCI_STATUS_CAP_LIST)) | |
550 | goto next; | |
14cf11af | 551 | |
1beb6a7d | 552 | mpic_scan_ht_pic(mpic, devbase, devfn, l); |
812fd1fd | 553 | mpic_scan_ht_msi(mpic, devbase, devfn); |
c4b22f26 | 554 | |
14cf11af PM |
555 | next: |
556 | /* next device, if function 0 */ | |
c4b22f26 | 557 | if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) |
14cf11af PM |
558 | devfn += 7; |
559 | } | |
560 | } | |
561 | ||
6cfef5b2 | 562 | #else /* CONFIG_MPIC_U3_HT_IRQS */ |
6e99e458 BH |
563 | |
564 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) | |
565 | { | |
566 | return 0; | |
567 | } | |
568 | ||
569 | static void __init mpic_scan_ht_pics(struct mpic *mpic) | |
570 | { | |
571 | } | |
572 | ||
6cfef5b2 | 573 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
14cf11af | 574 | |
3c10c9c4 | 575 | #ifdef CONFIG_SMP |
2ef613cb | 576 | static int irq_choose_cpu(const struct cpumask *mask) |
3c10c9c4 | 577 | { |
3c10c9c4 KG |
578 | int cpuid; |
579 | ||
38e1313f | 580 | if (cpumask_equal(mask, cpu_all_mask)) { |
2ef613cb | 581 | static int irq_rover = 0; |
203041ad | 582 | static DEFINE_RAW_SPINLOCK(irq_rover_lock); |
3c10c9c4 KG |
583 | unsigned long flags; |
584 | ||
585 | /* Round-robin distribution... */ | |
586 | do_round_robin: | |
203041ad | 587 | raw_spin_lock_irqsave(&irq_rover_lock, flags); |
3c10c9c4 | 588 | |
2ef613cb BH |
589 | irq_rover = cpumask_next(irq_rover, cpu_online_mask); |
590 | if (irq_rover >= nr_cpu_ids) | |
591 | irq_rover = cpumask_first(cpu_online_mask); | |
592 | ||
3c10c9c4 | 593 | cpuid = irq_rover; |
3c10c9c4 | 594 | |
203041ad | 595 | raw_spin_unlock_irqrestore(&irq_rover_lock, flags); |
3c10c9c4 | 596 | } else { |
38e1313f YL |
597 | cpuid = cpumask_first_and(mask, cpu_online_mask); |
598 | if (cpuid >= nr_cpu_ids) | |
3c10c9c4 | 599 | goto do_round_robin; |
3c10c9c4 KG |
600 | } |
601 | ||
7a0d7940 | 602 | return get_hard_smp_processor_id(cpuid); |
3c10c9c4 KG |
603 | } |
604 | #else | |
2ef613cb | 605 | static int irq_choose_cpu(const struct cpumask *mask) |
3c10c9c4 KG |
606 | { |
607 | return hard_smp_processor_id(); | |
608 | } | |
609 | #endif | |
14cf11af | 610 | |
0ebfff14 BH |
611 | #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) |
612 | ||
14cf11af | 613 | /* Find an mpic associated with a given linux interrupt */ |
d69a78d7 | 614 | static struct mpic *mpic_find(unsigned int irq) |
14cf11af | 615 | { |
0ebfff14 BH |
616 | if (irq < NUM_ISA_INTERRUPTS) |
617 | return NULL; | |
7df2457d | 618 | |
ec775d0e | 619 | return irq_get_chip_data(irq); |
d69a78d7 | 620 | } |
7df2457d | 621 | |
d69a78d7 TB |
622 | /* Determine if the linux irq is an IPI */ |
623 | static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) | |
624 | { | |
625 | unsigned int src = mpic_irq_to_hw(irq); | |
0ebfff14 | 626 | |
d69a78d7 | 627 | return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); |
14cf11af PM |
628 | } |
629 | ||
d69a78d7 | 630 | |
14cf11af PM |
631 | /* Convert a cpu mask from logical to physical cpu numbers. */ |
632 | static inline u32 mpic_physmask(u32 cpumask) | |
633 | { | |
634 | int i; | |
635 | u32 mask = 0; | |
636 | ||
637 | for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) | |
638 | mask |= (cpumask & 1) << get_hard_smp_processor_id(i); | |
639 | return mask; | |
640 | } | |
641 | ||
642 | #ifdef CONFIG_SMP | |
643 | /* Get the mpic structure from the IPI number */ | |
835c0553 | 644 | static inline struct mpic * mpic_from_ipi(struct irq_data *d) |
14cf11af | 645 | { |
835c0553 | 646 | return irq_data_get_irq_chip_data(d); |
14cf11af PM |
647 | } |
648 | #endif | |
649 | ||
650 | /* Get the mpic structure from the irq number */ | |
651 | static inline struct mpic * mpic_from_irq(unsigned int irq) | |
652 | { | |
ec775d0e | 653 | return irq_get_chip_data(irq); |
835c0553 LB |
654 | } |
655 | ||
656 | /* Get the mpic structure from the irq data */ | |
657 | static inline struct mpic * mpic_from_irq_data(struct irq_data *d) | |
658 | { | |
659 | return irq_data_get_irq_chip_data(d); | |
14cf11af PM |
660 | } |
661 | ||
662 | /* Send an EOI */ | |
663 | static inline void mpic_eoi(struct mpic *mpic) | |
664 | { | |
7233593b ZR |
665 | mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); |
666 | (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); | |
14cf11af PM |
667 | } |
668 | ||
14cf11af PM |
669 | /* |
670 | * Linux descriptor level callbacks | |
671 | */ | |
672 | ||
673 | ||
835c0553 | 674 | void mpic_unmask_irq(struct irq_data *d) |
14cf11af PM |
675 | { |
676 | unsigned int loops = 100000; | |
835c0553 LB |
677 | struct mpic *mpic = mpic_from_irq_data(d); |
678 | unsigned int src = mpic_irq_to_hw(d->irq); | |
14cf11af | 679 | |
835c0553 | 680 | DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); |
14cf11af | 681 | |
7233593b ZR |
682 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
683 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & | |
e5356640 | 684 | ~MPIC_VECPRI_MASK); |
14cf11af PM |
685 | /* make sure mask gets to controller before we return to user */ |
686 | do { | |
687 | if (!loops--) { | |
8bfc5e36 SW |
688 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
689 | __func__, src); | |
14cf11af PM |
690 | break; |
691 | } | |
7233593b | 692 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); |
14cf11af PM |
693 | } |
694 | ||
835c0553 | 695 | void mpic_mask_irq(struct irq_data *d) |
14cf11af PM |
696 | { |
697 | unsigned int loops = 100000; | |
835c0553 LB |
698 | struct mpic *mpic = mpic_from_irq_data(d); |
699 | unsigned int src = mpic_irq_to_hw(d->irq); | |
14cf11af | 700 | |
835c0553 | 701 | DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); |
14cf11af | 702 | |
7233593b ZR |
703 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
704 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | | |
e5356640 | 705 | MPIC_VECPRI_MASK); |
14cf11af PM |
706 | |
707 | /* make sure mask gets to controller before we return to user */ | |
708 | do { | |
709 | if (!loops--) { | |
8bfc5e36 SW |
710 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
711 | __func__, src); | |
14cf11af PM |
712 | break; |
713 | } | |
7233593b | 714 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); |
14cf11af PM |
715 | } |
716 | ||
835c0553 | 717 | void mpic_end_irq(struct irq_data *d) |
1beb6a7d | 718 | { |
835c0553 | 719 | struct mpic *mpic = mpic_from_irq_data(d); |
b9e5b4e6 BH |
720 | |
721 | #ifdef DEBUG_IRQ | |
835c0553 | 722 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
b9e5b4e6 BH |
723 | #endif |
724 | /* We always EOI on end_irq() even for edge interrupts since that | |
725 | * should only lower the priority, the MPIC should have properly | |
726 | * latched another edge interrupt coming in anyway | |
727 | */ | |
728 | ||
729 | mpic_eoi(mpic); | |
730 | } | |
731 | ||
6cfef5b2 | 732 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 733 | |
835c0553 | 734 | static void mpic_unmask_ht_irq(struct irq_data *d) |
b9e5b4e6 | 735 | { |
835c0553 LB |
736 | struct mpic *mpic = mpic_from_irq_data(d); |
737 | unsigned int src = mpic_irq_to_hw(d->irq); | |
1beb6a7d | 738 | |
835c0553 | 739 | mpic_unmask_irq(d); |
1beb6a7d | 740 | |
24a3f2e8 | 741 | if (irqd_is_level_type(d)) |
b9e5b4e6 BH |
742 | mpic_ht_end_irq(mpic, src); |
743 | } | |
744 | ||
835c0553 | 745 | static unsigned int mpic_startup_ht_irq(struct irq_data *d) |
b9e5b4e6 | 746 | { |
835c0553 LB |
747 | struct mpic *mpic = mpic_from_irq_data(d); |
748 | unsigned int src = mpic_irq_to_hw(d->irq); | |
1beb6a7d | 749 | |
835c0553 | 750 | mpic_unmask_irq(d); |
24a3f2e8 | 751 | mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d)); |
b9e5b4e6 BH |
752 | |
753 | return 0; | |
1beb6a7d BH |
754 | } |
755 | ||
835c0553 | 756 | static void mpic_shutdown_ht_irq(struct irq_data *d) |
b9e5b4e6 | 757 | { |
835c0553 LB |
758 | struct mpic *mpic = mpic_from_irq_data(d); |
759 | unsigned int src = mpic_irq_to_hw(d->irq); | |
b9e5b4e6 | 760 | |
24a3f2e8 | 761 | mpic_shutdown_ht_interrupt(mpic, src); |
835c0553 | 762 | mpic_mask_irq(d); |
b9e5b4e6 BH |
763 | } |
764 | ||
835c0553 | 765 | static void mpic_end_ht_irq(struct irq_data *d) |
14cf11af | 766 | { |
835c0553 LB |
767 | struct mpic *mpic = mpic_from_irq_data(d); |
768 | unsigned int src = mpic_irq_to_hw(d->irq); | |
14cf11af | 769 | |
1beb6a7d | 770 | #ifdef DEBUG_IRQ |
835c0553 | 771 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
1beb6a7d | 772 | #endif |
14cf11af PM |
773 | /* We always EOI on end_irq() even for edge interrupts since that |
774 | * should only lower the priority, the MPIC should have properly | |
775 | * latched another edge interrupt coming in anyway | |
776 | */ | |
777 | ||
24a3f2e8 | 778 | if (irqd_is_level_type(d)) |
b9e5b4e6 | 779 | mpic_ht_end_irq(mpic, src); |
14cf11af PM |
780 | mpic_eoi(mpic); |
781 | } | |
6cfef5b2 | 782 | #endif /* !CONFIG_MPIC_U3_HT_IRQS */ |
b9e5b4e6 | 783 | |
14cf11af PM |
784 | #ifdef CONFIG_SMP |
785 | ||
835c0553 | 786 | static void mpic_unmask_ipi(struct irq_data *d) |
14cf11af | 787 | { |
835c0553 LB |
788 | struct mpic *mpic = mpic_from_ipi(d); |
789 | unsigned int src = mpic_irq_to_hw(d->irq) - mpic->ipi_vecs[0]; | |
14cf11af | 790 | |
835c0553 | 791 | DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); |
14cf11af PM |
792 | mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); |
793 | } | |
794 | ||
835c0553 | 795 | static void mpic_mask_ipi(struct irq_data *d) |
14cf11af PM |
796 | { |
797 | /* NEVER disable an IPI... that's just plain wrong! */ | |
798 | } | |
799 | ||
835c0553 | 800 | static void mpic_end_ipi(struct irq_data *d) |
14cf11af | 801 | { |
835c0553 | 802 | struct mpic *mpic = mpic_from_ipi(d); |
14cf11af PM |
803 | |
804 | /* | |
805 | * IPIs are marked IRQ_PER_CPU. This has the side effect of | |
806 | * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from | |
807 | * applying to them. We EOI them late to avoid re-entering. | |
6714465e | 808 | * We mark IPI's with IRQF_DISABLED as they must run with |
14cf11af PM |
809 | * irqs disabled. |
810 | */ | |
811 | mpic_eoi(mpic); | |
812 | } | |
813 | ||
814 | #endif /* CONFIG_SMP */ | |
815 | ||
835c0553 LB |
816 | int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
817 | bool force) | |
14cf11af | 818 | { |
835c0553 LB |
819 | struct mpic *mpic = mpic_from_irq_data(d); |
820 | unsigned int src = mpic_irq_to_hw(d->irq); | |
14cf11af | 821 | |
3c10c9c4 | 822 | if (mpic->flags & MPIC_SINGLE_DEST_CPU) { |
38e1313f | 823 | int cpuid = irq_choose_cpu(cpumask); |
14cf11af | 824 | |
3c10c9c4 KG |
825 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); |
826 | } else { | |
2ef613cb | 827 | cpumask_var_t tmp; |
14cf11af | 828 | |
2ef613cb BH |
829 | alloc_cpumask_var(&tmp, GFP_KERNEL); |
830 | ||
831 | cpumask_and(tmp, cpumask, cpu_online_mask); | |
3c10c9c4 KG |
832 | |
833 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), | |
2ef613cb BH |
834 | mpic_physmask(cpumask_bits(tmp)[0])); |
835 | ||
836 | free_cpumask_var(tmp); | |
3c10c9c4 | 837 | } |
d5dedd45 YL |
838 | |
839 | return 0; | |
14cf11af PM |
840 | } |
841 | ||
7233593b | 842 | static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) |
0ebfff14 | 843 | { |
0ebfff14 | 844 | /* Now convert sense value */ |
6e99e458 | 845 | switch(type & IRQ_TYPE_SENSE_MASK) { |
0ebfff14 | 846 | case IRQ_TYPE_EDGE_RISING: |
7233593b ZR |
847 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
848 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 | 849 | case IRQ_TYPE_EDGE_FALLING: |
6e99e458 | 850 | case IRQ_TYPE_EDGE_BOTH: |
7233593b ZR |
851 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
852 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 853 | case IRQ_TYPE_LEVEL_HIGH: |
7233593b ZR |
854 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
855 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 BH |
856 | case IRQ_TYPE_LEVEL_LOW: |
857 | default: | |
7233593b ZR |
858 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
859 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 860 | } |
6e99e458 BH |
861 | } |
862 | ||
835c0553 | 863 | int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
6e99e458 | 864 | { |
835c0553 LB |
865 | struct mpic *mpic = mpic_from_irq_data(d); |
866 | unsigned int src = mpic_irq_to_hw(d->irq); | |
6e99e458 BH |
867 | unsigned int vecpri, vold, vnew; |
868 | ||
06fe98e6 | 869 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", |
835c0553 | 870 | mpic, d->irq, src, flow_type); |
6e99e458 BH |
871 | |
872 | if (src >= mpic->irq_count) | |
873 | return -EINVAL; | |
874 | ||
875 | if (flow_type == IRQ_TYPE_NONE) | |
876 | if (mpic->senses && src < mpic->senses_count) | |
877 | flow_type = mpic->senses[src]; | |
878 | if (flow_type == IRQ_TYPE_NONE) | |
879 | flow_type = IRQ_TYPE_LEVEL_LOW; | |
880 | ||
24a3f2e8 | 881 | irqd_set_trigger_type(d, flow_type); |
6e99e458 BH |
882 | |
883 | if (mpic_is_ht_interrupt(mpic, src)) | |
884 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | | |
885 | MPIC_VECPRI_SENSE_EDGE; | |
886 | else | |
7233593b | 887 | vecpri = mpic_type_to_vecpri(mpic, flow_type); |
6e99e458 | 888 | |
7233593b ZR |
889 | vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
890 | vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | | |
891 | MPIC_INFO(VECPRI_SENSE_MASK)); | |
6e99e458 BH |
892 | vnew |= vecpri; |
893 | if (vold != vnew) | |
7233593b | 894 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); |
6e99e458 | 895 | |
24a3f2e8 | 896 | return IRQ_SET_MASK_OK_NOCOPY;; |
0ebfff14 BH |
897 | } |
898 | ||
38958dd9 OJ |
899 | void mpic_set_vector(unsigned int virq, unsigned int vector) |
900 | { | |
901 | struct mpic *mpic = mpic_from_irq(virq); | |
902 | unsigned int src = mpic_irq_to_hw(virq); | |
903 | unsigned int vecpri; | |
904 | ||
905 | DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", | |
906 | mpic, virq, src, vector); | |
907 | ||
908 | if (src >= mpic->irq_count) | |
909 | return; | |
910 | ||
911 | vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); | |
912 | vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); | |
913 | vecpri |= vector; | |
914 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); | |
915 | } | |
916 | ||
dfec2202 MI |
917 | void mpic_set_destination(unsigned int virq, unsigned int cpuid) |
918 | { | |
919 | struct mpic *mpic = mpic_from_irq(virq); | |
920 | unsigned int src = mpic_irq_to_hw(virq); | |
921 | ||
922 | DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", | |
923 | mpic, virq, src, cpuid); | |
924 | ||
925 | if (src >= mpic->irq_count) | |
926 | return; | |
927 | ||
928 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); | |
929 | } | |
930 | ||
b9e5b4e6 | 931 | static struct irq_chip mpic_irq_chip = { |
835c0553 LB |
932 | .irq_mask = mpic_mask_irq, |
933 | .irq_unmask = mpic_unmask_irq, | |
934 | .irq_eoi = mpic_end_irq, | |
935 | .irq_set_type = mpic_set_irq_type, | |
b9e5b4e6 BH |
936 | }; |
937 | ||
938 | #ifdef CONFIG_SMP | |
939 | static struct irq_chip mpic_ipi_chip = { | |
835c0553 LB |
940 | .irq_mask = mpic_mask_ipi, |
941 | .irq_unmask = mpic_unmask_ipi, | |
942 | .irq_eoi = mpic_end_ipi, | |
b9e5b4e6 BH |
943 | }; |
944 | #endif /* CONFIG_SMP */ | |
945 | ||
6cfef5b2 | 946 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 947 | static struct irq_chip mpic_irq_ht_chip = { |
835c0553 LB |
948 | .irq_startup = mpic_startup_ht_irq, |
949 | .irq_shutdown = mpic_shutdown_ht_irq, | |
950 | .irq_mask = mpic_mask_irq, | |
951 | .irq_unmask = mpic_unmask_ht_irq, | |
952 | .irq_eoi = mpic_end_ht_irq, | |
953 | .irq_set_type = mpic_set_irq_type, | |
b9e5b4e6 | 954 | }; |
6cfef5b2 | 955 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
b9e5b4e6 | 956 | |
14cf11af | 957 | |
0ebfff14 BH |
958 | static int mpic_host_match(struct irq_host *h, struct device_node *node) |
959 | { | |
0ebfff14 | 960 | /* Exact match, unless mpic node is NULL */ |
52964f87 | 961 | return h->of_node == NULL || h->of_node == node; |
0ebfff14 BH |
962 | } |
963 | ||
964 | static int mpic_host_map(struct irq_host *h, unsigned int virq, | |
6e99e458 | 965 | irq_hw_number_t hw) |
0ebfff14 | 966 | { |
0ebfff14 | 967 | struct mpic *mpic = h->host_data; |
6e99e458 | 968 | struct irq_chip *chip; |
0ebfff14 | 969 | |
06fe98e6 | 970 | DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); |
0ebfff14 | 971 | |
7df2457d | 972 | if (hw == mpic->spurious_vec) |
0ebfff14 | 973 | return -EINVAL; |
7fd72186 BH |
974 | if (mpic->protected && test_bit(hw, mpic->protected)) |
975 | return -EINVAL; | |
06fe98e6 | 976 | |
0ebfff14 | 977 | #ifdef CONFIG_SMP |
7df2457d | 978 | else if (hw >= mpic->ipi_vecs[0]) { |
0ebfff14 BH |
979 | WARN_ON(!(mpic->flags & MPIC_PRIMARY)); |
980 | ||
06fe98e6 | 981 | DBG("mpic: mapping as IPI\n"); |
ec775d0e TG |
982 | irq_set_chip_data(virq, mpic); |
983 | irq_set_chip_and_handler(virq, &mpic->hc_ipi, | |
0ebfff14 BH |
984 | handle_percpu_irq); |
985 | return 0; | |
986 | } | |
987 | #endif /* CONFIG_SMP */ | |
988 | ||
989 | if (hw >= mpic->irq_count) | |
990 | return -EINVAL; | |
991 | ||
a7de7c74 ME |
992 | mpic_msi_reserve_hwirq(mpic, hw); |
993 | ||
6e99e458 | 994 | /* Default chip */ |
0ebfff14 BH |
995 | chip = &mpic->hc_irq; |
996 | ||
6cfef5b2 | 997 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
0ebfff14 | 998 | /* Check for HT interrupts, override vecpri */ |
6e99e458 | 999 | if (mpic_is_ht_interrupt(mpic, hw)) |
0ebfff14 | 1000 | chip = &mpic->hc_ht_irq; |
6cfef5b2 | 1001 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
0ebfff14 | 1002 | |
06fe98e6 | 1003 | DBG("mpic: mapping to irq chip @%p\n", chip); |
0ebfff14 | 1004 | |
ec775d0e TG |
1005 | irq_set_chip_data(virq, mpic); |
1006 | irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); | |
6e99e458 BH |
1007 | |
1008 | /* Set default irq type */ | |
ec775d0e | 1009 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
6e99e458 | 1010 | |
dfec2202 MI |
1011 | /* If the MPIC was reset, then all vectors have already been |
1012 | * initialized. Otherwise, a per source lazy initialization | |
1013 | * is done here. | |
1014 | */ | |
1015 | if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { | |
dfec2202 | 1016 | mpic_set_vector(virq, hw); |
d6a2639b | 1017 | mpic_set_destination(virq, mpic_processor_id(mpic)); |
dfec2202 MI |
1018 | mpic_irq_set_priority(virq, 8); |
1019 | } | |
1020 | ||
0ebfff14 BH |
1021 | return 0; |
1022 | } | |
1023 | ||
1024 | static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, | |
40d50cf7 | 1025 | const u32 *intspec, unsigned int intsize, |
0ebfff14 BH |
1026 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
1027 | ||
1028 | { | |
1029 | static unsigned char map_mpic_senses[4] = { | |
1030 | IRQ_TYPE_EDGE_RISING, | |
1031 | IRQ_TYPE_LEVEL_LOW, | |
1032 | IRQ_TYPE_LEVEL_HIGH, | |
1033 | IRQ_TYPE_EDGE_FALLING, | |
1034 | }; | |
1035 | ||
1036 | *out_hwirq = intspec[0]; | |
06fe98e6 BH |
1037 | if (intsize > 1) { |
1038 | u32 mask = 0x3; | |
1039 | ||
1040 | /* Apple invented a new race of encoding on machines with | |
1041 | * an HT APIC. They encode, among others, the index within | |
1042 | * the HT APIC. We don't care about it here since thankfully, | |
1043 | * it appears that they have the APIC already properly | |
1044 | * configured, and thus our current fixup code that reads the | |
1045 | * APIC config works fine. However, we still need to mask out | |
1046 | * bits in the specifier to make sure we only get bit 0 which | |
1047 | * is the level/edge bit (the only sense bit exposed by Apple), | |
1048 | * as their bit 1 means something else. | |
1049 | */ | |
1050 | if (machine_is(powermac)) | |
1051 | mask = 0x1; | |
1052 | *out_flags = map_mpic_senses[intspec[1] & mask]; | |
1053 | } else | |
0ebfff14 BH |
1054 | *out_flags = IRQ_TYPE_NONE; |
1055 | ||
06fe98e6 BH |
1056 | DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", |
1057 | intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); | |
1058 | ||
0ebfff14 BH |
1059 | return 0; |
1060 | } | |
1061 | ||
1062 | static struct irq_host_ops mpic_host_ops = { | |
1063 | .match = mpic_host_match, | |
1064 | .map = mpic_host_map, | |
1065 | .xlate = mpic_host_xlate, | |
1066 | }; | |
1067 | ||
dfec2202 MI |
1068 | static int mpic_reset_prohibited(struct device_node *node) |
1069 | { | |
1070 | return node && of_get_property(node, "pic-no-reset", NULL); | |
1071 | } | |
1072 | ||
14cf11af PM |
1073 | /* |
1074 | * Exported functions | |
1075 | */ | |
1076 | ||
0ebfff14 | 1077 | struct mpic * __init mpic_alloc(struct device_node *node, |
a959ff56 | 1078 | phys_addr_t phys_addr, |
14cf11af PM |
1079 | unsigned int flags, |
1080 | unsigned int isu_size, | |
14cf11af | 1081 | unsigned int irq_count, |
14cf11af PM |
1082 | const char *name) |
1083 | { | |
1084 | struct mpic *mpic; | |
d9d1063d | 1085 | u32 greg_feature; |
14cf11af PM |
1086 | const char *vers; |
1087 | int i; | |
7df2457d | 1088 | int intvec_top; |
a959ff56 | 1089 | u64 paddr = phys_addr; |
14cf11af | 1090 | |
85355bb2 | 1091 | mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); |
14cf11af PM |
1092 | if (mpic == NULL) |
1093 | return NULL; | |
85355bb2 | 1094 | |
14cf11af PM |
1095 | mpic->name = name; |
1096 | ||
b9e5b4e6 | 1097 | mpic->hc_irq = mpic_irq_chip; |
b27df672 | 1098 | mpic->hc_irq.name = name; |
14cf11af | 1099 | if (flags & MPIC_PRIMARY) |
835c0553 | 1100 | mpic->hc_irq.irq_set_affinity = mpic_set_affinity; |
6cfef5b2 | 1101 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 1102 | mpic->hc_ht_irq = mpic_irq_ht_chip; |
b27df672 | 1103 | mpic->hc_ht_irq.name = name; |
b9e5b4e6 | 1104 | if (flags & MPIC_PRIMARY) |
835c0553 | 1105 | mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; |
6cfef5b2 | 1106 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
fbf0274e | 1107 | |
14cf11af | 1108 | #ifdef CONFIG_SMP |
b9e5b4e6 | 1109 | mpic->hc_ipi = mpic_ipi_chip; |
b27df672 | 1110 | mpic->hc_ipi.name = name; |
14cf11af PM |
1111 | #endif /* CONFIG_SMP */ |
1112 | ||
1113 | mpic->flags = flags; | |
1114 | mpic->isu_size = isu_size; | |
14cf11af | 1115 | mpic->irq_count = irq_count; |
14cf11af | 1116 | mpic->num_sources = 0; /* so far */ |
14cf11af | 1117 | |
7df2457d OJ |
1118 | if (flags & MPIC_LARGE_VECTORS) |
1119 | intvec_top = 2047; | |
1120 | else | |
1121 | intvec_top = 255; | |
1122 | ||
1123 | mpic->timer_vecs[0] = intvec_top - 8; | |
1124 | mpic->timer_vecs[1] = intvec_top - 7; | |
1125 | mpic->timer_vecs[2] = intvec_top - 6; | |
1126 | mpic->timer_vecs[3] = intvec_top - 5; | |
1127 | mpic->ipi_vecs[0] = intvec_top - 4; | |
1128 | mpic->ipi_vecs[1] = intvec_top - 3; | |
1129 | mpic->ipi_vecs[2] = intvec_top - 2; | |
1130 | mpic->ipi_vecs[3] = intvec_top - 1; | |
1131 | mpic->spurious_vec = intvec_top; | |
1132 | ||
a959ff56 | 1133 | /* Check for "big-endian" in device-tree */ |
e2eb6392 | 1134 | if (node && of_get_property(node, "big-endian", NULL) != NULL) |
a959ff56 BH |
1135 | mpic->flags |= MPIC_BIG_ENDIAN; |
1136 | ||
7fd72186 BH |
1137 | /* Look for protected sources */ |
1138 | if (node) { | |
d9d1063d JB |
1139 | int psize; |
1140 | unsigned int bits, mapsize; | |
7fd72186 BH |
1141 | const u32 *psrc = |
1142 | of_get_property(node, "protected-sources", &psize); | |
1143 | if (psrc) { | |
1144 | psize /= 4; | |
1145 | bits = intvec_top + 1; | |
1146 | mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long); | |
ea96025a | 1147 | mpic->protected = kzalloc(mapsize, GFP_KERNEL); |
7fd72186 | 1148 | BUG_ON(mpic->protected == NULL); |
7fd72186 BH |
1149 | for (i = 0; i < psize; i++) { |
1150 | if (psrc[i] > intvec_top) | |
1151 | continue; | |
1152 | __set_bit(psrc[i], mpic->protected); | |
1153 | } | |
1154 | } | |
1155 | } | |
a959ff56 | 1156 | |
7233593b ZR |
1157 | #ifdef CONFIG_MPIC_WEIRD |
1158 | mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; | |
1159 | #endif | |
1160 | ||
fbf0274e BH |
1161 | /* default register type */ |
1162 | mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? | |
1163 | mpic_access_mmio_be : mpic_access_mmio_le; | |
1164 | ||
a959ff56 BH |
1165 | /* If no physical address is passed in, a device-node is mandatory */ |
1166 | BUG_ON(paddr == 0 && node == NULL); | |
1167 | ||
1168 | /* If no physical address passed in, check if it's dcr based */ | |
0411a5e2 | 1169 | if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) { |
fbf0274e | 1170 | #ifdef CONFIG_PPC_DCR |
0411a5e2 | 1171 | mpic->flags |= MPIC_USES_DCR; |
fbf0274e | 1172 | mpic->reg_type = mpic_access_dcr; |
fbf0274e | 1173 | #else |
0411a5e2 | 1174 | BUG(); |
fbf0274e | 1175 | #endif /* CONFIG_PPC_DCR */ |
0411a5e2 | 1176 | } |
fbf0274e | 1177 | |
a959ff56 BH |
1178 | /* If the MPIC is not DCR based, and no physical address was passed |
1179 | * in, try to obtain one | |
1180 | */ | |
1181 | if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { | |
d9d1063d | 1182 | const u32 *reg = of_get_property(node, "reg", NULL); |
a959ff56 BH |
1183 | BUG_ON(reg == NULL); |
1184 | paddr = of_translate_address(node, reg); | |
1185 | BUG_ON(paddr == OF_BAD_ADDR); | |
1186 | } | |
1187 | ||
14cf11af | 1188 | /* Map the global registers */ |
5a2642f6 BH |
1189 | mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); |
1190 | mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); | |
14cf11af PM |
1191 | |
1192 | /* Reset */ | |
dfec2202 MI |
1193 | |
1194 | /* When using a device-node, reset requests are only honored if the MPIC | |
1195 | * is allowed to reset. | |
1196 | */ | |
1197 | if (mpic_reset_prohibited(node)) | |
1198 | mpic->flags |= MPIC_NO_RESET; | |
1199 | ||
1200 | if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) { | |
1201 | printk(KERN_DEBUG "mpic: Resetting\n"); | |
7233593b ZR |
1202 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
1203 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
14cf11af | 1204 | | MPIC_GREG_GCONF_RESET); |
7233593b | 1205 | while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
14cf11af PM |
1206 | & MPIC_GREG_GCONF_RESET) |
1207 | mb(); | |
1208 | } | |
1209 | ||
d91e4ea7 KG |
1210 | /* CoreInt */ |
1211 | if (flags & MPIC_ENABLE_COREINT) | |
1212 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1213 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1214 | | MPIC_GREG_GCONF_COREINT); | |
1215 | ||
f365355e OJ |
1216 | if (flags & MPIC_ENABLE_MCK) |
1217 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1218 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1219 | | MPIC_GREG_GCONF_MCK); | |
1220 | ||
14cf11af PM |
1221 | /* Read feature register, calculate num CPUs and, for non-ISU |
1222 | * MPICs, num sources as well. On ISU MPICs, sources are counted | |
1223 | * as ISUs are added | |
1224 | */ | |
d9d1063d JB |
1225 | greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); |
1226 | mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK) | |
14cf11af | 1227 | >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; |
5073e7ee | 1228 | if (isu_size == 0) { |
475ca391 KG |
1229 | if (flags & MPIC_BROKEN_FRR_NIRQS) |
1230 | mpic->num_sources = mpic->irq_count; | |
1231 | else | |
1232 | mpic->num_sources = | |
1233 | ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) | |
1234 | >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; | |
5073e7ee | 1235 | } |
14cf11af PM |
1236 | |
1237 | /* Map the per-CPU registers */ | |
1238 | for (i = 0; i < mpic->num_cpus; i++) { | |
5a2642f6 | 1239 | mpic_map(mpic, node, paddr, &mpic->cpuregs[i], |
fbf0274e BH |
1240 | MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), |
1241 | 0x1000); | |
14cf11af PM |
1242 | } |
1243 | ||
1244 | /* Initialize main ISU if none provided */ | |
1245 | if (mpic->isu_size == 0) { | |
1246 | mpic->isu_size = mpic->num_sources; | |
5a2642f6 | 1247 | mpic_map(mpic, node, paddr, &mpic->isus[0], |
fbf0274e | 1248 | MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
14cf11af PM |
1249 | } |
1250 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); | |
1251 | mpic->isu_mask = (1 << mpic->isu_shift) - 1; | |
1252 | ||
31207dab KG |
1253 | mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, |
1254 | isu_size ? isu_size : mpic->num_sources, | |
1255 | &mpic_host_ops, | |
1256 | flags & MPIC_LARGE_VECTORS ? 2048 : 256); | |
1257 | if (mpic->irqhost == NULL) | |
1258 | return NULL; | |
1259 | ||
1260 | mpic->irqhost->host_data = mpic; | |
1261 | ||
14cf11af | 1262 | /* Display version */ |
d9d1063d | 1263 | switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { |
14cf11af PM |
1264 | case 1: |
1265 | vers = "1.0"; | |
1266 | break; | |
1267 | case 2: | |
1268 | vers = "1.2"; | |
1269 | break; | |
1270 | case 3: | |
1271 | vers = "1.3"; | |
1272 | break; | |
1273 | default: | |
1274 | vers = "<unknown>"; | |
1275 | break; | |
1276 | } | |
a959ff56 BH |
1277 | printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," |
1278 | " max %d CPUs\n", | |
1279 | name, vers, (unsigned long long)paddr, mpic->num_cpus); | |
1280 | printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", | |
1281 | mpic->isu_size, mpic->isu_shift, mpic->isu_mask); | |
14cf11af PM |
1282 | |
1283 | mpic->next = mpics; | |
1284 | mpics = mpic; | |
1285 | ||
0ebfff14 | 1286 | if (flags & MPIC_PRIMARY) { |
14cf11af | 1287 | mpic_primary = mpic; |
0ebfff14 BH |
1288 | irq_set_default_host(mpic->irqhost); |
1289 | } | |
14cf11af PM |
1290 | |
1291 | return mpic; | |
1292 | } | |
1293 | ||
1294 | void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, | |
a959ff56 | 1295 | phys_addr_t paddr) |
14cf11af PM |
1296 | { |
1297 | unsigned int isu_first = isu_num * mpic->isu_size; | |
1298 | ||
1299 | BUG_ON(isu_num >= MPIC_MAX_ISU); | |
1300 | ||
5a2642f6 BH |
1301 | mpic_map(mpic, mpic->irqhost->of_node, |
1302 | paddr, &mpic->isus[isu_num], 0, | |
fbf0274e | 1303 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
5a2642f6 | 1304 | |
14cf11af PM |
1305 | if ((isu_first + mpic->isu_size) > mpic->num_sources) |
1306 | mpic->num_sources = isu_first + mpic->isu_size; | |
1307 | } | |
1308 | ||
0ebfff14 BH |
1309 | void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) |
1310 | { | |
1311 | mpic->senses = senses; | |
1312 | mpic->senses_count = count; | |
1313 | } | |
1314 | ||
14cf11af PM |
1315 | void __init mpic_init(struct mpic *mpic) |
1316 | { | |
1317 | int i; | |
cc353c30 | 1318 | int cpu; |
14cf11af PM |
1319 | |
1320 | BUG_ON(mpic->num_sources == 0); | |
1321 | ||
1322 | printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); | |
1323 | ||
1324 | /* Set current processor priority to max */ | |
7233593b | 1325 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
14cf11af PM |
1326 | |
1327 | /* Initialize timers: just disable them all */ | |
1328 | for (i = 0; i < 4; i++) { | |
1329 | mpic_write(mpic->tmregs, | |
7233593b ZR |
1330 | i * MPIC_INFO(TIMER_STRIDE) + |
1331 | MPIC_INFO(TIMER_DESTINATION), 0); | |
14cf11af | 1332 | mpic_write(mpic->tmregs, |
7233593b ZR |
1333 | i * MPIC_INFO(TIMER_STRIDE) + |
1334 | MPIC_INFO(TIMER_VECTOR_PRI), | |
14cf11af | 1335 | MPIC_VECPRI_MASK | |
7df2457d | 1336 | (mpic->timer_vecs[0] + i)); |
14cf11af PM |
1337 | } |
1338 | ||
1339 | /* Initialize IPIs to our reserved vectors and mark them disabled for now */ | |
1340 | mpic_test_broken_ipi(mpic); | |
1341 | for (i = 0; i < 4; i++) { | |
1342 | mpic_ipi_write(i, | |
1343 | MPIC_VECPRI_MASK | | |
1344 | (10 << MPIC_VECPRI_PRIORITY_SHIFT) | | |
7df2457d | 1345 | (mpic->ipi_vecs[0] + i)); |
14cf11af PM |
1346 | } |
1347 | ||
1348 | /* Initialize interrupt sources */ | |
1349 | if (mpic->irq_count == 0) | |
1350 | mpic->irq_count = mpic->num_sources; | |
1351 | ||
1beb6a7d | 1352 | /* Do the HT PIC fixups on U3 broken mpic */ |
14cf11af | 1353 | DBG("MPIC flags: %x\n", mpic->flags); |
05af7bd2 | 1354 | if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) { |
3669e930 | 1355 | mpic_scan_ht_pics(mpic); |
05af7bd2 ME |
1356 | mpic_u3msi_init(mpic); |
1357 | } | |
14cf11af | 1358 | |
38958dd9 OJ |
1359 | mpic_pasemi_msi_init(mpic); |
1360 | ||
d6a2639b | 1361 | cpu = mpic_processor_id(mpic); |
cc353c30 | 1362 | |
dfec2202 MI |
1363 | if (!(mpic->flags & MPIC_NO_RESET)) { |
1364 | for (i = 0; i < mpic->num_sources; i++) { | |
1365 | /* start with vector = source number, and masked */ | |
1366 | u32 vecpri = MPIC_VECPRI_MASK | i | | |
1367 | (8 << MPIC_VECPRI_PRIORITY_SHIFT); | |
14cf11af | 1368 | |
dfec2202 MI |
1369 | /* check if protected */ |
1370 | if (mpic->protected && test_bit(i, mpic->protected)) | |
1371 | continue; | |
1372 | /* init hw */ | |
1373 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); | |
1374 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); | |
1375 | } | |
14cf11af PM |
1376 | } |
1377 | ||
7df2457d OJ |
1378 | /* Init spurious vector */ |
1379 | mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); | |
14cf11af | 1380 | |
7233593b ZR |
1381 | /* Disable 8259 passthrough, if supported */ |
1382 | if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) | |
1383 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1384 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1385 | | MPIC_GREG_GCONF_8259_PTHROU_DIS); | |
14cf11af | 1386 | |
d87bf3be OJ |
1387 | if (mpic->flags & MPIC_NO_BIAS) |
1388 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1389 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1390 | | MPIC_GREG_GCONF_NO_BIAS); | |
1391 | ||
14cf11af | 1392 | /* Set current processor priority to 0 */ |
7233593b | 1393 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
3669e930 JB |
1394 | |
1395 | #ifdef CONFIG_PM | |
1396 | /* allocate memory to save mpic state */ | |
ea96025a AV |
1397 | mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data), |
1398 | GFP_KERNEL); | |
3669e930 JB |
1399 | BUG_ON(mpic->save_data == NULL); |
1400 | #endif | |
14cf11af PM |
1401 | } |
1402 | ||
868ea0c9 MG |
1403 | void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) |
1404 | { | |
1405 | u32 v; | |
1406 | ||
1407 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); | |
1408 | v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; | |
1409 | v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); | |
1410 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); | |
1411 | } | |
14cf11af | 1412 | |
868ea0c9 MG |
1413 | void __init mpic_set_serial_int(struct mpic *mpic, int enable) |
1414 | { | |
ba1826e5 | 1415 | unsigned long flags; |
868ea0c9 MG |
1416 | u32 v; |
1417 | ||
203041ad | 1418 | raw_spin_lock_irqsave(&mpic_lock, flags); |
868ea0c9 MG |
1419 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); |
1420 | if (enable) | |
1421 | v |= MPIC_GREG_GLOBAL_CONF_1_SIE; | |
1422 | else | |
1423 | v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; | |
1424 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); | |
203041ad | 1425 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
868ea0c9 | 1426 | } |
14cf11af PM |
1427 | |
1428 | void mpic_irq_set_priority(unsigned int irq, unsigned int pri) | |
1429 | { | |
d69a78d7 | 1430 | struct mpic *mpic = mpic_find(irq); |
0ebfff14 | 1431 | unsigned int src = mpic_irq_to_hw(irq); |
14cf11af PM |
1432 | unsigned long flags; |
1433 | u32 reg; | |
1434 | ||
06a901c5 SR |
1435 | if (!mpic) |
1436 | return; | |
1437 | ||
203041ad | 1438 | raw_spin_lock_irqsave(&mpic_lock, flags); |
d69a78d7 | 1439 | if (mpic_is_ipi(mpic, irq)) { |
7df2457d | 1440 | reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & |
e5356640 | 1441 | ~MPIC_VECPRI_PRIORITY_MASK; |
7df2457d | 1442 | mpic_ipi_write(src - mpic->ipi_vecs[0], |
14cf11af PM |
1443 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
1444 | } else { | |
7233593b | 1445 | reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
e5356640 | 1446 | & ~MPIC_VECPRI_PRIORITY_MASK; |
7233593b | 1447 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
14cf11af PM |
1448 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
1449 | } | |
203041ad | 1450 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1451 | } |
1452 | ||
14cf11af PM |
1453 | void mpic_setup_this_cpu(void) |
1454 | { | |
1455 | #ifdef CONFIG_SMP | |
1456 | struct mpic *mpic = mpic_primary; | |
1457 | unsigned long flags; | |
1458 | u32 msk = 1 << hard_smp_processor_id(); | |
1459 | unsigned int i; | |
1460 | ||
1461 | BUG_ON(mpic == NULL); | |
1462 | ||
1463 | DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
1464 | ||
203041ad | 1465 | raw_spin_lock_irqsave(&mpic_lock, flags); |
14cf11af PM |
1466 | |
1467 | /* let the mpic know we want intrs. default affinity is 0xffffffff | |
1468 | * until changed via /proc. That's how it's done on x86. If we want | |
1469 | * it differently, then we should make sure we also change the default | |
a53da52f | 1470 | * values of irq_desc[].affinity in irq.c. |
14cf11af PM |
1471 | */ |
1472 | if (distribute_irqs) { | |
1473 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1474 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1475 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); | |
14cf11af PM |
1476 | } |
1477 | ||
1478 | /* Set current processor priority to 0 */ | |
7233593b | 1479 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
14cf11af | 1480 | |
203041ad | 1481 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1482 | #endif /* CONFIG_SMP */ |
1483 | } | |
1484 | ||
1485 | int mpic_cpu_get_priority(void) | |
1486 | { | |
1487 | struct mpic *mpic = mpic_primary; | |
1488 | ||
7233593b | 1489 | return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); |
14cf11af PM |
1490 | } |
1491 | ||
1492 | void mpic_cpu_set_priority(int prio) | |
1493 | { | |
1494 | struct mpic *mpic = mpic_primary; | |
1495 | ||
1496 | prio &= MPIC_CPU_TASKPRI_MASK; | |
7233593b | 1497 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); |
14cf11af PM |
1498 | } |
1499 | ||
14cf11af PM |
1500 | void mpic_teardown_this_cpu(int secondary) |
1501 | { | |
1502 | struct mpic *mpic = mpic_primary; | |
1503 | unsigned long flags; | |
1504 | u32 msk = 1 << hard_smp_processor_id(); | |
1505 | unsigned int i; | |
1506 | ||
1507 | BUG_ON(mpic == NULL); | |
1508 | ||
1509 | DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
203041ad | 1510 | raw_spin_lock_irqsave(&mpic_lock, flags); |
14cf11af PM |
1511 | |
1512 | /* let the mpic know we don't want intrs. */ | |
1513 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1514 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1515 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); | |
14cf11af PM |
1516 | |
1517 | /* Set current processor priority to max */ | |
7233593b | 1518 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
7132799b VB |
1519 | /* We need to EOI the IPI since not all platforms reset the MPIC |
1520 | * on boot and new interrupts wouldn't get delivered otherwise. | |
1521 | */ | |
1522 | mpic_eoi(mpic); | |
14cf11af | 1523 | |
203041ad | 1524 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1525 | } |
1526 | ||
1527 | ||
f365355e | 1528 | static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) |
14cf11af | 1529 | { |
0ebfff14 | 1530 | u32 src; |
14cf11af | 1531 | |
f365355e | 1532 | src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); |
1beb6a7d | 1533 | #ifdef DEBUG_LOW |
f365355e | 1534 | DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); |
1beb6a7d | 1535 | #endif |
5cddd2e3 JB |
1536 | if (unlikely(src == mpic->spurious_vec)) { |
1537 | if (mpic->flags & MPIC_SPV_EOI) | |
1538 | mpic_eoi(mpic); | |
0ebfff14 | 1539 | return NO_IRQ; |
5cddd2e3 | 1540 | } |
7fd72186 BH |
1541 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { |
1542 | if (printk_ratelimit()) | |
1543 | printk(KERN_WARNING "%s: Got protected source %d !\n", | |
1544 | mpic->name, (int)src); | |
1545 | mpic_eoi(mpic); | |
1546 | return NO_IRQ; | |
1547 | } | |
1548 | ||
0ebfff14 | 1549 | return irq_linear_revmap(mpic->irqhost, src); |
14cf11af PM |
1550 | } |
1551 | ||
f365355e OJ |
1552 | unsigned int mpic_get_one_irq(struct mpic *mpic) |
1553 | { | |
1554 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); | |
1555 | } | |
1556 | ||
35a84c2f | 1557 | unsigned int mpic_get_irq(void) |
14cf11af PM |
1558 | { |
1559 | struct mpic *mpic = mpic_primary; | |
1560 | ||
1561 | BUG_ON(mpic == NULL); | |
1562 | ||
35a84c2f | 1563 | return mpic_get_one_irq(mpic); |
14cf11af PM |
1564 | } |
1565 | ||
d91e4ea7 KG |
1566 | unsigned int mpic_get_coreint_irq(void) |
1567 | { | |
1568 | #ifdef CONFIG_BOOKE | |
1569 | struct mpic *mpic = mpic_primary; | |
1570 | u32 src; | |
1571 | ||
1572 | BUG_ON(mpic == NULL); | |
1573 | ||
1574 | src = mfspr(SPRN_EPR); | |
1575 | ||
1576 | if (unlikely(src == mpic->spurious_vec)) { | |
1577 | if (mpic->flags & MPIC_SPV_EOI) | |
1578 | mpic_eoi(mpic); | |
1579 | return NO_IRQ; | |
1580 | } | |
1581 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { | |
1582 | if (printk_ratelimit()) | |
1583 | printk(KERN_WARNING "%s: Got protected source %d !\n", | |
1584 | mpic->name, (int)src); | |
1585 | return NO_IRQ; | |
1586 | } | |
1587 | ||
1588 | return irq_linear_revmap(mpic->irqhost, src); | |
1589 | #else | |
1590 | return NO_IRQ; | |
1591 | #endif | |
1592 | } | |
1593 | ||
f365355e OJ |
1594 | unsigned int mpic_get_mcirq(void) |
1595 | { | |
1596 | struct mpic *mpic = mpic_primary; | |
1597 | ||
1598 | BUG_ON(mpic == NULL); | |
1599 | ||
1600 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); | |
1601 | } | |
14cf11af PM |
1602 | |
1603 | #ifdef CONFIG_SMP | |
1604 | void mpic_request_ipis(void) | |
1605 | { | |
1606 | struct mpic *mpic = mpic_primary; | |
78608dd3 | 1607 | int i; |
14cf11af | 1608 | BUG_ON(mpic == NULL); |
14cf11af | 1609 | |
8354be9c | 1610 | printk(KERN_INFO "mpic: requesting IPIs...\n"); |
0ebfff14 BH |
1611 | |
1612 | for (i = 0; i < 4; i++) { | |
1613 | unsigned int vipi = irq_create_mapping(mpic->irqhost, | |
7df2457d | 1614 | mpic->ipi_vecs[0] + i); |
0ebfff14 | 1615 | if (vipi == NO_IRQ) { |
78608dd3 MM |
1616 | printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); |
1617 | continue; | |
d16f1b64 | 1618 | } |
78608dd3 | 1619 | smp_request_message_ipi(vipi, i); |
0ebfff14 | 1620 | } |
14cf11af | 1621 | } |
a9c59264 | 1622 | |
2ef613cb BH |
1623 | static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask) |
1624 | { | |
1625 | struct mpic *mpic = mpic_primary; | |
1626 | ||
1627 | BUG_ON(mpic == NULL); | |
1628 | ||
1629 | #ifdef DEBUG_IPI | |
1630 | DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); | |
1631 | #endif | |
1632 | ||
1633 | mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + | |
1634 | ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), | |
1635 | mpic_physmask(cpumask_bits(cpu_mask)[0])); | |
1636 | } | |
1637 | ||
a9c59264 PM |
1638 | void smp_mpic_message_pass(int target, int msg) |
1639 | { | |
2ef613cb BH |
1640 | cpumask_var_t tmp; |
1641 | ||
a9c59264 PM |
1642 | /* make sure we're sending something that translates to an IPI */ |
1643 | if ((unsigned int)msg > 3) { | |
1644 | printk("SMP %d: smp_message_pass: unknown msg %d\n", | |
1645 | smp_processor_id(), msg); | |
1646 | return; | |
1647 | } | |
1648 | switch (target) { | |
1649 | case MSG_ALL: | |
2ef613cb | 1650 | mpic_send_ipi(msg, cpu_online_mask); |
a9c59264 PM |
1651 | break; |
1652 | case MSG_ALL_BUT_SELF: | |
2ef613cb BH |
1653 | alloc_cpumask_var(&tmp, GFP_NOWAIT); |
1654 | cpumask_andnot(tmp, cpu_online_mask, | |
1655 | cpumask_of(smp_processor_id())); | |
1656 | mpic_send_ipi(msg, tmp); | |
1657 | free_cpumask_var(tmp); | |
a9c59264 PM |
1658 | break; |
1659 | default: | |
2ef613cb | 1660 | mpic_send_ipi(msg, cpumask_of(target)); |
a9c59264 PM |
1661 | break; |
1662 | } | |
1663 | } | |
775aeff4 ME |
1664 | |
1665 | int __init smp_mpic_probe(void) | |
1666 | { | |
1667 | int nr_cpus; | |
1668 | ||
1669 | DBG("smp_mpic_probe()...\n"); | |
1670 | ||
2ef613cb | 1671 | nr_cpus = cpumask_weight(cpu_possible_mask); |
775aeff4 ME |
1672 | |
1673 | DBG("nr_cpus: %d\n", nr_cpus); | |
1674 | ||
1675 | if (nr_cpus > 1) | |
1676 | mpic_request_ipis(); | |
1677 | ||
1678 | return nr_cpus; | |
1679 | } | |
1680 | ||
1681 | void __devinit smp_mpic_setup_cpu(int cpu) | |
1682 | { | |
1683 | mpic_setup_this_cpu(); | |
1684 | } | |
66953ebe MM |
1685 | |
1686 | void mpic_reset_core(int cpu) | |
1687 | { | |
1688 | struct mpic *mpic = mpic_primary; | |
1689 | u32 pir; | |
1690 | int cpuid = get_hard_smp_processor_id(cpu); | |
1691 | ||
1692 | /* Set target bit for core reset */ | |
1693 | pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1694 | pir |= (1 << cpuid); | |
1695 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); | |
1696 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1697 | ||
1698 | /* Restore target bit after reset complete */ | |
1699 | pir &= ~(1 << cpuid); | |
1700 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); | |
1701 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1702 | } | |
14cf11af | 1703 | #endif /* CONFIG_SMP */ |
3669e930 JB |
1704 | |
1705 | #ifdef CONFIG_PM | |
f5a592f7 | 1706 | static void mpic_suspend_one(struct mpic *mpic) |
3669e930 | 1707 | { |
3669e930 JB |
1708 | int i; |
1709 | ||
1710 | for (i = 0; i < mpic->num_sources; i++) { | |
1711 | mpic->save_data[i].vecprio = | |
1712 | mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); | |
1713 | mpic->save_data[i].dest = | |
1714 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); | |
1715 | } | |
f5a592f7 RW |
1716 | } |
1717 | ||
1718 | static int mpic_suspend(void) | |
1719 | { | |
1720 | struct mpic *mpic = mpics; | |
1721 | ||
1722 | while (mpic) { | |
1723 | mpic_suspend_one(mpic); | |
1724 | mpic = mpic->next; | |
1725 | } | |
3669e930 JB |
1726 | |
1727 | return 0; | |
1728 | } | |
1729 | ||
f5a592f7 | 1730 | static void mpic_resume_one(struct mpic *mpic) |
3669e930 | 1731 | { |
3669e930 JB |
1732 | int i; |
1733 | ||
1734 | for (i = 0; i < mpic->num_sources; i++) { | |
1735 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), | |
1736 | mpic->save_data[i].vecprio); | |
1737 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), | |
1738 | mpic->save_data[i].dest); | |
1739 | ||
1740 | #ifdef CONFIG_MPIC_U3_HT_IRQS | |
7c9d9360 | 1741 | if (mpic->fixups) { |
3669e930 JB |
1742 | struct mpic_irq_fixup *fixup = &mpic->fixups[i]; |
1743 | ||
1744 | if (fixup->base) { | |
1745 | /* we use the lowest bit in an inverted meaning */ | |
1746 | if ((mpic->save_data[i].fixup_data & 1) == 0) | |
1747 | continue; | |
1748 | ||
1749 | /* Enable and configure */ | |
1750 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
1751 | ||
1752 | writel(mpic->save_data[i].fixup_data & ~1, | |
1753 | fixup->base + 4); | |
1754 | } | |
1755 | } | |
1756 | #endif | |
1757 | } /* end for loop */ | |
f5a592f7 | 1758 | } |
3669e930 | 1759 | |
f5a592f7 RW |
1760 | static void mpic_resume(void) |
1761 | { | |
1762 | struct mpic *mpic = mpics; | |
1763 | ||
1764 | while (mpic) { | |
1765 | mpic_resume_one(mpic); | |
1766 | mpic = mpic->next; | |
1767 | } | |
3669e930 | 1768 | } |
3669e930 | 1769 | |
f5a592f7 | 1770 | static struct syscore_ops mpic_syscore_ops = { |
3669e930 JB |
1771 | .resume = mpic_resume, |
1772 | .suspend = mpic_suspend, | |
3669e930 JB |
1773 | }; |
1774 | ||
1775 | static int mpic_init_sys(void) | |
1776 | { | |
f5a592f7 RW |
1777 | register_syscore_ops(&mpic_syscore_ops); |
1778 | return 0; | |
3669e930 JB |
1779 | } |
1780 | ||
1781 | device_initcall(mpic_init_sys); | |
f5a592f7 | 1782 | #endif |