[deliverable/linux.git] / arch / powerpc / sysdev / mv64x60_pci.c

/*
 * PCI bus setup for Marvell mv64360/mv64460 host bridges (Discovery)
 *
 * Author: Dale Farnsworth <dale@farnsworth.org>
 *
 * 2007 (c) MontaVista, Software, Inc.  This file is licensed under
 * the terms of the GNU General Public License version 2.  This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>

#include <asm/prom.h>
#include <asm/pci-bridge.h>

#define PCI_HEADER_TYPE_INVALID		0x7f	/* Invalid PCI header type */

#ifdef CONFIG_SYSFS
/* 32-bit hex or dec stringified number + '\n' */
#define MV64X60_VAL_LEN_MAX		11
#define MV64X60_PCICFG_CPCI_HOTSWAP	0x68

static ssize_t mv64x60_hs_reg_read(struct file *filp, struct kobject *kobj,
				   struct bin_attribute *attr, char *buf,
				   loff_t off, size_t count)
{
	struct pci_dev *phb;
	u32 v;

	if (off > 0)
		return 0;
	if (count < MV64X60_VAL_LEN_MAX)
		return -EINVAL;

	phb = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
	if (!phb)
		return -ENODEV;
	pci_read_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, &v);
	pci_dev_put(phb);

	return sprintf(buf, "0x%08x\n", v);
}

static ssize_t mv64x60_hs_reg_write(struct file *filp, struct kobject *kobj,
				    struct bin_attribute *attr, char *buf,
				    loff_t off, size_t count)
{
	struct pci_dev *phb;
	u32 v;

	if (off > 0)
		return 0;
	if (count <= 0)
		return -EINVAL;

	if (sscanf(buf, "%i", &v) != 1)
		return -EINVAL;

	phb = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
	if (!phb)
		return -ENODEV;
	pci_write_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, v);
	pci_dev_put(phb);

	return count;
}

static struct bin_attribute mv64x60_hs_reg_attr = { /* Hotswap register */
	.attr = {
		.name = "hs_reg",
		.mode = S_IRUGO | S_IWUSR,
	},
	.size  = MV64X60_VAL_LEN_MAX,
	.read  = mv64x60_hs_reg_read,
	.write = mv64x60_hs_reg_write,
};

static int __init mv64x60_sysfs_init(void)
{
	struct device_node *np;
	struct platform_device *pdev;
	const unsigned int *prop;

	np = of_find_compatible_node(NULL, NULL, "marvell,mv64360");
	if (!np)
		return 0;

	prop = of_get_property(np, "hs_reg_valid", NULL);
	of_node_put(np);

	pdev = platform_device_register_simple("marvell,mv64360", 0, NULL, 0);
	if (IS_ERR(pdev))
		return PTR_ERR(pdev);

	return sysfs_create_bin_file(&pdev->dev.kobj, &mv64x60_hs_reg_attr);
}

subsys_initcall(mv64x60_sysfs_init);

#endif /* CONFIG_SYSFS */

static void __init mv64x60_pci_fixup_early(struct pci_dev *dev)
{
	/*
	 * Set the host bridge hdr_type to an invalid value so that
	 * pci_setup_device() will ignore the host bridge.
	 */
	dev->hdr_type = PCI_HEADER_TYPE_INVALID;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360,
			mv64x60_pci_fixup_early);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64460,
			mv64x60_pci_fixup_early);

static int __init mv64x60_add_bridge(struct device_node *dev)
{
	int len;
	struct pci_controller *hose;
	struct resource rsrc;
	const int *bus_range;
	int primary;

	memset(&rsrc, 0, sizeof(rsrc));

	/* Fetch host bridge registers address */
	if (of_address_to_resource(dev, 0, &rsrc)) {
		printk(KERN_ERR "No PCI reg property in device tree\n");
		return -ENODEV;
	}

	/* Get bus range if any */
	bus_range = of_get_property(dev, "bus-range", &len);
	if (bus_range == NULL || len < 2 * sizeof(int))
		printk(KERN_WARNING "Can't get bus-range for %s, assume"
		       " bus 0\n", dev->full_name);

	hose = pcibios_alloc_controller(dev);
	if (!hose)
		return -ENOMEM;

	hose->first_busno = bus_range ? bus_range[0] : 0;
	hose->last_busno = bus_range ? bus_range[1] : 0xff;

	setup_indirect_pci(hose, rsrc.start, rsrc.start + 4, 0);
	hose->self_busno = hose->first_busno;

	printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. "
	       "Firmware bus number: %d->%d\n",
	       (unsigned long long)rsrc.start, hose->first_busno,
	       hose->last_busno);

	/* Interpret the "ranges" property */
	/* This also maps the I/O region and sets isa_io/mem_base */
	primary = (hose->first_busno == 0);
	pci_process_bridge_OF_ranges(hose, dev, primary);

	return 0;
}

void __init mv64x60_pci_init(void)
{
	struct device_node *np;

	for_each_compatible_node(np, "pci", "marvell,mv64360-pci")
		mv64x60_add_bridge(np);
}
Commit	Line	Data
e1a3107b DF	1	/*
	2	* PCI bus setup for Marvell mv64360/mv64460 host bridges (Discovery)
	3	*
	4	* Author: Dale Farnsworth <dale@farnsworth.org>
	5	*
	6	* 2007 (c) MontaVista, Software, Inc. This file is licensed under
	7	* the terms of the GNU General Public License version 2. This program
	8	* is licensed "as is" without any warranty of any kind, whether express
	9	* or implied.
	10	*/
	11
	12	#include <linux/stddef.h>
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/pci.h>
	16
	17	#include <asm/prom.h>
	18	#include <asm/pci-bridge.h>
	19
	20	#define PCI_HEADER_TYPE_INVALID 0x7f /* Invalid PCI header type */
	21
	22	#ifdef CONFIG_SYSFS
	23	/* 32-bit hex or dec stringified number + '\n' */
	24	#define MV64X60_VAL_LEN_MAX 11
	25	#define MV64X60_PCICFG_CPCI_HOTSWAP 0x68
	26
2c3c8bea	27	static ssize_t mv64x60_hs_reg_read(struct file filp, struct kobject kobj,
d102c9d5 DF	28	struct bin_attribute attr, char buf,
d102c9d5 DF	29	loff_t off, size_t count)
e1a3107b DF	30	{
	31	struct pci_dev *phb;
	32	u32 v;
	33
	34	if (off > 0)
	35	return 0;
	36	if (count < MV64X60_VAL_LEN_MAX)
	37	return -EINVAL;
	38
	39	phb = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
	40	if (!phb)
	41	return -ENODEV;
	42	pci_read_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, &v);
	43	pci_dev_put(phb);
	44
	45	return sprintf(buf, "0x%08x\n", v);
	46	}
	47
2c3c8bea	48	static ssize_t mv64x60_hs_reg_write(struct file filp, struct kobject kobj,
d102c9d5 DF	49	struct bin_attribute attr, char buf,
d102c9d5 DF	50	loff_t off, size_t count)
e1a3107b DF	51	{
	52	struct pci_dev *phb;
	53	u32 v;
	54
	55	if (off > 0)
	56	return 0;
	57	if (count <= 0)
	58	return -EINVAL;
	59
	60	if (sscanf(buf, "%i", &v) != 1)
	61	return -EINVAL;
	62
	63	phb = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
	64	if (!phb)
	65	return -ENODEV;
	66	pci_write_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, v);
	67	pci_dev_put(phb);
	68
	69	return count;
	70	}
	71
	72	static struct bin_attribute mv64x60_hs_reg_attr = { /* Hotswap register */
	73	.attr = {
	74	.name = "hs_reg",
	75	.mode = S_IRUGO \| S_IWUSR,
e1a3107b DF	76	},
	77	.size = MV64X60_VAL_LEN_MAX,
	78	.read = mv64x60_hs_reg_read,
	79	.write = mv64x60_hs_reg_write,
	80	};
	81
	82	static int __init mv64x60_sysfs_init(void)
	83	{
	84	struct device_node *np;
	85	struct platform_device *pdev;
	86	const unsigned int *prop;
	87
a1810b44	88	np = of_find_compatible_node(NULL, NULL, "marvell,mv64360");
e1a3107b DF	89	if (!np)
	90	return 0;
	91
	92	prop = of_get_property(np, "hs_reg_valid", NULL);
	93	of_node_put(np);
	94
a1810b44	95	pdev = platform_device_register_simple("marvell,mv64360", 0, NULL, 0);
e1a3107b DF	96	if (IS_ERR(pdev))
	97	return PTR_ERR(pdev);
	98
	99	return sysfs_create_bin_file(&pdev->dev.kobj, &mv64x60_hs_reg_attr);
	100	}
	101
	102	subsys_initcall(mv64x60_sysfs_init);
	103
	104	#endif /* CONFIG_SYSFS */
	105
	106	static void __init mv64x60_pci_fixup_early(struct pci_dev *dev)
	107	{
	108	/*
	109	* Set the host bridge hdr_type to an invalid value so that
	110	* pci_setup_device() will ignore the host bridge.
	111	*/
	112	dev->hdr_type = PCI_HEADER_TYPE_INVALID;
	113	}
	114	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360,
	115	mv64x60_pci_fixup_early);
	116	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64460,
	117	mv64x60_pci_fixup_early);
	118
	119	static int __init mv64x60_add_bridge(struct device_node *dev)
	120	{
	121	int len;
	122	struct pci_controller *hose;
	123	struct resource rsrc;
	124	const int *bus_range;
	125	int primary;
	126
	127	memset(&rsrc, 0, sizeof(rsrc));
	128
	129	/* Fetch host bridge registers address */
	130	if (of_address_to_resource(dev, 0, &rsrc)) {
	131	printk(KERN_ERR "No PCI reg property in device tree\n");
	132	return -ENODEV;
	133	}
	134
	135	/* Get bus range if any */
	136	bus_range = of_get_property(dev, "bus-range", &len);
	137	if (bus_range == NULL \|\| len < 2 * sizeof(int))
	138	printk(KERN_WARNING "Can't get bus-range for %s, assume"
	139	" bus 0\n", dev->full_name);
	140
dbf8471f	141	hose = pcibios_alloc_controller(dev);
e1a3107b DF	142	if (!hose)
	143	return -ENOMEM;
	144
e1a3107b DF	145	hose->first_busno = bus_range ? bus_range[0] : 0;
	146	hose->last_busno = bus_range ? bus_range[1] : 0xff;
	147
2e56ff20	148	setup_indirect_pci(hose, rsrc.start, rsrc.start + 4, 0);
0a3786c5	149	hose->self_busno = hose->first_busno;
e1a3107b DF	150
	151	printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. "
	152	"Firmware bus number: %d->%d\n",
	153	(unsigned long long)rsrc.start, hose->first_busno,
	154	hose->last_busno);
	155
	156	/* Interpret the "ranges" property */
	157	/* This also maps the I/O region and sets isa_io/mem_base */
	158	primary = (hose->first_busno == 0);
	159	pci_process_bridge_OF_ranges(hose, dev, primary);
	160
	161	return 0;
	162	}
	163
	164	void __init mv64x60_pci_init(void)
	165	{
26cb7d8b	166	struct device_node *np;
e1a3107b	167
a1810b44	168	for_each_compatible_node(np, "pci", "marvell,mv64360-pci")
e1a3107b DF	169	mv64x60_add_bridge(np);
e1a3107b DF	170	}