[deliverable/linux.git] / arch / powerpc / sysdev / qe_lib / qe.c

/*
 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
 *
 * Authors: 	Shlomi Gridish <gridish@freescale.com>
 * 		Li Yang <leoli@freescale.com>
 * Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
 *
 * Description:
 * General Purpose functions for the global management of the
 * QUICC Engine (QE).
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/ioport.h>
#include <linux/crc32.h>
#include <asm/irq.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/immap_qe.h>
#include <asm/qe.h>
#include <asm/prom.h>
#include <asm/rheap.h>

static void qe_snums_init(void);
static int qe_sdma_init(void);

static DEFINE_SPINLOCK(qe_lock);
DEFINE_SPINLOCK(cmxgcr_lock);
EXPORT_SYMBOL(cmxgcr_lock);

/* QE snum state */
enum qe_snum_state {
	QE_SNUM_STATE_USED,
	QE_SNUM_STATE_FREE
};

/* QE snum */
struct qe_snum {
	u8 num;
	enum qe_snum_state state;
};

/* We allocate this here because it is used almost exclusively for
 * the communication processor devices.
 */
struct qe_immap __iomem *qe_immr;
EXPORT_SYMBOL(qe_immr);

static struct qe_snum snums[QE_NUM_OF_SNUM];	/* Dynamically allocated SNUMs */
static unsigned int qe_num_of_snum;

static phys_addr_t qebase = -1;

phys_addr_t get_qe_base(void)
{
	struct device_node *qe;
	int size;
	const u32 *prop;

	if (qebase != -1)
		return qebase;

	qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!qe) {
		qe = of_find_node_by_type(NULL, "qe");
		if (!qe)
			return qebase;
	}

	prop = of_get_property(qe, "reg", &size);
	if (prop && size >= sizeof(*prop))
		qebase = of_translate_address(qe, prop);
	of_node_put(qe);

	return qebase;
}

EXPORT_SYMBOL(get_qe_base);

void __init qe_reset(void)
{
	if (qe_immr == NULL)
		qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);

	qe_snums_init();

	qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
		     QE_CR_PROTOCOL_UNSPECIFIED, 0);

	/* Reclaim the MURAM memory for our use. */
	qe_muram_init();

	if (qe_sdma_init())
		panic("sdma init failed!");
}

int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
{
	unsigned long flags;
	u8 mcn_shift = 0, dev_shift = 0;

	spin_lock_irqsave(&qe_lock, flags);
	if (cmd == QE_RESET) {
		out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
	} else {
		if (cmd == QE_ASSIGN_PAGE) {
			/* Here device is the SNUM, not sub-block */
			dev_shift = QE_CR_SNUM_SHIFT;
		} else if (cmd == QE_ASSIGN_RISC) {
			/* Here device is the SNUM, and mcnProtocol is
			 * e_QeCmdRiscAssignment value */
			dev_shift = QE_CR_SNUM_SHIFT;
			mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
		} else {
			if (device == QE_CR_SUBBLOCK_USB)
				mcn_shift = QE_CR_MCN_USB_SHIFT;
			else
				mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
		}

		out_be32(&qe_immr->cp.cecdr, cmd_input);
		out_be32(&qe_immr->cp.cecr,
			 (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
			  mcn_protocol << mcn_shift));
	}

	/* wait for the QE_CR_FLG to clear */
	while(in_be32(&qe_immr->cp.cecr) & QE_CR_FLG)
		cpu_relax();
	spin_unlock_irqrestore(&qe_lock, flags);

	return 0;
}
EXPORT_SYMBOL(qe_issue_cmd);

/* Set a baud rate generator. This needs lots of work. There are
 * 16 BRGs, which can be connected to the QE channels or output
 * as clocks. The BRGs are in two different block of internal
 * memory mapped space.
 * The BRG clock is the QE clock divided by 2.
 * It was set up long ago during the initial boot phase and is
 * is given to us.
 * Baud rate clocks are zero-based in the driver code (as that maps
 * to port numbers). Documentation uses 1-based numbering.
 */
static unsigned int brg_clk = 0;

unsigned int qe_get_brg_clk(void)
{
	struct device_node *qe;
	int size;
	const u32 *prop;

	if (brg_clk)
		return brg_clk;

	qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!qe) {
		qe = of_find_node_by_type(NULL, "qe");
		if (!qe)
			return brg_clk;
	}

	prop = of_get_property(qe, "brg-frequency", &size);
	if (prop && size == sizeof(*prop))
		brg_clk = *prop;

	of_node_put(qe);

	return brg_clk;
}
EXPORT_SYMBOL(qe_get_brg_clk);

/* Program the BRG to the given sampling rate and multiplier
 *
 * @brg: the BRG, QE_BRG1 - QE_BRG16
 * @rate: the desired sampling rate
 * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
 * GUMR_L[TDCR].  E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
 * then 'multiplier' should be 8.
 */
int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
{
	u32 divisor, tempval;
	u32 div16 = 0;

	if ((brg < QE_BRG1) || (brg > QE_BRG16))
		return -EINVAL;

	divisor = qe_get_brg_clk() / (rate * multiplier);

	if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
		div16 = QE_BRGC_DIV16;
		divisor /= 16;
	}

	/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
	   that the BRG divisor must be even if you're not using divide-by-16
	   mode. */
	if (!div16 && (divisor & 1))
		divisor++;

	tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
		QE_BRGC_ENABLE | div16;

	out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);

	return 0;
}
EXPORT_SYMBOL(qe_setbrg);

/* Convert a string to a QE clock source enum
 *
 * This function takes a string, typically from a property in the device
 * tree, and returns the corresponding "enum qe_clock" value.
*/
enum qe_clock qe_clock_source(const char *source)
{
	unsigned int i;

	if (strcasecmp(source, "none") == 0)
		return QE_CLK_NONE;

	if (strncasecmp(source, "brg", 3) == 0) {
		i = simple_strtoul(source + 3, NULL, 10);
		if ((i >= 1) && (i <= 16))
			return (QE_BRG1 - 1) + i;
		else
			return QE_CLK_DUMMY;
	}

	if (strncasecmp(source, "clk", 3) == 0) {
		i = simple_strtoul(source + 3, NULL, 10);
		if ((i >= 1) && (i <= 24))
			return (QE_CLK1 - 1) + i;
		else
			return QE_CLK_DUMMY;
	}

	return QE_CLK_DUMMY;
}
EXPORT_SYMBOL(qe_clock_source);

/* Initialize SNUMs (thread serial numbers) according to
 * QE Module Control chapter, SNUM table
 */
static void qe_snums_init(void)
{
	int i;
	static const u8 snum_init[] = {
		0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
		0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
		0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
		0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
		0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
		0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
	};

	qe_num_of_snum = qe_get_num_of_snums();

	for (i = 0; i < qe_num_of_snum; i++) {
		snums[i].num = snum_init[i];
		snums[i].state = QE_SNUM_STATE_FREE;
	}
}

int qe_get_snum(void)
{
	unsigned long flags;
	int snum = -EBUSY;
	int i;

	spin_lock_irqsave(&qe_lock, flags);
	for (i = 0; i < qe_num_of_snum; i++) {
		if (snums[i].state == QE_SNUM_STATE_FREE) {
			snums[i].state = QE_SNUM_STATE_USED;
			snum = snums[i].num;
			break;
		}
	}
	spin_unlock_irqrestore(&qe_lock, flags);

	return snum;
}
EXPORT_SYMBOL(qe_get_snum);

void qe_put_snum(u8 snum)
{
	int i;

	for (i = 0; i < qe_num_of_snum; i++) {
		if (snums[i].num == snum) {
			snums[i].state = QE_SNUM_STATE_FREE;
			break;
		}
	}
}
EXPORT_SYMBOL(qe_put_snum);

static int qe_sdma_init(void)
{
	struct sdma __iomem *sdma = &qe_immr->sdma;
	unsigned long sdma_buf_offset;

	if (!sdma)
		return -ENODEV;

	/* allocate 2 internal temporary buffers (512 bytes size each) for
	 * the SDMA */
 	sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
	if (IS_ERR_VALUE(sdma_buf_offset))
		return -ENOMEM;

	out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
 	out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
 					(0x1 << QE_SDMR_CEN_SHIFT)));

	return 0;
}

/* The maximum number of RISCs we support */
#define MAX_QE_RISC     2

/* Firmware information stored here for qe_get_firmware_info() */
static struct qe_firmware_info qe_firmware_info;

/*
 * Set to 1 if QE firmware has been uploaded, and therefore
 * qe_firmware_info contains valid data.
 */
static int qe_firmware_uploaded;

/*
 * Upload a QE microcode
 *
 * This function is a worker function for qe_upload_firmware().  It does
 * the actual uploading of the microcode.
 */
static void qe_upload_microcode(const void *base,
	const struct qe_microcode *ucode)
{
	const __be32 *code = base + be32_to_cpu(ucode->code_offset);
	unsigned int i;

	if (ucode->major || ucode->minor || ucode->revision)
		printk(KERN_INFO "qe-firmware: "
			"uploading microcode '%s' version %u.%u.%u\n",
			ucode->id, ucode->major, ucode->minor, ucode->revision);
	else
		printk(KERN_INFO "qe-firmware: "
			"uploading microcode '%s'\n", ucode->id);

	/* Use auto-increment */
	out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
		QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);

	for (i = 0; i < be32_to_cpu(ucode->count); i++)
		out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
}

/*
 * Upload a microcode to the I-RAM at a specific address.
 *
 * See Documentation/powerpc/qe-firmware.txt for information on QE microcode
 * uploading.
 *
 * Currently, only version 1 is supported, so the 'version' field must be
 * set to 1.
 *
 * The SOC model and revision are not validated, they are only displayed for
 * informational purposes.
 *
 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
 * all of the microcode structures, minus the CRC.
 *
 * 'length' is the size that the structure says it is, including the CRC.
 */
int qe_upload_firmware(const struct qe_firmware *firmware)
{
	unsigned int i;
	unsigned int j;
	u32 crc;
	size_t calc_size = sizeof(struct qe_firmware);
	size_t length;
	const struct qe_header *hdr;

	if (!firmware) {
		printk(KERN_ERR "qe-firmware: invalid pointer\n");
		return -EINVAL;
	}

	hdr = &firmware->header;
	length = be32_to_cpu(hdr->length);

	/* Check the magic */
	if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
	    (hdr->magic[2] != 'F')) {
		printk(KERN_ERR "qe-firmware: not a microcode\n");
		return -EPERM;
	}

	/* Check the version */
	if (hdr->version != 1) {
		printk(KERN_ERR "qe-firmware: unsupported version\n");
		return -EPERM;
	}

	/* Validate some of the fields */
	if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
		printk(KERN_ERR "qe-firmware: invalid data\n");
		return -EINVAL;
	}

	/* Validate the length and check if there's a CRC */
	calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);

	for (i = 0; i < firmware->count; i++)
		/*
		 * For situations where the second RISC uses the same microcode
		 * as the first, the 'code_offset' and 'count' fields will be
		 * zero, so it's okay to add those.
		 */
		calc_size += sizeof(__be32) *
			be32_to_cpu(firmware->microcode[i].count);

	/* Validate the length */
	if (length != calc_size + sizeof(__be32)) {
		printk(KERN_ERR "qe-firmware: invalid length\n");
		return -EPERM;
	}

	/* Validate the CRC */
	crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
	if (crc != crc32(0, firmware, calc_size)) {
		printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
		return -EIO;
	}

	/*
	 * If the microcode calls for it, split the I-RAM.
	 */
	if (!firmware->split)
		setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);

	if (firmware->soc.model)
		printk(KERN_INFO
			"qe-firmware: firmware '%s' for %u V%u.%u\n",
			firmware->id, be16_to_cpu(firmware->soc.model),
			firmware->soc.major, firmware->soc.minor);
	else
		printk(KERN_INFO "qe-firmware: firmware '%s'\n",
			firmware->id);

	/*
	 * The QE only supports one microcode per RISC, so clear out all the
	 * saved microcode information and put in the new.
	 */
	memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
	strcpy(qe_firmware_info.id, firmware->id);
	qe_firmware_info.extended_modes = firmware->extended_modes;
	memcpy(qe_firmware_info.vtraps, firmware->vtraps,
		sizeof(firmware->vtraps));

	/* Loop through each microcode. */
	for (i = 0; i < firmware->count; i++) {
		const struct qe_microcode *ucode = &firmware->microcode[i];

		/* Upload a microcode if it's present */
		if (ucode->code_offset)
			qe_upload_microcode(firmware, ucode);

		/* Program the traps for this processor */
		for (j = 0; j < 16; j++) {
			u32 trap = be32_to_cpu(ucode->traps[j]);

			if (trap)
				out_be32(&qe_immr->rsp[i].tibcr[j], trap);
		}

		/* Enable traps */
		out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
	}

	qe_firmware_uploaded = 1;

	return 0;
}
EXPORT_SYMBOL(qe_upload_firmware);

/*
 * Get info on the currently-loaded firmware
 *
 * This function also checks the device tree to see if the boot loader has
 * uploaded a firmware already.
 */
struct qe_firmware_info *qe_get_firmware_info(void)
{
	static int initialized;
	struct property *prop;
	struct device_node *qe;
	struct device_node *fw = NULL;
	const char *sprop;
	unsigned int i;

	/*
	 * If we haven't checked yet, and a driver hasn't uploaded a firmware
	 * yet, then check the device tree for information.
	 */
	if (qe_firmware_uploaded)
		return &qe_firmware_info;

	if (initialized)
		return NULL;

	initialized = 1;

	/*
	 * Newer device trees have an "fsl,qe" compatible property for the QE
	 * node, but we still need to support older device trees.
	*/
	qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!qe) {
		qe = of_find_node_by_type(NULL, "qe");
		if (!qe)
			return NULL;
	}

	/* Find the 'firmware' child node */
	for_each_child_of_node(qe, fw) {
		if (strcmp(fw->name, "firmware") == 0)
			break;
	}

	of_node_put(qe);

	/* Did we find the 'firmware' node? */
	if (!fw)
		return NULL;

	qe_firmware_uploaded = 1;

	/* Copy the data into qe_firmware_info*/
	sprop = of_get_property(fw, "id", NULL);
	if (sprop)
		strncpy(qe_firmware_info.id, sprop,
			sizeof(qe_firmware_info.id) - 1);

	prop = of_find_property(fw, "extended-modes", NULL);
	if (prop && (prop->length == sizeof(u64))) {
		const u64 *iprop = prop->value;

		qe_firmware_info.extended_modes = *iprop;
	}

	prop = of_find_property(fw, "virtual-traps", NULL);
	if (prop && (prop->length == 32)) {
		const u32 *iprop = prop->value;

		for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++)
			qe_firmware_info.vtraps[i] = iprop[i];
	}

	of_node_put(fw);

	return &qe_firmware_info;
}
EXPORT_SYMBOL(qe_get_firmware_info);

unsigned int qe_get_num_of_risc(void)
{
	struct device_node *qe;
	int size;
	unsigned int num_of_risc = 0;
	const u32 *prop;

	qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!qe) {
		/* Older devices trees did not have an "fsl,qe"
		 * compatible property, so we need to look for
		 * the QE node by name.
		 */
		qe = of_find_node_by_type(NULL, "qe");
		if (!qe)
			return num_of_risc;
	}

	prop = of_get_property(qe, "fsl,qe-num-riscs", &size);
	if (prop && size == sizeof(*prop))
		num_of_risc = *prop;

	of_node_put(qe);

	return num_of_risc;
}
EXPORT_SYMBOL(qe_get_num_of_risc);

unsigned int qe_get_num_of_snums(void)
{
	struct device_node *qe;
	int size;
	unsigned int num_of_snums;
	const u32 *prop;

	num_of_snums = 28; /* The default number of snum for threads is 28 */
	qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!qe) {
		/* Older devices trees did not have an "fsl,qe"
		 * compatible property, so we need to look for
		 * the QE node by name.
		 */
		qe = of_find_node_by_type(NULL, "qe");
		if (!qe)
			return num_of_snums;
	}

	prop = of_get_property(qe, "fsl,qe-num-snums", &size);
	if (prop && size == sizeof(*prop)) {
		num_of_snums = *prop;
		if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) {
			/* No QE ever has fewer than 28 SNUMs */
			pr_err("QE: number of snum is invalid\n");
			return -EINVAL;
		}
	}

	of_node_put(qe);

	return num_of_snums;
}
EXPORT_SYMBOL(qe_get_num_of_snums);
Commit	Line	Data
98658538 LY	1	/*
	2	* Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
	3	*
	4	* Authors: Shlomi Gridish <gridish@freescale.com>
	5	* Li Yang <leoli@freescale.com>
	6	* Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
	7	*
	8	* Description:
	9	* General Purpose functions for the global management of the
	10	* QUICC Engine (QE).
	11	*
	12	* This program is free software; you can redistribute it and/or modify it
	13	* under the terms of the GNU General Public License as published by the
	14	* Free Software Foundation; either version 2 of the License, or (at your
	15	* option) any later version.
	16	*/
	17	#include <linux/errno.h>
	18	#include <linux/sched.h>
	19	#include <linux/kernel.h>
	20	#include <linux/param.h>
	21	#include <linux/string.h>
09a3fba8	22	#include <linux/spinlock.h>
98658538 LY	23	#include <linux/mm.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/bootmem.h>
	26	#include <linux/module.h>
	27	#include <linux/delay.h>
	28	#include <linux/ioport.h>
bc556ba9	29	#include <linux/crc32.h>
98658538 LY	30	#include <asm/irq.h>
	31	#include <asm/page.h>
	32	#include <asm/pgtable.h>
	33	#include <asm/immap_qe.h>
	34	#include <asm/qe.h>
	35	#include <asm/prom.h>
	36	#include <asm/rheap.h>
	37
	38	static void qe_snums_init(void);
98658538 LY	39	static int qe_sdma_init(void);
	40
	41	static DEFINE_SPINLOCK(qe_lock);
09a3fba8 AV	42	DEFINE_SPINLOCK(cmxgcr_lock);
09a3fba8 AV	43	EXPORT_SYMBOL(cmxgcr_lock);
98658538 LY	44
	45	/* QE snum state */
	46	enum qe_snum_state {
	47	QE_SNUM_STATE_USED,
	48	QE_SNUM_STATE_FREE
	49	};
	50
	51	/* QE snum */
	52	struct qe_snum {
	53	u8 num;
	54	enum qe_snum_state state;
	55	};
	56
	57	/* We allocate this here because it is used almost exclusively for
	58	* the communication processor devices.
	59	*/
0b51b02e	60	struct qe_immap __iomem *qe_immr;
98658538 LY	61	EXPORT_SYMBOL(qe_immr);
	62
	63	static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
98ca77af	64	static unsigned int qe_num_of_snum;
98658538 LY	65
	66	static phys_addr_t qebase = -1;
	67
	68	phys_addr_t get_qe_base(void)
	69	{
	70	struct device_node *qe;
7e1cc9c5	71	int size;
d8985fd2	72	const u32 *prop;
98658538 LY	73
	74	if (qebase != -1)
	75	return qebase;
	76
a2dd70a1 AV	77	qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
	78	if (!qe) {
	79	qe = of_find_node_by_type(NULL, "qe");
	80	if (!qe)
	81	return qebase;
	82	}
	83
	84	prop = of_get_property(qe, "reg", &size);
d8985fd2 AV	85	if (prop && size >= sizeof(*prop))
d8985fd2 AV	86	qebase = of_translate_address(qe, prop);
a2dd70a1	87	of_node_put(qe);
98658538 LY	88
	89	return qebase;
	90	}
	91
	92	EXPORT_SYMBOL(get_qe_base);
	93
5848f169	94	void __init qe_reset(void)
98658538 LY	95	{
	96	if (qe_immr == NULL)
	97	qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
	98
	99	qe_snums_init();
	100
	101	qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
	102	QE_CR_PROTOCOL_UNSPECIFIED, 0);
	103
	104	/* Reclaim the MURAM memory for our use. */
	105	qe_muram_init();
	106
	107	if (qe_sdma_init())
	108	panic("sdma init failed!");
	109	}
	110
	111	int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
	112	{
	113	unsigned long flags;
	114	u8 mcn_shift = 0, dev_shift = 0;
	115
	116	spin_lock_irqsave(&qe_lock, flags);
	117	if (cmd == QE_RESET) {
	118	out_be32(&qe_immr->cp.cecr, (u32) (cmd \| QE_CR_FLG));
	119	} else {
	120	if (cmd == QE_ASSIGN_PAGE) {
	121	/* Here device is the SNUM, not sub-block */
	122	dev_shift = QE_CR_SNUM_SHIFT;
	123	} else if (cmd == QE_ASSIGN_RISC) {
	124	/* Here device is the SNUM, and mcnProtocol is
	125	* e_QeCmdRiscAssignment value */
	126	dev_shift = QE_CR_SNUM_SHIFT;
	127	mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
	128	} else {
	129	if (device == QE_CR_SUBBLOCK_USB)
	130	mcn_shift = QE_CR_MCN_USB_SHIFT;
	131	else
	132	mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
	133	}
	134
302439d2	135	out_be32(&qe_immr->cp.cecdr, cmd_input);
98658538 LY	136	out_be32(&qe_immr->cp.cecr,
	137	(cmd \| QE_CR_FLG \| ((u32) device << dev_shift) \| (u32)
	138	mcn_protocol << mcn_shift));
	139	}
	140
	141	/* wait for the QE_CR_FLG to clear */
	142	while(in_be32(&qe_immr->cp.cecr) & QE_CR_FLG)
	143	cpu_relax();
	144	spin_unlock_irqrestore(&qe_lock, flags);
	145
	146	return 0;
	147	}
	148	EXPORT_SYMBOL(qe_issue_cmd);
	149
	150	/* Set a baud rate generator. This needs lots of work. There are
	151	* 16 BRGs, which can be connected to the QE channels or output
	152	* as clocks. The BRGs are in two different block of internal
	153	* memory mapped space.
6b0b594b	154	* The BRG clock is the QE clock divided by 2.
98658538 LY	155	* It was set up long ago during the initial boot phase and is
	156	* is given to us.
	157	* Baud rate clocks are zero-based in the driver code (as that maps
	158	* to port numbers). Documentation uses 1-based numbering.
	159	*/
	160	static unsigned int brg_clk = 0;
	161
7f0a6fc8	162	unsigned int qe_get_brg_clk(void)
98658538 LY	163	{
98658538 LY	164	struct device_node *qe;
7e1cc9c5	165	int size;
a2dd70a1 AV	166	const u32 *prop;
a2dd70a1 AV	167
98658538 LY	168	if (brg_clk)
	169	return brg_clk;
	170
a2dd70a1 AV	171	qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
	172	if (!qe) {
	173	qe = of_find_node_by_type(NULL, "qe");
	174	if (!qe)
	175	return brg_clk;
	176	}
	177
	178	prop = of_get_property(qe, "brg-frequency", &size);
d8985fd2 AV	179	if (prop && size == sizeof(*prop))
d8985fd2 AV	180	brg_clk = *prop;
a2dd70a1	181
a2dd70a1 AV	182	of_node_put(qe);
a2dd70a1 AV	183
98658538 LY	184	return brg_clk;
98658538 LY	185	}
7f0a6fc8	186	EXPORT_SYMBOL(qe_get_brg_clk);
98658538	187
6b0b594b TT	188	/* Program the BRG to the given sampling rate and multiplier
6b0b594b TT	189	*
7264ec44	190	* @brg: the BRG, QE_BRG1 - QE_BRG16
6b0b594b TT	191	* @rate: the desired sampling rate
	192	* @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
	193	* GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
	194	* then 'multiplier' should be 8.
98658538	195	*/
7264ec44	196	int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
98658538	197	{
98658538	198	u32 divisor, tempval;
6b0b594b	199	u32 div16 = 0;
98658538	200
7264ec44 TT	201	if ((brg < QE_BRG1) \|\| (brg > QE_BRG16))
	202	return -EINVAL;
	203
7f0a6fc8	204	divisor = qe_get_brg_clk() / (rate * multiplier);
98658538	205
98658538	206	if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
6b0b594b	207	div16 = QE_BRGC_DIV16;
98658538 LY	208	divisor /= 16;
	209	}
	210
6b0b594b TT	211	/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
	212	that the BRG divisor must be even if you're not using divide-by-16
	213	mode. */
	214	if (!div16 && (divisor & 1))
	215	divisor++;
	216
	217	tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) \|
	218	QE_BRGC_ENABLE \| div16;
98658538	219
7264ec44 TT	220	out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
	221
	222	return 0;
98658538	223	}
7264ec44	224	EXPORT_SYMBOL(qe_setbrg);
98658538	225
174b0da2 TT	226	/* Convert a string to a QE clock source enum
	227	*
	228	* This function takes a string, typically from a property in the device
	229	* tree, and returns the corresponding "enum qe_clock" value.
	230	*/
	231	enum qe_clock qe_clock_source(const char *source)
	232	{
	233	unsigned int i;
	234
	235	if (strcasecmp(source, "none") == 0)
	236	return QE_CLK_NONE;
	237
	238	if (strncasecmp(source, "brg", 3) == 0) {
	239	i = simple_strtoul(source + 3, NULL, 10);
	240	if ((i >= 1) && (i <= 16))
	241	return (QE_BRG1 - 1) + i;
	242	else
	243	return QE_CLK_DUMMY;
	244	}
	245
	246	if (strncasecmp(source, "clk", 3) == 0) {
	247	i = simple_strtoul(source + 3, NULL, 10);
	248	if ((i >= 1) && (i <= 24))
	249	return (QE_CLK1 - 1) + i;
	250	else
	251	return QE_CLK_DUMMY;
	252	}
	253
	254	return QE_CLK_DUMMY;
	255	}
	256	EXPORT_SYMBOL(qe_clock_source);
	257
98658538 LY	258	/* Initialize SNUMs (thread serial numbers) according to
	259	* QE Module Control chapter, SNUM table
	260	*/
	261	static void qe_snums_init(void)
	262	{
	263	int i;
	264	static const u8 snum_init[] = {
	265	0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
	266	0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
	267	0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
98ca77af HW	268	0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
	269	0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
	270	0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
98658538 LY	271	};
98658538 LY	272
98ca77af HW	273	qe_num_of_snum = qe_get_num_of_snums();
	274
	275	for (i = 0; i < qe_num_of_snum; i++) {
98658538 LY	276	snums[i].num = snum_init[i];
	277	snums[i].state = QE_SNUM_STATE_FREE;
	278	}
	279	}
	280
	281	int qe_get_snum(void)
	282	{
	283	unsigned long flags;
	284	int snum = -EBUSY;
	285	int i;
	286
	287	spin_lock_irqsave(&qe_lock, flags);
98ca77af	288	for (i = 0; i < qe_num_of_snum; i++) {
98658538 LY	289	if (snums[i].state == QE_SNUM_STATE_FREE) {
	290	snums[i].state = QE_SNUM_STATE_USED;
	291	snum = snums[i].num;
	292	break;
	293	}
	294	}
	295	spin_unlock_irqrestore(&qe_lock, flags);
	296
	297	return snum;
	298	}
	299	EXPORT_SYMBOL(qe_get_snum);
	300
	301	void qe_put_snum(u8 snum)
	302	{
	303	int i;
	304
98ca77af	305	for (i = 0; i < qe_num_of_snum; i++) {
98658538 LY	306	if (snums[i].num == snum) {
	307	snums[i].state = QE_SNUM_STATE_FREE;
	308	break;
	309	}
	310	}
	311	}
	312	EXPORT_SYMBOL(qe_put_snum);
	313
	314	static int qe_sdma_init(void)
	315	{
7e1cc9c5	316	struct sdma __iomem *sdma = &qe_immr->sdma;
4c35630c	317	unsigned long sdma_buf_offset;
98658538 LY	318
	319	if (!sdma)
	320	return -ENODEV;
	321
	322	/* allocate 2 internal temporary buffers (512 bytes size each) for
	323	* the SDMA */
7f013bc9	324	sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
4c35630c	325	if (IS_ERR_VALUE(sdma_buf_offset))
98658538 LY	326	return -ENOMEM;
98658538 LY	327
4c35630c	328	out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
7f013bc9 CM	329	out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK \|
7f013bc9 CM	330	(0x1 << QE_SDMR_CEN_SHIFT)));
98658538 LY	331
	332	return 0;
	333	}
	334
bc556ba9 TT	335	/* The maximum number of RISCs we support */
	336	#define MAX_QE_RISC 2
	337
	338	/* Firmware information stored here for qe_get_firmware_info() */
	339	static struct qe_firmware_info qe_firmware_info;
	340
	341	/*
	342	* Set to 1 if QE firmware has been uploaded, and therefore
	343	* qe_firmware_info contains valid data.
	344	*/
	345	static int qe_firmware_uploaded;
	346
	347	/*
	348	* Upload a QE microcode
	349	*
	350	* This function is a worker function for qe_upload_firmware(). It does
	351	* the actual uploading of the microcode.
	352	*/
	353	static void qe_upload_microcode(const void *base,
	354	const struct qe_microcode *ucode)
	355	{
	356	const __be32 *code = base + be32_to_cpu(ucode->code_offset);
	357	unsigned int i;
	358
	359	if (ucode->major \|\| ucode->minor \|\| ucode->revision)
	360	printk(KERN_INFO "qe-firmware: "
	361	"uploading microcode '%s' version %u.%u.%u\n",
	362	ucode->id, ucode->major, ucode->minor, ucode->revision);
	363	else
	364	printk(KERN_INFO "qe-firmware: "
	365	"uploading microcode '%s'\n", ucode->id);
	366
	367	/* Use auto-increment */
	368	out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) \|
	369	QE_IRAM_IADD_AIE \| QE_IRAM_IADD_BADDR);
	370
	371	for (i = 0; i < be32_to_cpu(ucode->count); i++)
	372	out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
	373	}
	374
	375	/*
	376	* Upload a microcode to the I-RAM at a specific address.
	377	*
	378	* See Documentation/powerpc/qe-firmware.txt for information on QE microcode
	379	* uploading.
	380	*
	381	* Currently, only version 1 is supported, so the 'version' field must be
	382	* set to 1.
	383	*
	384	* The SOC model and revision are not validated, they are only displayed for
	385	* informational purposes.
	386	*
	387	* 'calc_size' is the calculated size, in bytes, of the firmware structure and
	388	* all of the microcode structures, minus the CRC.
	389	*
	390	* 'length' is the size that the structure says it is, including the CRC.
	391	*/
	392	int qe_upload_firmware(const struct qe_firmware *firmware)
	393	{
	394	unsigned int i;
	395	unsigned int j;
	396	u32 crc;
	397	size_t calc_size = sizeof(struct qe_firmware);
	398	size_t length;
399	const struct qe_header *hdr;
400
401	if (!firmware) {
402	printk(KERN_ERR "qe-firmware: invalid pointer\n");
403	return -EINVAL;
404	}
405
406	hdr = &firmware->header;
407	length = be32_to_cpu(hdr->length);
408
409	/* Check the magic */
410	if ((hdr->magic[0] != 'Q') \|\| (hdr->magic[1] != 'E') \|\|
411	(hdr->magic[2] != 'F')) {
412	printk(KERN_ERR "qe-firmware: not a microcode\n");
413	return -EPERM;
414	}
415
416	/* Check the version */
417	if (hdr->version != 1) {
418	printk(KERN_ERR "qe-firmware: unsupported version\n");
419	return -EPERM;
420	}
421
422	/* Validate some of the fields */
6f913160	423	if ((firmware->count < 1) \|\| (firmware->count > MAX_QE_RISC)) {
bc556ba9 TT	424	printk(KERN_ERR "qe-firmware: invalid data\n");
	425	return -EINVAL;
	426	}
	427
	428	/* Validate the length and check if there's a CRC */
	429	calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
	430
	431	for (i = 0; i < firmware->count; i++)
	432	/*
	433	* For situations where the second RISC uses the same microcode
	434	* as the first, the 'code_offset' and 'count' fields will be
	435	* zero, so it's okay to add those.
	436	*/
	437	calc_size += sizeof(__be32) *
	438	be32_to_cpu(firmware->microcode[i].count);
	439
	440	/* Validate the length */
	441	if (length != calc_size + sizeof(__be32)) {
	442	printk(KERN_ERR "qe-firmware: invalid length\n");
	443	return -EPERM;
	444	}
	445
	446	/* Validate the CRC */
	447	crc = be32_to_cpu((__be32 )((void *)firmware + calc_size));
	448	if (crc != crc32(0, firmware, calc_size)) {
	449	printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
	450	return -EIO;
	451	}
	452
	453	/*
	454	* If the microcode calls for it, split the I-RAM.
	455	*/
	456	if (!firmware->split)
	457	setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
	458
	459	if (firmware->soc.model)
	460	printk(KERN_INFO
	461	"qe-firmware: firmware '%s' for %u V%u.%u\n",
	462	firmware->id, be16_to_cpu(firmware->soc.model),
	463	firmware->soc.major, firmware->soc.minor);
	464	else
	465	printk(KERN_INFO "qe-firmware: firmware '%s'\n",
	466	firmware->id);
	467
	468	/*
	469	* The QE only supports one microcode per RISC, so clear out all the
	470	* saved microcode information and put in the new.
	471	*/
	472	memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
	473	strcpy(qe_firmware_info.id, firmware->id);
	474	qe_firmware_info.extended_modes = firmware->extended_modes;
	475	memcpy(qe_firmware_info.vtraps, firmware->vtraps,
	476	sizeof(firmware->vtraps));
	477
	478	/* Loop through each microcode. */
	479	for (i = 0; i < firmware->count; i++) {
	480	const struct qe_microcode *ucode = &firmware->microcode[i];
	481
	482	/* Upload a microcode if it's present */
	483	if (ucode->code_offset)
	484	qe_upload_microcode(firmware, ucode);
	485
	486	/* Program the traps for this processor */
	487	for (j = 0; j < 16; j++) {
488	u32 trap = be32_to_cpu(ucode->traps[j]);
489
490	if (trap)
491	out_be32(&qe_immr->rsp[i].tibcr[j], trap);
492	}
493
494	/* Enable traps */
495	out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
496	}
497
498	qe_firmware_uploaded = 1;
499
500	return 0;
501	}
502	EXPORT_SYMBOL(qe_upload_firmware);
503
504	/*
505	* Get info on the currently-loaded firmware
506	*
507	* This function also checks the device tree to see if the boot loader has
508	* uploaded a firmware already.
509	*/
510	struct qe_firmware_info *qe_get_firmware_info(void)
511	{
512	static int initialized;
513	struct property *prop;
514	struct device_node *qe;
515	struct device_node *fw = NULL;
516	const char *sprop;
517	unsigned int i;
518
519	/*
520	* If we haven't checked yet, and a driver hasn't uploaded a firmware
521	* yet, then check the device tree for information.
522	*/
86f4e5d4 IN	523	if (qe_firmware_uploaded)
	524	return &qe_firmware_info;
	525
	526	if (initialized)
bc556ba9 TT	527	return NULL;
	528
	529	initialized = 1;
	530
	531	/*
	532	* Newer device trees have an "fsl,qe" compatible property for the QE
	533	* node, but we still need to support older device trees.
	534	*/
	535	qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
	536	if (!qe) {
	537	qe = of_find_node_by_type(NULL, "qe");
	538	if (!qe)
	539	return NULL;
	540	}
	541
	542	/* Find the 'firmware' child node */
	543	for_each_child_of_node(qe, fw) {
	544	if (strcmp(fw->name, "firmware") == 0)
	545	break;
	546	}
	547
	548	of_node_put(qe);
	549
	550	/* Did we find the 'firmware' node? */
	551	if (!fw)
	552	return NULL;
	553
	554	qe_firmware_uploaded = 1;
	555
	556	/* Copy the data into qe_firmware_info*/
	557	sprop = of_get_property(fw, "id", NULL);
	558	if (sprop)
	559	strncpy(qe_firmware_info.id, sprop,
	560	sizeof(qe_firmware_info.id) - 1);
	561
	562	prop = of_find_property(fw, "extended-modes", NULL);
	563	if (prop && (prop->length == sizeof(u64))) {
	564	const u64 *iprop = prop->value;
	565
	566	qe_firmware_info.extended_modes = *iprop;
	567	}
	568
	569	prop = of_find_property(fw, "virtual-traps", NULL);
	570	if (prop && (prop->length == 32)) {
	571	const u32 *iprop = prop->value;
	572
	573	for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++)
	574	qe_firmware_info.vtraps[i] = iprop[i];
	575	}
	576
	577	of_node_put(fw);
	578
	579	return &qe_firmware_info;
	580	}
	581	EXPORT_SYMBOL(qe_get_firmware_info);
	582
06c44350 HW	583	unsigned int qe_get_num_of_risc(void)
	584	{
	585	struct device_node *qe;
	586	int size;
	587	unsigned int num_of_risc = 0;
	588	const u32 *prop;
	589
	590	qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
	591	if (!qe) {
	592	/* Older devices trees did not have an "fsl,qe"
	593	* compatible property, so we need to look for
	594	* the QE node by name.
	595	*/
	596	qe = of_find_node_by_type(NULL, "qe");
	597	if (!qe)
	598	return num_of_risc;
	599	}
	600
	601	prop = of_get_property(qe, "fsl,qe-num-riscs", &size);
	602	if (prop && size == sizeof(*prop))
	603	num_of_risc = *prop;
	604
	605	of_node_put(qe);
	606
	607	return num_of_risc;
	608	}
	609	EXPORT_SYMBOL(qe_get_num_of_risc);
	610
98ca77af HW	611	unsigned int qe_get_num_of_snums(void)
	612	{
	613	struct device_node *qe;
	614	int size;
	615	unsigned int num_of_snums;
	616	const u32 *prop;
	617
	618	num_of_snums = 28; /* The default number of snum for threads is 28 */
	619	qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
	620	if (!qe) {
	621	/* Older devices trees did not have an "fsl,qe"
	622	* compatible property, so we need to look for
	623	* the QE node by name.
	624	*/
	625	qe = of_find_node_by_type(NULL, "qe");
	626	if (!qe)
	627	return num_of_snums;
	628	}
	629
	630	prop = of_get_property(qe, "fsl,qe-num-snums", &size);
	631	if (prop && size == sizeof(*prop)) {
	632	num_of_snums = *prop;
	633	if ((num_of_snums < 28) \|\| (num_of_snums > QE_NUM_OF_SNUM)) {
	634	/* No QE ever has fewer than 28 SNUMs */
	635	pr_err("QE: number of snum is invalid\n");
	636	return -EINVAL;
	637	}
	638	}
	639
	640	of_node_put(qe);
	641
	642	return num_of_snums;
	643	}
	644	EXPORT_SYMBOL(qe_get_num_of_snums);