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0b05ac6e BH |
1 | /* |
2 | * Copyright 2011 IBM Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | */ | |
10 | #include <linux/types.h> | |
11 | #include <linux/threads.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/irq.h> | |
14 | #include <linux/debugfs.h> | |
15 | #include <linux/smp.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/seq_file.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/cpu.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | ||
24 | #include <asm/prom.h> | |
25 | #include <asm/io.h> | |
26 | #include <asm/smp.h> | |
27 | #include <asm/machdep.h> | |
28 | #include <asm/irq.h> | |
29 | #include <asm/errno.h> | |
30 | #include <asm/rtas.h> | |
31 | #include <asm/xics.h> | |
32 | #include <asm/firmware.h> | |
33 | ||
34 | /* Globals common to all ICP/ICS implementations */ | |
35 | const struct icp_ops *icp_ops; | |
36 | ||
37 | unsigned int xics_default_server = 0xff; | |
38 | unsigned int xics_default_distrib_server = 0; | |
39 | unsigned int xics_interrupt_server_size = 8; | |
40 | ||
41 | DEFINE_PER_CPU(struct xics_cppr, xics_cppr); | |
42 | ||
bae1d8f1 | 43 | struct irq_domain *xics_host; |
0b05ac6e BH |
44 | |
45 | static LIST_HEAD(ics_list); | |
46 | ||
47 | void xics_update_irq_servers(void) | |
48 | { | |
49 | int i, j; | |
50 | struct device_node *np; | |
51 | u32 ilen; | |
d213dd53 | 52 | const __be32 *ireg; |
0b05ac6e BH |
53 | u32 hcpuid; |
54 | ||
55 | /* Find the server numbers for the boot cpu. */ | |
56 | np = of_get_cpu_node(boot_cpuid, NULL); | |
57 | BUG_ON(!np); | |
58 | ||
59 | hcpuid = get_hard_smp_processor_id(boot_cpuid); | |
f6e17f9b BH |
60 | xics_default_server = xics_default_distrib_server = hcpuid; |
61 | ||
62 | pr_devel("xics: xics_default_server = 0x%x\n", xics_default_server); | |
0b05ac6e BH |
63 | |
64 | ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen); | |
65 | if (!ireg) { | |
66 | of_node_put(np); | |
67 | return; | |
68 | } | |
69 | ||
70 | i = ilen / sizeof(int); | |
71 | ||
72 | /* Global interrupt distribution server is specified in the last | |
73 | * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last | |
74 | * entry fom this property for current boot cpu id and use it as | |
75 | * default distribution server | |
76 | */ | |
77 | for (j = 0; j < i; j += 2) { | |
d213dd53 AB |
78 | if (be32_to_cpu(ireg[j]) == hcpuid) { |
79 | xics_default_distrib_server = be32_to_cpu(ireg[j+1]); | |
f6e17f9b | 80 | break; |
0b05ac6e BH |
81 | } |
82 | } | |
f6e17f9b BH |
83 | pr_devel("xics: xics_default_distrib_server = 0x%x\n", |
84 | xics_default_distrib_server); | |
0b05ac6e BH |
85 | of_node_put(np); |
86 | } | |
87 | ||
88 | /* GIQ stuff, currently only supported on RTAS setups, will have | |
89 | * to be sorted properly for bare metal | |
90 | */ | |
91 | void xics_set_cpu_giq(unsigned int gserver, unsigned int join) | |
92 | { | |
93 | #ifdef CONFIG_PPC_RTAS | |
94 | int index; | |
95 | int status; | |
96 | ||
97 | if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL)) | |
98 | return; | |
99 | ||
100 | index = (1UL << xics_interrupt_server_size) - 1 - gserver; | |
101 | ||
102 | status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join); | |
103 | ||
104 | WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n", | |
105 | GLOBAL_INTERRUPT_QUEUE, index, join, status); | |
106 | #endif | |
107 | } | |
108 | ||
109 | void xics_setup_cpu(void) | |
110 | { | |
111 | icp_ops->set_priority(LOWEST_PRIORITY); | |
112 | ||
113 | xics_set_cpu_giq(xics_default_distrib_server, 1); | |
114 | } | |
115 | ||
116 | void xics_mask_unknown_vec(unsigned int vec) | |
117 | { | |
118 | struct ics *ics; | |
119 | ||
f6e17f9b | 120 | pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec); |
0b05ac6e BH |
121 | |
122 | list_for_each_entry(ics, &ics_list, link) | |
123 | ics->mask_unknown(ics, vec); | |
124 | } | |
125 | ||
126 | ||
127 | #ifdef CONFIG_SMP | |
128 | ||
0b05ac6e BH |
129 | static void xics_request_ipi(void) |
130 | { | |
131 | unsigned int ipi; | |
132 | ||
133 | ipi = irq_create_mapping(xics_host, XICS_IPI); | |
134 | BUG_ON(ipi == NO_IRQ); | |
135 | ||
136 | /* | |
a3a9f3b4 | 137 | * IPIs are marked IRQF_PERCPU. The handler was set in map. |
0b05ac6e | 138 | */ |
0b05ac6e | 139 | BUG_ON(request_irq(ipi, icp_ops->ipi_action, |
3b5e16d7 | 140 | IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL)); |
0b05ac6e BH |
141 | } |
142 | ||
a7f4ee1f | 143 | void __init xics_smp_probe(void) |
0b05ac6e | 144 | { |
23d72bfd MM |
145 | /* Setup cause_ipi callback based on which ICP is used */ |
146 | smp_ops->cause_ipi = icp_ops->cause_ipi; | |
0b05ac6e BH |
147 | |
148 | /* Register all the IPIs */ | |
149 | xics_request_ipi(); | |
0b05ac6e BH |
150 | } |
151 | ||
152 | #endif /* CONFIG_SMP */ | |
153 | ||
154 | void xics_teardown_cpu(void) | |
155 | { | |
69111bac | 156 | struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr); |
0b05ac6e BH |
157 | |
158 | /* | |
159 | * we have to reset the cppr index to 0 because we're | |
160 | * not going to return from the IPI | |
161 | */ | |
162 | os_cppr->index = 0; | |
163 | icp_ops->set_priority(0); | |
164 | icp_ops->teardown_cpu(); | |
165 | } | |
166 | ||
167 | void xics_kexec_teardown_cpu(int secondary) | |
168 | { | |
169 | xics_teardown_cpu(); | |
170 | ||
171 | icp_ops->flush_ipi(); | |
172 | ||
173 | /* | |
174 | * Some machines need to have at least one cpu in the GIQ, | |
175 | * so leave the master cpu in the group. | |
176 | */ | |
177 | if (secondary) | |
178 | xics_set_cpu_giq(xics_default_distrib_server, 0); | |
179 | } | |
180 | ||
181 | ||
182 | #ifdef CONFIG_HOTPLUG_CPU | |
183 | ||
184 | /* Interrupts are disabled. */ | |
185 | void xics_migrate_irqs_away(void) | |
186 | { | |
187 | int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id(); | |
188 | unsigned int irq, virq; | |
4013369f | 189 | struct irq_desc *desc; |
0b05ac6e BH |
190 | |
191 | /* If we used to be the default server, move to the new "boot_cpuid" */ | |
192 | if (hw_cpu == xics_default_server) | |
193 | xics_update_irq_servers(); | |
194 | ||
195 | /* Reject any interrupt that was queued to us... */ | |
196 | icp_ops->set_priority(0); | |
197 | ||
198 | /* Remove ourselves from the global interrupt queue */ | |
199 | xics_set_cpu_giq(xics_default_distrib_server, 0); | |
200 | ||
201 | /* Allow IPIs again... */ | |
202 | icp_ops->set_priority(DEFAULT_PRIORITY); | |
203 | ||
4013369f | 204 | for_each_irq_desc(virq, desc) { |
0b05ac6e BH |
205 | struct irq_chip *chip; |
206 | long server; | |
207 | unsigned long flags; | |
208 | struct ics *ics; | |
209 | ||
210 | /* We can't set affinity on ISA interrupts */ | |
211 | if (virq < NUM_ISA_INTERRUPTS) | |
212 | continue; | |
0b05ac6e | 213 | /* We only need to migrate enabled IRQS */ |
4013369f | 214 | if (!desc->action) |
0b05ac6e | 215 | continue; |
6d9285b0 GL |
216 | if (desc->irq_data.domain != xics_host) |
217 | continue; | |
218 | irq = desc->irq_data.hwirq; | |
219 | /* We need to get IPIs still. */ | |
220 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
221 | continue; | |
0b05ac6e BH |
222 | chip = irq_desc_get_chip(desc); |
223 | if (!chip || !chip->irq_set_affinity) | |
224 | continue; | |
225 | ||
226 | raw_spin_lock_irqsave(&desc->lock, flags); | |
227 | ||
228 | /* Locate interrupt server */ | |
229 | server = -1; | |
c1231a78 | 230 | ics = irq_desc_get_chip_data(desc); |
0b05ac6e BH |
231 | if (ics) |
232 | server = ics->get_server(ics, irq); | |
233 | if (server < 0) { | |
234 | printk(KERN_ERR "%s: Can't find server for irq %d\n", | |
235 | __func__, irq); | |
236 | goto unlock; | |
237 | } | |
238 | ||
239 | /* We only support delivery to all cpus or to one cpu. | |
240 | * The irq has to be migrated only in the single cpu | |
241 | * case. | |
242 | */ | |
243 | if (server != hw_cpu) | |
244 | goto unlock; | |
245 | ||
246 | /* This is expected during cpu offline. */ | |
247 | if (cpu_online(cpu)) | |
248 | pr_warning("IRQ %u affinity broken off cpu %u\n", | |
249 | virq, cpu); | |
250 | ||
251 | /* Reset affinity to all cpus */ | |
252 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
253 | irq_set_affinity(virq, cpu_all_mask); | |
254 | continue; | |
255 | unlock: | |
256 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
257 | } | |
258 | } | |
259 | #endif /* CONFIG_HOTPLUG_CPU */ | |
260 | ||
261 | #ifdef CONFIG_SMP | |
262 | /* | |
263 | * For the moment we only implement delivery to all cpus or one cpu. | |
264 | * | |
265 | * If the requested affinity is cpu_all_mask, we set global affinity. | |
266 | * If not we set it to the first cpu in the mask, even if multiple cpus | |
267 | * are set. This is so things like irqbalance (which set core and package | |
268 | * wide affinities) do the right thing. | |
f6e17f9b BH |
269 | * |
270 | * We need to fix this to implement support for the links | |
0b05ac6e BH |
271 | */ |
272 | int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask, | |
273 | unsigned int strict_check) | |
274 | { | |
275 | ||
276 | if (!distribute_irqs) | |
277 | return xics_default_server; | |
278 | ||
279 | if (!cpumask_subset(cpu_possible_mask, cpumask)) { | |
280 | int server = cpumask_first_and(cpu_online_mask, cpumask); | |
281 | ||
282 | if (server < nr_cpu_ids) | |
283 | return get_hard_smp_processor_id(server); | |
284 | ||
285 | if (strict_check) | |
286 | return -1; | |
287 | } | |
288 | ||
289 | /* | |
290 | * Workaround issue with some versions of JS20 firmware that | |
291 | * deliver interrupts to cpus which haven't been started. This | |
292 | * happens when using the maxcpus= boot option. | |
293 | */ | |
294 | if (cpumask_equal(cpu_online_mask, cpu_present_mask)) | |
295 | return xics_default_distrib_server; | |
296 | ||
297 | return xics_default_server; | |
298 | } | |
299 | #endif /* CONFIG_SMP */ | |
300 | ||
ad3aedfb MZ |
301 | static int xics_host_match(struct irq_domain *h, struct device_node *node, |
302 | enum irq_domain_bus_token bus_token) | |
0b05ac6e | 303 | { |
5ca12376 ME |
304 | struct ics *ics; |
305 | ||
306 | list_for_each_entry(ics, &ics_list, link) | |
307 | if (ics->host_match(ics, node)) | |
308 | return 1; | |
309 | ||
310 | return 0; | |
0b05ac6e BH |
311 | } |
312 | ||
313 | /* Dummies */ | |
314 | static void xics_ipi_unmask(struct irq_data *d) { } | |
315 | static void xics_ipi_mask(struct irq_data *d) { } | |
316 | ||
317 | static struct irq_chip xics_ipi_chip = { | |
318 | .name = "XICS", | |
319 | .irq_eoi = NULL, /* Patched at init time */ | |
320 | .irq_mask = xics_ipi_mask, | |
321 | .irq_unmask = xics_ipi_unmask, | |
322 | }; | |
323 | ||
bae1d8f1 | 324 | static int xics_host_map(struct irq_domain *h, unsigned int virq, |
0b05ac6e BH |
325 | irq_hw_number_t hw) |
326 | { | |
327 | struct ics *ics; | |
328 | ||
329 | pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw); | |
330 | ||
0b05ac6e BH |
331 | /* They aren't all level sensitive but we just don't really know */ |
332 | irq_set_status_flags(virq, IRQ_LEVEL); | |
333 | ||
334 | /* Don't call into ICS for IPIs */ | |
335 | if (hw == XICS_IPI) { | |
336 | irq_set_chip_and_handler(virq, &xics_ipi_chip, | |
e085255e | 337 | handle_percpu_irq); |
0b05ac6e BH |
338 | return 0; |
339 | } | |
340 | ||
341 | /* Let the ICS setup the chip data */ | |
342 | list_for_each_entry(ics, &ics_list, link) | |
343 | if (ics->map(ics, virq) == 0) | |
e085255e MM |
344 | return 0; |
345 | ||
346 | return -EINVAL; | |
0b05ac6e BH |
347 | } |
348 | ||
bae1d8f1 | 349 | static int xics_host_xlate(struct irq_domain *h, struct device_node *ct, |
0b05ac6e BH |
350 | const u32 *intspec, unsigned int intsize, |
351 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) | |
352 | ||
353 | { | |
354 | /* Current xics implementation translates everything | |
355 | * to level. It is not technically right for MSIs but this | |
356 | * is irrelevant at this point. We might get smarter in the future | |
357 | */ | |
358 | *out_hwirq = intspec[0]; | |
359 | *out_flags = IRQ_TYPE_LEVEL_LOW; | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
202648a6 | 364 | static const struct irq_domain_ops xics_host_ops = { |
0b05ac6e BH |
365 | .match = xics_host_match, |
366 | .map = xics_host_map, | |
367 | .xlate = xics_host_xlate, | |
368 | }; | |
369 | ||
370 | static void __init xics_init_host(void) | |
371 | { | |
a8db8cf0 | 372 | xics_host = irq_domain_add_tree(NULL, &xics_host_ops, NULL); |
0b05ac6e BH |
373 | BUG_ON(xics_host == NULL); |
374 | irq_set_default_host(xics_host); | |
375 | } | |
376 | ||
377 | void __init xics_register_ics(struct ics *ics) | |
378 | { | |
379 | list_add(&ics->link, &ics_list); | |
380 | } | |
381 | ||
382 | static void __init xics_get_server_size(void) | |
383 | { | |
384 | struct device_node *np; | |
d213dd53 | 385 | const __be32 *isize; |
0b05ac6e BH |
386 | |
387 | /* We fetch the interrupt server size from the first ICS node | |
388 | * we find if any | |
389 | */ | |
390 | np = of_find_compatible_node(NULL, NULL, "ibm,ppc-xics"); | |
391 | if (!np) | |
392 | return; | |
393 | isize = of_get_property(np, "ibm,interrupt-server#-size", NULL); | |
394 | if (!isize) | |
395 | return; | |
d213dd53 | 396 | xics_interrupt_server_size = be32_to_cpu(*isize); |
0b05ac6e BH |
397 | of_node_put(np); |
398 | } | |
399 | ||
400 | void __init xics_init(void) | |
401 | { | |
402 | int rc = -1; | |
403 | ||
404 | /* Fist locate ICP */ | |
0b05ac6e BH |
405 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
406 | rc = icp_hv_init(); | |
d7436188 | 407 | if (rc < 0) { |
0b05ac6e | 408 | rc = icp_native_init(); |
d7436188 BH |
409 | if (rc == -ENODEV) |
410 | rc = icp_opal_init(); | |
411 | } | |
0b05ac6e BH |
412 | if (rc < 0) { |
413 | pr_warning("XICS: Cannot find a Presentation Controller !\n"); | |
414 | return; | |
415 | } | |
416 | ||
417 | /* Copy get_irq callback over to ppc_md */ | |
418 | ppc_md.get_irq = icp_ops->get_irq; | |
419 | ||
420 | /* Patch up IPI chip EOI */ | |
421 | xics_ipi_chip.irq_eoi = icp_ops->eoi; | |
422 | ||
423 | /* Now locate ICS */ | |
0b05ac6e | 424 | rc = ics_rtas_init(); |
5c7c1e94 BH |
425 | if (rc < 0) |
426 | rc = ics_opal_init(); | |
0b05ac6e BH |
427 | if (rc < 0) |
428 | pr_warning("XICS: Cannot find a Source Controller !\n"); | |
429 | ||
430 | /* Initialize common bits */ | |
431 | xics_get_server_size(); | |
432 | xics_update_irq_servers(); | |
433 | xics_init_host(); | |
434 | xics_setup_cpu(); | |
435 | } |