Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Ethernet driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
5 | * I copied the basic skeleton from the lance driver, because I did not | |
6 | * know how to write the Linux driver, but I did know how the LANCE worked. | |
7 | * | |
8 | * This version of the driver is somewhat selectable for the different | |
9 | * processor/board combinations. It works for the boards I know about | |
10 | * now, and should be easily modified to include others. Some of the | |
11 | * configuration information is contained in <asm/commproc.h> and the | |
12 | * remainder is here. | |
13 | * | |
14 | * Buffer descriptors are kept in the CPM dual port RAM, and the frame | |
15 | * buffers are in the host memory. | |
16 | * | |
17 | * Right now, I am very watseful with the buffers. I allocate memory | |
18 | * pages and then divide them into 2K frame buffers. This way I know I | |
19 | * have buffers large enough to hold one frame within one buffer descriptor. | |
20 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
21 | * will be much more memory efficient and will easily handle lots of | |
22 | * small packets. | |
23 | * | |
24 | */ | |
1da177e4 LT |
25 | #include <linux/kernel.h> |
26 | #include <linux/sched.h> | |
27 | #include <linux/string.h> | |
28 | #include <linux/ptrace.h> | |
29 | #include <linux/errno.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/interrupt.h> | |
1da177e4 LT |
33 | #include <linux/init.h> |
34 | #include <linux/delay.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/spinlock.h> | |
39 | #include <linux/dma-mapping.h> | |
40 | #include <linux/bitops.h> | |
41 | ||
42 | #include <asm/8xx_immap.h> | |
43 | #include <asm/pgtable.h> | |
44 | #include <asm/mpc8xx.h> | |
45 | #include <asm/uaccess.h> | |
46 | #include <asm/commproc.h> | |
47 | ||
48 | /* | |
49 | * Theory of Operation | |
50 | * | |
51 | * The MPC8xx CPM performs the Ethernet processing on SCC1. It can use | |
52 | * an aribtrary number of buffers on byte boundaries, but must have at | |
53 | * least two receive buffers to prevent constant overrun conditions. | |
54 | * | |
55 | * The buffer descriptors are allocated from the CPM dual port memory | |
56 | * with the data buffers allocated from host memory, just like all other | |
57 | * serial communication protocols. The host memory buffers are allocated | |
58 | * from the free page pool, and then divided into smaller receive and | |
59 | * transmit buffers. The size of the buffers should be a power of two, | |
60 | * since that nicely divides the page. This creates a ring buffer | |
61 | * structure similar to the LANCE and other controllers. | |
62 | * | |
63 | * Like the LANCE driver: | |
64 | * The driver runs as two independent, single-threaded flows of control. One | |
65 | * is the send-packet routine, which enforces single-threaded use by the | |
66 | * cep->tx_busy flag. The other thread is the interrupt handler, which is | |
67 | * single threaded by the hardware and other software. | |
68 | * | |
69 | * The send packet thread has partial control over the Tx ring and the | |
70 | * 'cep->tx_busy' flag. It sets the tx_busy flag whenever it's queuing a Tx | |
71 | * packet. If the next queue slot is empty, it clears the tx_busy flag when | |
72 | * finished otherwise it sets the 'lp->tx_full' flag. | |
73 | * | |
74 | * The MBX has a control register external to the MPC8xx that has some | |
75 | * control of the Ethernet interface. Information is in the manual for | |
76 | * your board. | |
77 | * | |
78 | * The RPX boards have an external control/status register. Consult the | |
79 | * programming documents for details unique to your board. | |
80 | * | |
81 | * For the TQM8xx(L) modules, there is no control register interface. | |
82 | * All functions are directly controlled using I/O pins. See <asm/commproc.h>. | |
83 | */ | |
84 | ||
85 | /* The transmitter timeout | |
86 | */ | |
87 | #define TX_TIMEOUT (2*HZ) | |
88 | ||
89 | /* The number of Tx and Rx buffers. These are allocated from the page | |
90 | * pool. The code may assume these are power of two, so it is best | |
91 | * to keep them that size. | |
92 | * We don't need to allocate pages for the transmitter. We just use | |
93 | * the skbuffer directly. | |
94 | */ | |
95 | #ifdef CONFIG_ENET_BIG_BUFFERS | |
96 | #define CPM_ENET_RX_PAGES 32 | |
97 | #define CPM_ENET_RX_FRSIZE 2048 | |
98 | #define CPM_ENET_RX_FRPPG (PAGE_SIZE / CPM_ENET_RX_FRSIZE) | |
99 | #define RX_RING_SIZE (CPM_ENET_RX_FRPPG * CPM_ENET_RX_PAGES) | |
100 | #define TX_RING_SIZE 64 /* Must be power of two */ | |
101 | #define TX_RING_MOD_MASK 63 /* for this to work */ | |
102 | #else | |
103 | #define CPM_ENET_RX_PAGES 4 | |
104 | #define CPM_ENET_RX_FRSIZE 2048 | |
105 | #define CPM_ENET_RX_FRPPG (PAGE_SIZE / CPM_ENET_RX_FRSIZE) | |
106 | #define RX_RING_SIZE (CPM_ENET_RX_FRPPG * CPM_ENET_RX_PAGES) | |
107 | #define TX_RING_SIZE 8 /* Must be power of two */ | |
108 | #define TX_RING_MOD_MASK 7 /* for this to work */ | |
109 | #endif | |
110 | ||
111 | /* The CPM stores dest/src/type, data, and checksum for receive packets. | |
112 | */ | |
113 | #define PKT_MAXBUF_SIZE 1518 | |
114 | #define PKT_MINBUF_SIZE 64 | |
115 | #define PKT_MAXBLR_SIZE 1520 | |
116 | ||
117 | /* The CPM buffer descriptors track the ring buffers. The rx_bd_base and | |
118 | * tx_bd_base always point to the base of the buffer descriptors. The | |
119 | * cur_rx and cur_tx point to the currently available buffer. | |
120 | * The dirty_tx tracks the current buffer that is being sent by the | |
121 | * controller. The cur_tx and dirty_tx are equal under both completely | |
122 | * empty and completely full conditions. The empty/ready indicator in | |
123 | * the buffer descriptor determines the actual condition. | |
124 | */ | |
125 | struct scc_enet_private { | |
126 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ | |
127 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
128 | ushort skb_cur; | |
129 | ushort skb_dirty; | |
130 | ||
131 | /* CPM dual port RAM relative addresses. | |
132 | */ | |
133 | cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ | |
134 | cbd_t *tx_bd_base; | |
135 | cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ | |
136 | cbd_t *dirty_tx; /* The ring entries to be free()ed. */ | |
137 | scc_t *sccp; | |
138 | ||
139 | /* Virtual addresses for the receive buffers because we can't | |
140 | * do a __va() on them anymore. | |
141 | */ | |
142 | unsigned char *rx_vaddr[RX_RING_SIZE]; | |
143 | struct net_device_stats stats; | |
144 | uint tx_full; | |
145 | spinlock_t lock; | |
146 | }; | |
147 | ||
148 | static int scc_enet_open(struct net_device *dev); | |
149 | static int scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
150 | static int scc_enet_rx(struct net_device *dev); | |
39e3eb72 | 151 | static void scc_enet_interrupt(void *dev_id); |
1da177e4 LT |
152 | static int scc_enet_close(struct net_device *dev); |
153 | static struct net_device_stats *scc_enet_get_stats(struct net_device *dev); | |
154 | static void set_multicast_list(struct net_device *dev); | |
155 | ||
156 | /* Get this from various configuration locations (depends on board). | |
157 | */ | |
158 | /*static ushort my_enet_addr[] = { 0x0800, 0x3e26, 0x1559 };*/ | |
159 | ||
160 | /* Typically, 860(T) boards use SCC1 for Ethernet, and other 8xx boards | |
161 | * use SCC2. Some even may use SCC3. | |
162 | * This is easily extended if necessary. | |
163 | */ | |
164 | #if defined(CONFIG_SCC3_ENET) | |
165 | #define CPM_CR_ENET CPM_CR_CH_SCC3 | |
166 | #define PROFF_ENET PROFF_SCC3 | |
167 | #define SCC_ENET 2 /* Index, not number! */ | |
168 | #define CPMVEC_ENET CPMVEC_SCC3 | |
169 | #elif defined(CONFIG_SCC2_ENET) | |
170 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
171 | #define PROFF_ENET PROFF_SCC2 | |
172 | #define SCC_ENET 1 /* Index, not number! */ | |
173 | #define CPMVEC_ENET CPMVEC_SCC2 | |
174 | #elif defined(CONFIG_SCC1_ENET) | |
175 | #define CPM_CR_ENET CPM_CR_CH_SCC1 | |
176 | #define PROFF_ENET PROFF_SCC1 | |
177 | #define SCC_ENET 0 /* Index, not number! */ | |
178 | #define CPMVEC_ENET CPMVEC_SCC1 | |
179 | #else | |
180 | #error CONFIG_SCCx_ENET not defined | |
181 | #endif | |
182 | ||
183 | static int | |
184 | scc_enet_open(struct net_device *dev) | |
185 | { | |
186 | ||
187 | /* I should reset the ring buffers here, but I don't yet know | |
188 | * a simple way to do that. | |
189 | */ | |
190 | ||
191 | netif_start_queue(dev); | |
192 | return 0; /* Always succeed */ | |
193 | } | |
194 | ||
195 | static int | |
196 | scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
197 | { | |
198 | struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv; | |
199 | volatile cbd_t *bdp; | |
200 | ||
201 | /* Fill in a Tx ring entry */ | |
202 | bdp = cep->cur_tx; | |
203 | ||
204 | #ifndef final_version | |
205 | if (bdp->cbd_sc & BD_ENET_TX_READY) { | |
206 | /* Ooops. All transmit buffers are full. Bail out. | |
207 | * This should not happen, since cep->tx_busy should be set. | |
208 | */ | |
209 | printk("%s: tx queue full!.\n", dev->name); | |
210 | return 1; | |
211 | } | |
212 | #endif | |
213 | ||
214 | /* Clear all of the status flags. | |
215 | */ | |
216 | bdp->cbd_sc &= ~BD_ENET_TX_STATS; | |
217 | ||
218 | /* If the frame is short, tell CPM to pad it. | |
219 | */ | |
220 | if (skb->len <= ETH_ZLEN) | |
221 | bdp->cbd_sc |= BD_ENET_TX_PAD; | |
222 | else | |
223 | bdp->cbd_sc &= ~BD_ENET_TX_PAD; | |
224 | ||
225 | /* Set buffer length and buffer pointer. | |
226 | */ | |
227 | bdp->cbd_datlen = skb->len; | |
228 | bdp->cbd_bufaddr = __pa(skb->data); | |
229 | ||
230 | /* Save skb pointer. | |
231 | */ | |
232 | cep->tx_skbuff[cep->skb_cur] = skb; | |
233 | ||
234 | cep->stats.tx_bytes += skb->len; | |
235 | cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK; | |
236 | ||
237 | /* Push the data cache so the CPM does not get stale memory | |
238 | * data. | |
239 | */ | |
240 | flush_dcache_range((unsigned long)(skb->data), | |
241 | (unsigned long)(skb->data + skb->len)); | |
242 | ||
243 | spin_lock_irq(&cep->lock); | |
244 | ||
245 | /* Send it on its way. Tell CPM its ready, interrupt when done, | |
246 | * its the last BD of the frame, and to put the CRC on the end. | |
247 | */ | |
248 | bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC); | |
249 | ||
250 | dev->trans_start = jiffies; | |
251 | ||
252 | /* If this was the last BD in the ring, start at the beginning again. | |
253 | */ | |
254 | if (bdp->cbd_sc & BD_ENET_TX_WRAP) | |
255 | bdp = cep->tx_bd_base; | |
256 | else | |
257 | bdp++; | |
258 | ||
259 | if (bdp->cbd_sc & BD_ENET_TX_READY) { | |
260 | netif_stop_queue(dev); | |
261 | cep->tx_full = 1; | |
262 | } | |
263 | ||
264 | cep->cur_tx = (cbd_t *)bdp; | |
265 | ||
266 | spin_unlock_irq(&cep->lock); | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
271 | static void | |
272 | scc_enet_timeout(struct net_device *dev) | |
273 | { | |
274 | struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv; | |
275 | ||
276 | printk("%s: transmit timed out.\n", dev->name); | |
277 | cep->stats.tx_errors++; | |
278 | #ifndef final_version | |
279 | { | |
280 | int i; | |
281 | cbd_t *bdp; | |
282 | printk(" Ring data dump: cur_tx %p%s cur_rx %p.\n", | |
283 | cep->cur_tx, cep->tx_full ? " (full)" : "", | |
284 | cep->cur_rx); | |
285 | bdp = cep->tx_bd_base; | |
286 | for (i = 0 ; i < TX_RING_SIZE; i++, bdp++) | |
287 | printk("%04x %04x %08x\n", | |
288 | bdp->cbd_sc, | |
289 | bdp->cbd_datlen, | |
290 | bdp->cbd_bufaddr); | |
291 | bdp = cep->rx_bd_base; | |
292 | for (i = 0 ; i < RX_RING_SIZE; i++, bdp++) | |
293 | printk("%04x %04x %08x\n", | |
294 | bdp->cbd_sc, | |
295 | bdp->cbd_datlen, | |
296 | bdp->cbd_bufaddr); | |
297 | } | |
298 | #endif | |
299 | if (!cep->tx_full) | |
300 | netif_wake_queue(dev); | |
301 | } | |
302 | ||
303 | /* The interrupt handler. | |
304 | * This is called from the CPM handler, not the MPC core interrupt. | |
305 | */ | |
306 | static void | |
39e3eb72 | 307 | scc_enet_interrupt(void *dev_id) |
1da177e4 LT |
308 | { |
309 | struct net_device *dev = dev_id; | |
310 | volatile struct scc_enet_private *cep; | |
311 | volatile cbd_t *bdp; | |
312 | ushort int_events; | |
313 | int must_restart; | |
314 | ||
315 | cep = (struct scc_enet_private *)dev->priv; | |
316 | ||
317 | /* Get the interrupt events that caused us to be here. | |
318 | */ | |
319 | int_events = cep->sccp->scc_scce; | |
320 | cep->sccp->scc_scce = int_events; | |
321 | must_restart = 0; | |
322 | ||
323 | /* Handle receive event in its own function. | |
324 | */ | |
325 | if (int_events & SCCE_ENET_RXF) | |
326 | scc_enet_rx(dev_id); | |
327 | ||
328 | /* Check for a transmit error. The manual is a little unclear | |
329 | * about this, so the debug code until I get it figured out. It | |
330 | * appears that if TXE is set, then TXB is not set. However, | |
331 | * if carrier sense is lost during frame transmission, the TXE | |
332 | * bit is set, "and continues the buffer transmission normally." | |
333 | * I don't know if "normally" implies TXB is set when the buffer | |
334 | * descriptor is closed.....trial and error :-). | |
335 | */ | |
336 | ||
337 | /* Transmit OK, or non-fatal error. Update the buffer descriptors. | |
338 | */ | |
339 | if (int_events & (SCCE_ENET_TXE | SCCE_ENET_TXB)) { | |
340 | spin_lock(&cep->lock); | |
341 | bdp = cep->dirty_tx; | |
342 | while ((bdp->cbd_sc&BD_ENET_TX_READY)==0) { | |
343 | if ((bdp==cep->cur_tx) && (cep->tx_full == 0)) | |
344 | break; | |
345 | ||
346 | if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */ | |
347 | cep->stats.tx_heartbeat_errors++; | |
348 | if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */ | |
349 | cep->stats.tx_window_errors++; | |
350 | if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */ | |
351 | cep->stats.tx_aborted_errors++; | |
352 | if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */ | |
353 | cep->stats.tx_fifo_errors++; | |
354 | if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */ | |
355 | cep->stats.tx_carrier_errors++; | |
356 | ||
357 | ||
358 | /* No heartbeat or Lost carrier are not really bad errors. | |
359 | * The others require a restart transmit command. | |
360 | */ | |
361 | if (bdp->cbd_sc & | |
362 | (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) { | |
363 | must_restart = 1; | |
364 | cep->stats.tx_errors++; | |
365 | } | |
366 | ||
367 | cep->stats.tx_packets++; | |
368 | ||
369 | /* Deferred means some collisions occurred during transmit, | |
370 | * but we eventually sent the packet OK. | |
371 | */ | |
372 | if (bdp->cbd_sc & BD_ENET_TX_DEF) | |
373 | cep->stats.collisions++; | |
374 | ||
375 | /* Free the sk buffer associated with this last transmit. | |
376 | */ | |
377 | dev_kfree_skb_irq(cep->tx_skbuff[cep->skb_dirty]); | |
378 | cep->skb_dirty = (cep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
379 | ||
380 | /* Update pointer to next buffer descriptor to be transmitted. | |
381 | */ | |
382 | if (bdp->cbd_sc & BD_ENET_TX_WRAP) | |
383 | bdp = cep->tx_bd_base; | |
384 | else | |
385 | bdp++; | |
386 | ||
387 | /* I don't know if we can be held off from processing these | |
388 | * interrupts for more than one frame time. I really hope | |
389 | * not. In such a case, we would now want to check the | |
390 | * currently available BD (cur_tx) and determine if any | |
391 | * buffers between the dirty_tx and cur_tx have also been | |
392 | * sent. We would want to process anything in between that | |
393 | * does not have BD_ENET_TX_READY set. | |
394 | */ | |
395 | ||
396 | /* Since we have freed up a buffer, the ring is no longer | |
397 | * full. | |
398 | */ | |
399 | if (cep->tx_full) { | |
400 | cep->tx_full = 0; | |
401 | if (netif_queue_stopped(dev)) | |
402 | netif_wake_queue(dev); | |
403 | } | |
404 | ||
405 | cep->dirty_tx = (cbd_t *)bdp; | |
406 | } | |
407 | ||
408 | if (must_restart) { | |
409 | volatile cpm8xx_t *cp; | |
410 | ||
411 | /* Some transmit errors cause the transmitter to shut | |
412 | * down. We now issue a restart transmit. Since the | |
413 | * errors close the BD and update the pointers, the restart | |
414 | * _should_ pick up without having to reset any of our | |
415 | * pointers either. | |
416 | */ | |
417 | cp = cpmp; | |
418 | cp->cp_cpcr = | |
419 | mk_cr_cmd(CPM_CR_ENET, CPM_CR_RESTART_TX) | CPM_CR_FLG; | |
420 | while (cp->cp_cpcr & CPM_CR_FLG); | |
421 | } | |
422 | spin_unlock(&cep->lock); | |
423 | } | |
424 | ||
425 | /* Check for receive busy, i.e. packets coming but no place to | |
426 | * put them. This "can't happen" because the receive interrupt | |
427 | * is tossing previous frames. | |
428 | */ | |
429 | if (int_events & SCCE_ENET_BSY) { | |
430 | cep->stats.rx_dropped++; | |
431 | printk("CPM ENET: BSY can't happen.\n"); | |
432 | } | |
433 | ||
434 | return; | |
435 | } | |
436 | ||
437 | /* During a receive, the cur_rx points to the current incoming buffer. | |
438 | * When we update through the ring, if the next incoming buffer has | |
439 | * not been given to the system, we just set the empty indicator, | |
440 | * effectively tossing the packet. | |
441 | */ | |
442 | static int | |
443 | scc_enet_rx(struct net_device *dev) | |
444 | { | |
445 | struct scc_enet_private *cep; | |
446 | volatile cbd_t *bdp; | |
447 | struct sk_buff *skb; | |
448 | ushort pkt_len; | |
449 | ||
450 | cep = (struct scc_enet_private *)dev->priv; | |
451 | ||
452 | /* First, grab all of the stats for the incoming packet. | |
453 | * These get messed up if we get called due to a busy condition. | |
454 | */ | |
455 | bdp = cep->cur_rx; | |
456 | ||
457 | for (;;) { | |
458 | if (bdp->cbd_sc & BD_ENET_RX_EMPTY) | |
459 | break; | |
460 | ||
461 | #ifndef final_version | |
462 | /* Since we have allocated space to hold a complete frame, both | |
463 | * the first and last indicators should be set. | |
464 | */ | |
465 | if ((bdp->cbd_sc & (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) != | |
466 | (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) | |
467 | printk("CPM ENET: rcv is not first+last\n"); | |
468 | #endif | |
469 | ||
470 | /* Frame too long or too short. | |
471 | */ | |
472 | if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) | |
473 | cep->stats.rx_length_errors++; | |
474 | if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */ | |
475 | cep->stats.rx_frame_errors++; | |
476 | if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */ | |
477 | cep->stats.rx_crc_errors++; | |
478 | if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */ | |
479 | cep->stats.rx_crc_errors++; | |
480 | ||
481 | /* Report late collisions as a frame error. | |
482 | * On this error, the BD is closed, but we don't know what we | |
483 | * have in the buffer. So, just drop this frame on the floor. | |
484 | */ | |
485 | if (bdp->cbd_sc & BD_ENET_RX_CL) { | |
486 | cep->stats.rx_frame_errors++; | |
487 | } | |
488 | else { | |
489 | ||
490 | /* Process the incoming frame. | |
491 | */ | |
492 | cep->stats.rx_packets++; | |
493 | pkt_len = bdp->cbd_datlen; | |
494 | cep->stats.rx_bytes += pkt_len; | |
495 | ||
496 | /* This does 16 byte alignment, much more than we need. | |
497 | * The packet length includes FCS, but we don't want to | |
498 | * include that when passing upstream as it messes up | |
499 | * bridging applications. | |
500 | */ | |
501 | skb = dev_alloc_skb(pkt_len-4); | |
502 | ||
503 | if (skb == NULL) { | |
504 | printk("%s: Memory squeeze, dropping packet.\n", dev->name); | |
505 | cep->stats.rx_dropped++; | |
506 | } | |
507 | else { | |
1da177e4 | 508 | skb_put(skb,pkt_len-4); /* Make room */ |
8c7b7faa | 509 | skb_copy_to_linear_data(skb, |
1da177e4 | 510 | cep->rx_vaddr[bdp - cep->rx_bd_base], |
8c7b7faa | 511 | pkt_len-4); |
1da177e4 LT |
512 | skb->protocol=eth_type_trans(skb,dev); |
513 | netif_rx(skb); | |
514 | } | |
515 | } | |
516 | ||
517 | /* Clear the status flags for this buffer. | |
518 | */ | |
519 | bdp->cbd_sc &= ~BD_ENET_RX_STATS; | |
520 | ||
521 | /* Mark the buffer empty. | |
522 | */ | |
523 | bdp->cbd_sc |= BD_ENET_RX_EMPTY; | |
524 | ||
525 | /* Update BD pointer to next entry. | |
526 | */ | |
527 | if (bdp->cbd_sc & BD_ENET_RX_WRAP) | |
528 | bdp = cep->rx_bd_base; | |
529 | else | |
530 | bdp++; | |
531 | ||
532 | } | |
533 | cep->cur_rx = (cbd_t *)bdp; | |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
538 | static int | |
539 | scc_enet_close(struct net_device *dev) | |
540 | { | |
541 | /* Don't know what to do yet. | |
542 | */ | |
543 | netif_stop_queue(dev); | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
548 | static struct net_device_stats *scc_enet_get_stats(struct net_device *dev) | |
549 | { | |
550 | struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv; | |
551 | ||
552 | return &cep->stats; | |
553 | } | |
554 | ||
555 | /* Set or clear the multicast filter for this adaptor. | |
556 | * Skeleton taken from sunlance driver. | |
557 | * The CPM Ethernet implementation allows Multicast as well as individual | |
558 | * MAC address filtering. Some of the drivers check to make sure it is | |
559 | * a group multicast address, and discard those that are not. I guess I | |
560 | * will do the same for now, but just remove the test if you want | |
561 | * individual filtering as well (do the upper net layers want or support | |
562 | * this kind of feature?). | |
563 | */ | |
564 | ||
565 | static void set_multicast_list(struct net_device *dev) | |
566 | { | |
567 | struct scc_enet_private *cep; | |
568 | struct dev_mc_list *dmi; | |
569 | u_char *mcptr, *tdptr; | |
570 | volatile scc_enet_t *ep; | |
571 | int i, j; | |
572 | cep = (struct scc_enet_private *)dev->priv; | |
573 | ||
574 | /* Get pointer to SCC area in parameter RAM. | |
575 | */ | |
576 | ep = (scc_enet_t *)dev->base_addr; | |
577 | ||
578 | if (dev->flags&IFF_PROMISC) { | |
579 | ||
580 | /* Log any net taps. */ | |
581 | printk("%s: Promiscuous mode enabled.\n", dev->name); | |
582 | cep->sccp->scc_psmr |= SCC_PSMR_PRO; | |
583 | } else { | |
584 | ||
585 | cep->sccp->scc_psmr &= ~SCC_PSMR_PRO; | |
586 | ||
587 | if (dev->flags & IFF_ALLMULTI) { | |
588 | /* Catch all multicast addresses, so set the | |
589 | * filter to all 1's. | |
590 | */ | |
591 | ep->sen_gaddr1 = 0xffff; | |
592 | ep->sen_gaddr2 = 0xffff; | |
593 | ep->sen_gaddr3 = 0xffff; | |
594 | ep->sen_gaddr4 = 0xffff; | |
595 | } | |
596 | else { | |
597 | /* Clear filter and add the addresses in the list. | |
598 | */ | |
599 | ep->sen_gaddr1 = 0; | |
600 | ep->sen_gaddr2 = 0; | |
601 | ep->sen_gaddr3 = 0; | |
602 | ep->sen_gaddr4 = 0; | |
603 | ||
604 | dmi = dev->mc_list; | |
605 | ||
606 | for (i=0; i<dev->mc_count; i++) { | |
607 | ||
608 | /* Only support group multicast for now. | |
609 | */ | |
610 | if (!(dmi->dmi_addr[0] & 1)) | |
611 | continue; | |
612 | ||
613 | /* The address in dmi_addr is LSB first, | |
614 | * and taddr is MSB first. We have to | |
615 | * copy bytes MSB first from dmi_addr. | |
616 | */ | |
617 | mcptr = (u_char *)dmi->dmi_addr + 5; | |
618 | tdptr = (u_char *)&ep->sen_taddrh; | |
619 | for (j=0; j<6; j++) | |
620 | *tdptr++ = *mcptr--; | |
621 | ||
622 | /* Ask CPM to run CRC and set bit in | |
623 | * filter mask. | |
624 | */ | |
625 | cpmp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_SET_GADDR) | CPM_CR_FLG; | |
626 | /* this delay is necessary here -- Cort */ | |
627 | udelay(10); | |
628 | while (cpmp->cp_cpcr & CPM_CR_FLG); | |
629 | } | |
630 | } | |
631 | } | |
632 | } | |
633 | ||
634 | /* Initialize the CPM Ethernet on SCC. If EPPC-Bug loaded us, or performed | |
635 | * some other network I/O, a whole bunch of this has already been set up. | |
636 | * It is no big deal if we do it again, we just have to disable the | |
637 | * transmit and receive to make sure we don't catch the CPM with some | |
638 | * inconsistent control information. | |
639 | */ | |
640 | static int __init scc_enet_init(void) | |
641 | { | |
642 | struct net_device *dev; | |
643 | struct scc_enet_private *cep; | |
644 | int i, j, k, err; | |
645 | uint dp_offset; | |
646 | unsigned char *eap, *ba; | |
647 | dma_addr_t mem_addr; | |
648 | bd_t *bd; | |
649 | volatile cbd_t *bdp; | |
650 | volatile cpm8xx_t *cp; | |
651 | volatile scc_t *sccp; | |
652 | volatile scc_enet_t *ep; | |
653 | volatile immap_t *immap; | |
654 | ||
655 | cp = cpmp; /* Get pointer to Communication Processor */ | |
656 | ||
657 | immap = (immap_t *)(mfspr(SPRN_IMMR) & 0xFFFF0000); /* and to internal registers */ | |
658 | ||
659 | bd = (bd_t *)__res; | |
660 | ||
661 | dev = alloc_etherdev(sizeof(*cep)); | |
662 | if (!dev) | |
663 | return -ENOMEM; | |
664 | ||
665 | cep = dev->priv; | |
666 | spin_lock_init(&cep->lock); | |
667 | ||
668 | /* Get pointer to SCC area in parameter RAM. | |
669 | */ | |
670 | ep = (scc_enet_t *)(&cp->cp_dparam[PROFF_ENET]); | |
671 | ||
672 | /* And another to the SCC register area. | |
673 | */ | |
674 | sccp = (volatile scc_t *)(&cp->cp_scc[SCC_ENET]); | |
675 | cep->sccp = (scc_t *)sccp; /* Keep the pointer handy */ | |
676 | ||
677 | /* Disable receive and transmit in case EPPC-Bug started it. | |
678 | */ | |
679 | sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
680 | ||
681 | /* Cookbook style from the MPC860 manual..... | |
682 | * Not all of this is necessary if EPPC-Bug has initialized | |
683 | * the network. | |
684 | * So far we are lucky, all board configurations use the same | |
685 | * pins, or at least the same I/O Port for these functions..... | |
686 | * It can't last though...... | |
687 | */ | |
688 | ||
689 | #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD)) | |
690 | /* Configure port A pins for Txd and Rxd. | |
691 | */ | |
692 | immap->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD); | |
693 | immap->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD); | |
694 | immap->im_ioport.iop_paodr &= ~PA_ENET_TXD; | |
695 | #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD)) | |
696 | /* Configure port B pins for Txd and Rxd. | |
697 | */ | |
698 | immap->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD); | |
699 | immap->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD); | |
700 | immap->im_cpm.cp_pbodr &= ~PB_ENET_TXD; | |
701 | #else | |
702 | #error Exactly ONE pair of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined | |
703 | #endif | |
704 | ||
705 | #if defined(PC_ENET_LBK) | |
706 | /* Configure port C pins to disable External Loopback | |
707 | */ | |
708 | immap->im_ioport.iop_pcpar &= ~PC_ENET_LBK; | |
709 | immap->im_ioport.iop_pcdir |= PC_ENET_LBK; | |
710 | immap->im_ioport.iop_pcso &= ~PC_ENET_LBK; | |
711 | immap->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */ | |
712 | #endif /* PC_ENET_LBK */ | |
713 | ||
e6b6239f AK |
714 | #ifdef PE_ENET_TCLK |
715 | /* Configure port E for TCLK and RCLK. | |
1da177e4 | 716 | */ |
e6b6239f AK |
717 | cp->cp_pepar |= (PE_ENET_TCLK | PE_ENET_RCLK); |
718 | cp->cp_pedir &= ~(PE_ENET_TCLK | PE_ENET_RCLK); | |
719 | cp->cp_peso &= ~(PE_ENET_TCLK | PE_ENET_RCLK); | |
720 | #else | |
1da177e4 LT |
721 | /* Configure port A for TCLK and RCLK. |
722 | */ | |
723 | immap->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK); | |
724 | immap->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK); | |
e6b6239f AK |
725 | #endif |
726 | ||
727 | /* Configure port C pins to enable CLSN and RENA. | |
728 | */ | |
729 | immap->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA); | |
730 | immap->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA); | |
731 | immap->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); | |
1da177e4 LT |
732 | |
733 | /* Configure Serial Interface clock routing. | |
734 | * First, clear all SCC bits to zero, then set the ones we want. | |
735 | */ | |
736 | cp->cp_sicr &= ~SICR_ENET_MASK; | |
737 | cp->cp_sicr |= SICR_ENET_CLKRT; | |
738 | ||
739 | /* Manual says set SDDR, but I can't find anything with that | |
740 | * name. I think it is a misprint, and should be SDCR. This | |
741 | * has already been set by the communication processor initialization. | |
742 | */ | |
743 | ||
744 | /* Allocate space for the buffer descriptors in the DP ram. | |
745 | * These are relative offsets in the DP ram address space. | |
746 | * Initialize base addresses for the buffer descriptors. | |
747 | */ | |
748 | dp_offset = cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8); | |
749 | ep->sen_genscc.scc_rbase = dp_offset; | |
750 | cep->rx_bd_base = cpm_dpram_addr(dp_offset); | |
751 | ||
752 | dp_offset = cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8); | |
753 | ep->sen_genscc.scc_tbase = dp_offset; | |
754 | cep->tx_bd_base = cpm_dpram_addr(dp_offset); | |
755 | ||
756 | cep->dirty_tx = cep->cur_tx = cep->tx_bd_base; | |
757 | cep->cur_rx = cep->rx_bd_base; | |
758 | ||
759 | /* Issue init Rx BD command for SCC. | |
760 | * Manual says to perform an Init Rx parameters here. We have | |
761 | * to perform both Rx and Tx because the SCC may have been | |
762 | * already running. | |
763 | * In addition, we have to do it later because we don't yet have | |
764 | * all of the BD control/status set properly. | |
765 | cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_INIT_RX) | CPM_CR_FLG; | |
766 | while (cp->cp_cpcr & CPM_CR_FLG); | |
767 | */ | |
768 | ||
769 | /* Initialize function code registers for big-endian. | |
770 | */ | |
771 | ep->sen_genscc.scc_rfcr = SCC_EB; | |
772 | ep->sen_genscc.scc_tfcr = SCC_EB; | |
773 | ||
774 | /* Set maximum bytes per receive buffer. | |
775 | * This appears to be an Ethernet frame size, not the buffer | |
776 | * fragment size. It must be a multiple of four. | |
777 | */ | |
778 | ep->sen_genscc.scc_mrblr = PKT_MAXBLR_SIZE; | |
779 | ||
780 | /* Set CRC preset and mask. | |
781 | */ | |
782 | ep->sen_cpres = 0xffffffff; | |
783 | ep->sen_cmask = 0xdebb20e3; | |
784 | ||
785 | ep->sen_crcec = 0; /* CRC Error counter */ | |
786 | ep->sen_alec = 0; /* alignment error counter */ | |
787 | ep->sen_disfc = 0; /* discard frame counter */ | |
788 | ||
789 | ep->sen_pads = 0x8888; /* Tx short frame pad character */ | |
790 | ep->sen_retlim = 15; /* Retry limit threshold */ | |
791 | ||
792 | ep->sen_maxflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ | |
793 | ep->sen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */ | |
794 | ||
795 | ep->sen_maxd1 = PKT_MAXBLR_SIZE; /* maximum DMA1 length */ | |
796 | ep->sen_maxd2 = PKT_MAXBLR_SIZE; /* maximum DMA2 length */ | |
797 | ||
798 | /* Clear hash tables. | |
799 | */ | |
800 | ep->sen_gaddr1 = 0; | |
801 | ep->sen_gaddr2 = 0; | |
802 | ep->sen_gaddr3 = 0; | |
803 | ep->sen_gaddr4 = 0; | |
804 | ep->sen_iaddr1 = 0; | |
805 | ep->sen_iaddr2 = 0; | |
806 | ep->sen_iaddr3 = 0; | |
807 | ep->sen_iaddr4 = 0; | |
808 | ||
809 | /* Set Ethernet station address. | |
810 | */ | |
811 | eap = (unsigned char *)&(ep->sen_paddrh); | |
812 | for (i=5; i>=0; i--) | |
813 | *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i]; | |
814 | ||
815 | ep->sen_pper = 0; /* 'cause the book says so */ | |
816 | ep->sen_taddrl = 0; /* temp address (LSB) */ | |
817 | ep->sen_taddrm = 0; | |
818 | ep->sen_taddrh = 0; /* temp address (MSB) */ | |
819 | ||
820 | /* Now allocate the host memory pages and initialize the | |
821 | * buffer descriptors. | |
822 | */ | |
823 | bdp = cep->tx_bd_base; | |
824 | for (i=0; i<TX_RING_SIZE; i++) { | |
825 | ||
826 | /* Initialize the BD for every fragment in the page. | |
827 | */ | |
828 | bdp->cbd_sc = 0; | |
829 | bdp->cbd_bufaddr = 0; | |
830 | bdp++; | |
831 | } | |
832 | ||
833 | /* Set the last buffer to wrap. | |
834 | */ | |
835 | bdp--; | |
836 | bdp->cbd_sc |= BD_SC_WRAP; | |
837 | ||
838 | bdp = cep->rx_bd_base; | |
839 | k = 0; | |
840 | for (i=0; i<CPM_ENET_RX_PAGES; i++) { | |
841 | ||
842 | /* Allocate a page. | |
843 | */ | |
844 | ba = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, | |
845 | &mem_addr, GFP_KERNEL); | |
846 | /* BUG: no check for failure */ | |
847 | ||
848 | /* Initialize the BD for every fragment in the page. | |
849 | */ | |
850 | for (j=0; j<CPM_ENET_RX_FRPPG; j++) { | |
851 | bdp->cbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR; | |
852 | bdp->cbd_bufaddr = mem_addr; | |
853 | cep->rx_vaddr[k++] = ba; | |
854 | mem_addr += CPM_ENET_RX_FRSIZE; | |
855 | ba += CPM_ENET_RX_FRSIZE; | |
856 | bdp++; | |
857 | } | |
858 | } | |
859 | ||
860 | /* Set the last buffer to wrap. | |
861 | */ | |
862 | bdp--; | |
863 | bdp->cbd_sc |= BD_SC_WRAP; | |
864 | ||
865 | /* Let's re-initialize the channel now. We have to do it later | |
866 | * than the manual describes because we have just now finished | |
867 | * the BD initialization. | |
868 | */ | |
869 | cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_INIT_TRX) | CPM_CR_FLG; | |
870 | while (cp->cp_cpcr & CPM_CR_FLG); | |
871 | ||
872 | cep->skb_cur = cep->skb_dirty = 0; | |
873 | ||
874 | sccp->scc_scce = 0xffff; /* Clear any pending events */ | |
875 | ||
876 | /* Enable interrupts for transmit error, complete frame | |
877 | * received, and any transmit buffer we have also set the | |
878 | * interrupt flag. | |
879 | */ | |
880 | sccp->scc_sccm = (SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB); | |
881 | ||
882 | /* Install our interrupt handler. | |
883 | */ | |
884 | cpm_install_handler(CPMVEC_ENET, scc_enet_interrupt, dev); | |
885 | ||
886 | /* Set GSMR_H to enable all normal operating modes. | |
887 | * Set GSMR_L to enable Ethernet to MC68160. | |
888 | */ | |
889 | sccp->scc_gsmrh = 0; | |
890 | sccp->scc_gsmrl = (SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 | SCC_GSMRL_MODE_ENET); | |
891 | ||
892 | /* Set sync/delimiters. | |
893 | */ | |
894 | sccp->scc_dsr = 0xd555; | |
895 | ||
896 | /* Set processing mode. Use Ethernet CRC, catch broadcast, and | |
897 | * start frame search 22 bit times after RENA. | |
898 | */ | |
899 | sccp->scc_psmr = (SCC_PSMR_ENCRC | SCC_PSMR_NIB22); | |
900 | ||
901 | /* It is now OK to enable the Ethernet transmitter. | |
902 | * Unfortunately, there are board implementation differences here. | |
903 | */ | |
e6b6239f | 904 | #if (!defined (PB_ENET_TENA) && defined (PC_ENET_TENA) && !defined (PE_ENET_TENA)) |
1da177e4 LT |
905 | immap->im_ioport.iop_pcpar |= PC_ENET_TENA; |
906 | immap->im_ioport.iop_pcdir &= ~PC_ENET_TENA; | |
e6b6239f | 907 | #elif ( defined (PB_ENET_TENA) && !defined (PC_ENET_TENA) && !defined (PE_ENET_TENA)) |
1da177e4 LT |
908 | cp->cp_pbpar |= PB_ENET_TENA; |
909 | cp->cp_pbdir |= PB_ENET_TENA; | |
e6b6239f AK |
910 | #elif ( !defined (PB_ENET_TENA) && !defined (PC_ENET_TENA) && defined (PE_ENET_TENA)) |
911 | cp->cp_pepar |= PE_ENET_TENA; | |
912 | cp->cp_pedir &= ~PE_ENET_TENA; | |
913 | cp->cp_peso |= PE_ENET_TENA; | |
1da177e4 | 914 | #else |
e6b6239f | 915 | #error Configuration Error: define exactly ONE of PB_ENET_TENA, PC_ENET_TENA, PE_ENET_TENA |
1da177e4 LT |
916 | #endif |
917 | ||
918 | #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) | |
919 | /* And while we are here, set the configuration to enable ethernet. | |
920 | */ | |
921 | *((volatile uint *)RPX_CSR_ADDR) &= ~BCSR0_ETHLPBK; | |
922 | *((volatile uint *)RPX_CSR_ADDR) |= | |
923 | (BCSR0_ETHEN | BCSR0_COLTESTDIS | BCSR0_FULLDPLXDIS); | |
924 | #endif | |
925 | ||
926 | #ifdef CONFIG_BSEIP | |
927 | /* BSE uses port B and C for PHY control. | |
928 | */ | |
929 | cp->cp_pbpar &= ~(PB_BSE_POWERUP | PB_BSE_FDXDIS); | |
930 | cp->cp_pbdir |= (PB_BSE_POWERUP | PB_BSE_FDXDIS); | |
931 | cp->cp_pbdat |= (PB_BSE_POWERUP | PB_BSE_FDXDIS); | |
932 | ||
933 | immap->im_ioport.iop_pcpar &= ~PC_BSE_LOOPBACK; | |
934 | immap->im_ioport.iop_pcdir |= PC_BSE_LOOPBACK; | |
935 | immap->im_ioport.iop_pcso &= ~PC_BSE_LOOPBACK; | |
936 | immap->im_ioport.iop_pcdat &= ~PC_BSE_LOOPBACK; | |
937 | #endif | |
938 | ||
939 | #ifdef CONFIG_FADS | |
940 | cp->cp_pbpar |= PB_ENET_TENA; | |
941 | cp->cp_pbdir |= PB_ENET_TENA; | |
942 | ||
943 | /* Enable the EEST PHY. | |
944 | */ | |
945 | *((volatile uint *)BCSR1) &= ~BCSR1_ETHEN; | |
946 | #endif | |
947 | ||
e6b6239f AK |
948 | #ifdef CONFIG_MPC885ADS |
949 | ||
950 | /* Deassert PHY reset and enable the PHY. | |
951 | */ | |
952 | { | |
953 | volatile uint __iomem *bcsr = ioremap(BCSR_ADDR, BCSR_SIZE); | |
954 | uint tmp; | |
955 | ||
956 | tmp = in_be32(bcsr + 1 /* BCSR1 */); | |
957 | tmp |= BCSR1_ETHEN; | |
958 | out_be32(bcsr + 1, tmp); | |
959 | tmp = in_be32(bcsr + 4 /* BCSR4 */); | |
960 | tmp |= BCSR4_ETH10_RST; | |
961 | out_be32(bcsr + 4, tmp); | |
962 | iounmap(bcsr); | |
963 | } | |
964 | ||
965 | /* On MPC885ADS SCC ethernet PHY defaults to the full duplex mode | |
966 | * upon reset. SCC is set to half duplex by default. So this | |
967 | * inconsistency should be better fixed by the software. | |
968 | */ | |
969 | #endif | |
970 | ||
1da177e4 LT |
971 | dev->base_addr = (unsigned long)ep; |
972 | #if 0 | |
973 | dev->name = "CPM_ENET"; | |
974 | #endif | |
975 | ||
976 | /* The CPM Ethernet specific entries in the device structure. */ | |
977 | dev->open = scc_enet_open; | |
978 | dev->hard_start_xmit = scc_enet_start_xmit; | |
979 | dev->tx_timeout = scc_enet_timeout; | |
980 | dev->watchdog_timeo = TX_TIMEOUT; | |
981 | dev->stop = scc_enet_close; | |
982 | dev->get_stats = scc_enet_get_stats; | |
983 | dev->set_multicast_list = set_multicast_list; | |
984 | ||
985 | err = register_netdev(dev); | |
986 | if (err) { | |
987 | free_netdev(dev); | |
988 | return err; | |
989 | } | |
990 | ||
991 | /* And last, enable the transmit and receive processing. | |
992 | */ | |
993 | sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
994 | ||
995 | printk("%s: CPM ENET Version 0.2 on SCC%d, ", dev->name, SCC_ENET+1); | |
996 | for (i=0; i<5; i++) | |
997 | printk("%02x:", dev->dev_addr[i]); | |
998 | printk("%02x\n", dev->dev_addr[5]); | |
999 | ||
1000 | return 0; | |
1001 | } | |
1002 | ||
1003 | module_init(scc_enet_init); | |
e6b6239f | 1004 |