[deliverable/linux.git] / arch / ppc / boot / simple / mv64x60_tty.c

/*
 * Bootloader version of the embedded MPSC/UART driver for the Marvell 64x60.
 * Note: Due to a GT64260A erratum, DMA will be used for UART input (via SDMA).
 *
 * Author: Mark A. Greer <mgreer@mvista.com>
 *
 * 2001 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

/* This code assumes that the data cache has been disabled (L1, L2, L3). */

#include <linux/config.h>
#include <linux/types.h>
#include <linux/serial_reg.h>
#include <asm/serial.h>
#include <asm/io.h>
#include <asm/mv64x60_defs.h>
#include <mpsc_defs.h>

#ifdef CONFIG_EV64360
#include <platforms/ev64360.h>
u32	mv64x60_console_baud = EV64360_DEFAULT_BAUD;
u32	mv64x60_mpsc_clk_src = EV64360_MPSC_CLK_SRC; /* TCLK */
u32	mv64x60_mpsc_clk_freq = EV64360_MPSC_CLK_FREQ;
#else
u32	mv64x60_console_baud = 9600;
u32	mv64x60_mpsc_clk_src = 8; /* TCLK */
u32	mv64x60_mpsc_clk_freq = 100000000;
#endif

extern void udelay(long);
static void stop_dma(int chan);

static void __iomem *mv64x60_base = (void __iomem *)CONFIG_MV64X60_NEW_BASE;

struct sdma_regs {
	u32	sdc;
	u32	sdcm;
	u32	rx_desc;
	u32	rx_buf_ptr;
	u32	scrdp;
	u32	tx_desc;
	u32	sctdp;
	u32	sftdp;
};

static struct sdma_regs	sdma_regs[2];

#define	SDMA_REGS_INIT(s, reg_base) {			\
	(s)->sdc	= (reg_base) + SDMA_SDC;	\
	(s)->sdcm	= (reg_base) + SDMA_SDCM;	\
	(s)->rx_desc	= (reg_base) + SDMA_RX_DESC;	\
	(s)->rx_buf_ptr = (reg_base) + SDMA_RX_BUF_PTR;	\
	(s)->scrdp	= (reg_base) + SDMA_SCRDP;	\
	(s)->tx_desc	= (reg_base) + SDMA_TX_DESC;	\
	(s)->sctdp	= (reg_base) + SDMA_SCTDP;	\
	(s)->sftdp	= (reg_base) + SDMA_SFTDP;	\
}

static u32	mpsc_base[2] = { MV64x60_MPSC_0_OFFSET, MV64x60_MPSC_1_OFFSET };

struct mv64x60_rx_desc {
	u16	bufsize;
	u16	bytecnt;
	u32	cmd_stat;
	u32	next_desc_ptr;
	u32	buffer;
};

struct mv64x60_tx_desc {
	u16	bytecnt;
	u16	shadow;
	u32	cmd_stat;
	u32	next_desc_ptr;
	u32	buffer;
};

#define	MAX_RESET_WAIT	10000
#define	MAX_TX_WAIT	10000

#define	RX_NUM_DESC	2
#define	TX_NUM_DESC	2

#define	RX_BUF_SIZE	32
#define	TX_BUF_SIZE	32

static struct mv64x60_rx_desc rd[2][RX_NUM_DESC] __attribute__ ((aligned(32)));
static struct mv64x60_tx_desc td[2][TX_NUM_DESC] __attribute__ ((aligned(32)));

static char rx_buf[2][RX_NUM_DESC * RX_BUF_SIZE] __attribute__ ((aligned(32)));
static char tx_buf[2][TX_NUM_DESC * TX_BUF_SIZE] __attribute__ ((aligned(32)));

static int cur_rd[2] = { 0, 0 };
static int cur_td[2] = { 0, 0 };

static char chan_initialized[2] = { 0, 0 };


#define	RX_INIT_RDP(rdp) {			\
	(rdp)->bufsize = 2;			\
	(rdp)->bytecnt = 0;			\
	(rdp)->cmd_stat = SDMA_DESC_CMDSTAT_L | SDMA_DESC_CMDSTAT_F |	\
		SDMA_DESC_CMDSTAT_O;	\
}

#ifdef CONFIG_MV64360
static u32 cpu2mem_tab[MV64x60_CPU2MEM_WINDOWS][2] = {
		{ MV64x60_CPU2MEM_0_BASE, MV64x60_CPU2MEM_0_SIZE },
		{ MV64x60_CPU2MEM_1_BASE, MV64x60_CPU2MEM_1_SIZE },
		{ MV64x60_CPU2MEM_2_BASE, MV64x60_CPU2MEM_2_SIZE },
		{ MV64x60_CPU2MEM_3_BASE, MV64x60_CPU2MEM_3_SIZE }
};

static u32 com2mem_tab[MV64x60_CPU2MEM_WINDOWS][2] = {
		{ MV64360_MPSC2MEM_0_BASE, MV64360_MPSC2MEM_0_SIZE },
		{ MV64360_MPSC2MEM_1_BASE, MV64360_MPSC2MEM_1_SIZE },
		{ MV64360_MPSC2MEM_2_BASE, MV64360_MPSC2MEM_2_SIZE },
		{ MV64360_MPSC2MEM_3_BASE, MV64360_MPSC2MEM_3_SIZE }
};

static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] = { 0xe, 0xd, 0xb, 0x7 };
#endif

unsigned long
serial_init(int chan, void *ignored)
{
	u32		mpsc_routing_base, sdma_base, brg_bcr, cdv;
	int		i;

	chan = (chan == 1); /* default to chan 0 if anything but 1 */

	if (chan_initialized[chan])
		return chan;

	chan_initialized[chan] = 1;

	if (chan == 0) {
		sdma_base = MV64x60_SDMA_0_OFFSET;
		brg_bcr = MV64x60_BRG_0_OFFSET + BRG_BCR;
		SDMA_REGS_INIT(&sdma_regs[0], MV64x60_SDMA_0_OFFSET);
	} else {
		sdma_base = MV64x60_SDMA_1_OFFSET;
		brg_bcr = MV64x60_BRG_1_OFFSET + BRG_BCR;
		SDMA_REGS_INIT(&sdma_regs[0], MV64x60_SDMA_1_OFFSET);
	}

	mpsc_routing_base = MV64x60_MPSC_ROUTING_OFFSET;

	stop_dma(chan);

	/* Set up ring buffers */
	for (i=0; i<RX_NUM_DESC; i++) {
		RX_INIT_RDP(&rd[chan][i]);
		rd[chan][i].buffer = (u32)&rx_buf[chan][i * RX_BUF_SIZE];
		rd[chan][i].next_desc_ptr = (u32)&rd[chan][i+1];
	}
	rd[chan][RX_NUM_DESC - 1].next_desc_ptr = (u32)&rd[chan][0];

	for (i=0; i<TX_NUM_DESC; i++) {
		td[chan][i].bytecnt = 0;
		td[chan][i].shadow = 0;
		td[chan][i].buffer = (u32)&tx_buf[chan][i * TX_BUF_SIZE];
		td[chan][i].cmd_stat = SDMA_DESC_CMDSTAT_F|SDMA_DESC_CMDSTAT_L;
		td[chan][i].next_desc_ptr = (u32)&td[chan][i+1];
	}
	td[chan][TX_NUM_DESC - 1].next_desc_ptr = (u32)&td[chan][0];

	/* Set MPSC Routing */
	out_le32(mv64x60_base + mpsc_routing_base + MPSC_MRR, 0x3ffffe38);

#ifdef CONFIG_GT64260
	out_le32(mv64x60_base + GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
#else /* Must be MV64360 or MV64460 */
	{
	u32	enables, prot_bits, v;

	/* Set up comm unit to memory mapping windows */
	/* Note: Assumes MV64x60_CPU2MEM_WINDOWS == 4 */

	enables = in_le32(mv64x60_base + MV64360_CPU_BAR_ENABLE) & 0xf;
	prot_bits = 0;

	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
		if (!(enables & (1 << i))) {
			v = in_le32(mv64x60_base + cpu2mem_tab[i][0]);
			v = ((v & 0xffff) << 16) | (dram_selects[i] << 8);
			out_le32(mv64x60_base + com2mem_tab[i][0], v);

			v = in_le32(mv64x60_base + cpu2mem_tab[i][1]);
			v = (v & 0xffff) << 16;
			out_le32(mv64x60_base + com2mem_tab[i][1], v);

			prot_bits |= (0x3 << (i << 1)); /* r/w access */
		}
	}

	out_le32(mv64x60_base + MV64360_MPSC_0_REMAP, 0);
	out_le32(mv64x60_base + MV64360_MPSC_1_REMAP, 0);
	out_le32(mv64x60_base + MV64360_MPSC2MEM_ACC_PROT_0, prot_bits);
	out_le32(mv64x60_base + MV64360_MPSC2MEM_ACC_PROT_1, prot_bits);
	out_le32(mv64x60_base + MV64360_MPSC2MEM_BAR_ENABLE, enables);
	}
#endif

	/* MPSC 0/1 Rx & Tx get clocks BRG0/1 */
	out_le32(mv64x60_base + mpsc_routing_base + MPSC_RCRR, 0x00000100);
	out_le32(mv64x60_base + mpsc_routing_base + MPSC_TCRR, 0x00000100);

	/* clear pending interrupts */
	out_le32(mv64x60_base + MV64x60_SDMA_INTR_OFFSET + SDMA_INTR_MASK, 0);

	out_le32(mv64x60_base + SDMA_SCRDP + sdma_base, (int)&rd[chan][0]);
	out_le32(mv64x60_base + SDMA_SCTDP + sdma_base,
		(int)&td[chan][TX_NUM_DESC - 1]);
	out_le32(mv64x60_base + SDMA_SFTDP + sdma_base,
		(int)&td[chan][TX_NUM_DESC - 1]);

	out_le32(mv64x60_base + SDMA_SDC + sdma_base,
		SDMA_SDC_RFT | SDMA_SDC_SFM | SDMA_SDC_BLMR | SDMA_SDC_BLMT |
		(3 << 12));

	cdv = ((mv64x60_mpsc_clk_freq/(32*mv64x60_console_baud))-1);
	out_le32(mv64x60_base + brg_bcr,
		((mv64x60_mpsc_clk_src << 18) | (1 << 16) | cdv));

	/* Put MPSC into UART mode, no null modem, 16x clock mode */
	out_le32(mv64x60_base + MPSC_MMCRL + mpsc_base[chan], 0x000004c4);
	out_le32(mv64x60_base + MPSC_MMCRH + mpsc_base[chan], 0x04400400);

	out_le32(mv64x60_base + MPSC_CHR_1 + mpsc_base[chan], 0);
	out_le32(mv64x60_base + MPSC_CHR_9 + mpsc_base[chan], 0);
	out_le32(mv64x60_base + MPSC_CHR_10 + mpsc_base[chan], 0);
	out_le32(mv64x60_base + MPSC_CHR_3 + mpsc_base[chan], 4);
	out_le32(mv64x60_base + MPSC_CHR_4 + mpsc_base[chan], 0);
	out_le32(mv64x60_base + MPSC_CHR_5 + mpsc_base[chan], 0);
	out_le32(mv64x60_base + MPSC_CHR_6 + mpsc_base[chan], 0);
	out_le32(mv64x60_base + MPSC_CHR_7 + mpsc_base[chan], 0);
	out_le32(mv64x60_base + MPSC_CHR_8 + mpsc_base[chan], 0);

	/* 8 data bits, 1 stop bit */
	out_le32(mv64x60_base + MPSC_MPCR + mpsc_base[chan], (3 << 12));
	out_le32(mv64x60_base + SDMA_SDCM + sdma_base, SDMA_SDCM_ERD);
	out_le32(mv64x60_base + MPSC_CHR_2 + mpsc_base[chan], MPSC_CHR_2_EH);

	udelay(100);

	return chan;
}

static void
stop_dma(int chan)
{
	int	i;

	/* Abort MPSC Rx (aborting Tx messes things up) */
	out_le32(mv64x60_base + MPSC_CHR_2 + mpsc_base[chan], MPSC_CHR_2_RA);

	/* Abort SDMA Rx, Tx */
	out_le32(mv64x60_base + sdma_regs[chan].sdcm,
		SDMA_SDCM_AR | SDMA_SDCM_STD);

	for (i=0; i<MAX_RESET_WAIT; i++) {
		if ((in_le32(mv64x60_base + sdma_regs[chan].sdcm) &
				(SDMA_SDCM_AR | SDMA_SDCM_AT)) == 0)
			break;

		udelay(100);
	}
}

static int
wait_for_ownership(int chan)
{
	int	i;

	for (i=0; i<MAX_TX_WAIT; i++) {
		if ((in_le32(mv64x60_base + sdma_regs[chan].sdcm) &
				SDMA_SDCM_TXD) == 0)
			break;

		udelay(1000);
	}

	return (i < MAX_TX_WAIT);
}

void
serial_putc(unsigned long com_port, unsigned char c)
{
	struct mv64x60_tx_desc	*tdp;

	if (wait_for_ownership(com_port) == 0)
		return;

	tdp = &td[com_port][cur_td[com_port]];
	if (++cur_td[com_port] >= TX_NUM_DESC)
		cur_td[com_port] = 0;

	*(unchar *)(tdp->buffer ^ 7) = c;
	tdp->bytecnt = 1;
	tdp->shadow = 1;
	tdp->cmd_stat = SDMA_DESC_CMDSTAT_L | SDMA_DESC_CMDSTAT_F |
		SDMA_DESC_CMDSTAT_O;

	out_le32(mv64x60_base + sdma_regs[com_port].sctdp, (int)tdp);
	out_le32(mv64x60_base + sdma_regs[com_port].sftdp, (int)tdp);
	out_le32(mv64x60_base + sdma_regs[com_port].sdcm,
		in_le32(mv64x60_base + sdma_regs[com_port].sdcm) |
			SDMA_SDCM_TXD);
}

unsigned char
serial_getc(unsigned long com_port)
{
	struct mv64x60_rx_desc	*rdp;
	unchar			c = '\0';

	rdp = &rd[com_port][cur_rd[com_port]];

	if ((rdp->cmd_stat & (SDMA_DESC_CMDSTAT_O|SDMA_DESC_CMDSTAT_ES)) == 0) {
		c = *(unchar *)(rdp->buffer ^ 7);
		RX_INIT_RDP(rdp);
		if (++cur_rd[com_port] >= RX_NUM_DESC)
			cur_rd[com_port] = 0;
	}

	return c;
}

int
serial_tstc(unsigned long com_port)
{
	struct mv64x60_rx_desc	*rdp;
	int			loop_count = 0;
	int			rc = 0;

	rdp = &rd[com_port][cur_rd[com_port]];

	/* Go thru rcv desc's until empty looking for one with data (no error)*/
	while (((rdp->cmd_stat & SDMA_DESC_CMDSTAT_O) == 0) &&
		(loop_count++ < RX_NUM_DESC)) {

		/* If there was an error, reinit the desc & continue */
		if ((rdp->cmd_stat & SDMA_DESC_CMDSTAT_ES) != 0) {
			RX_INIT_RDP(rdp);
			if (++cur_rd[com_port] >= RX_NUM_DESC)
				cur_rd[com_port] = 0;
			rdp = (struct mv64x60_rx_desc *)rdp->next_desc_ptr;
		} else {
			rc = 1;
			break;
		}
	}

	return rc;
}

void
serial_close(unsigned long com_port)
{
	stop_dma(com_port);
}
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Bootloader version of the embedded MPSC/UART driver for the Marvell 64x60.
	3	* Note: Due to a GT64260A erratum, DMA will be used for UART input (via SDMA).
	4	*
	5	* Author: Mark A. Greer <mgreer@mvista.com>
	6	*
	7	* 2001 (c) MontaVista Software, Inc. This file is licensed under
	8	* the terms of the GNU General Public License version 2. This program
	9	* is licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*/
	12
	13	/* This code assumes that the data cache has been disabled (L1, L2, L3). */
	14
	15	#include <linux/config.h>
	16	#include <linux/types.h>
	17	#include <linux/serial_reg.h>
	18	#include <asm/serial.h>
	19	#include <asm/io.h>
	20	#include <asm/mv64x60_defs.h>
	21	#include <mpsc_defs.h>
	22
3acb2344 LN	23	#ifdef CONFIG_EV64360
	24	#include <platforms/ev64360.h>
	25	u32 mv64x60_console_baud = EV64360_DEFAULT_BAUD;
	26	u32 mv64x60_mpsc_clk_src = EV64360_MPSC_CLK_SRC; /* TCLK */
	27	u32 mv64x60_mpsc_clk_freq = EV64360_MPSC_CLK_FREQ;
	28	#else
1da177e4 LT	29	u32 mv64x60_console_baud = 9600;
	30	u32 mv64x60_mpsc_clk_src = 8; /* TCLK */
	31	u32 mv64x60_mpsc_clk_freq = 100000000;
3acb2344	32	#endif
1da177e4 LT	33
	34	extern void udelay(long);
	35	static void stop_dma(int chan);
	36
	37	static void __iomem mv64x60_base = (void __iomem )CONFIG_MV64X60_NEW_BASE;
	38
	39	struct sdma_regs {
	40	u32 sdc;
	41	u32 sdcm;
	42	u32 rx_desc;
	43	u32 rx_buf_ptr;
	44	u32 scrdp;
	45	u32 tx_desc;
	46	u32 sctdp;
	47	u32 sftdp;
	48	};
	49
	50	static struct sdma_regs sdma_regs[2];
	51
	52	#define SDMA_REGS_INIT(s, reg_base) { \
	53	(s)->sdc = (reg_base) + SDMA_SDC; \
	54	(s)->sdcm = (reg_base) + SDMA_SDCM; \
	55	(s)->rx_desc = (reg_base) + SDMA_RX_DESC; \
	56	(s)->rx_buf_ptr = (reg_base) + SDMA_RX_BUF_PTR; \
	57	(s)->scrdp = (reg_base) + SDMA_SCRDP; \
	58	(s)->tx_desc = (reg_base) + SDMA_TX_DESC; \
	59	(s)->sctdp = (reg_base) + SDMA_SCTDP; \
	60	(s)->sftdp = (reg_base) + SDMA_SFTDP; \
	61	}
	62
	63	static u32 mpsc_base[2] = { MV64x60_MPSC_0_OFFSET, MV64x60_MPSC_1_OFFSET };
	64
	65	struct mv64x60_rx_desc {
	66	u16 bufsize;
	67	u16 bytecnt;
	68	u32 cmd_stat;
	69	u32 next_desc_ptr;
	70	u32 buffer;
	71	};
	72
	73	struct mv64x60_tx_desc {
	74	u16 bytecnt;
	75	u16 shadow;
	76	u32 cmd_stat;
	77	u32 next_desc_ptr;
	78	u32 buffer;
	79	};
	80
	81	#define MAX_RESET_WAIT 10000
	82	#define MAX_TX_WAIT 10000
	83
	84	#define RX_NUM_DESC 2
	85	#define TX_NUM_DESC 2
	86
	87	#define RX_BUF_SIZE 32
	88	#define TX_BUF_SIZE 32
	89
	90	static struct mv64x60_rx_desc rd[2][RX_NUM_DESC] __attribute__ ((aligned(32)));
	91	static struct mv64x60_tx_desc td[2][TX_NUM_DESC] __attribute__ ((aligned(32)));
	92
	93	static char rx_buf[2][RX_NUM_DESC * RX_BUF_SIZE] __attribute__ ((aligned(32)));
	94	static char tx_buf[2][TX_NUM_DESC * TX_BUF_SIZE] __attribute__ ((aligned(32)));
	95
	96	static int cur_rd[2] = { 0, 0 };
97	static int cur_td[2] = { 0, 0 };
98
99	static char chan_initialized[2] = { 0, 0 };
100
101
102	#define RX_INIT_RDP(rdp) { \
103	(rdp)->bufsize = 2; \
104	(rdp)->bytecnt = 0; \
105	(rdp)->cmd_stat = SDMA_DESC_CMDSTAT_L \| SDMA_DESC_CMDSTAT_F \| \
106	SDMA_DESC_CMDSTAT_O; \
107	}
108
109	#ifdef CONFIG_MV64360
110	static u32 cpu2mem_tab[MV64x60_CPU2MEM_WINDOWS][2] = {
111	{ MV64x60_CPU2MEM_0_BASE, MV64x60_CPU2MEM_0_SIZE },
112	{ MV64x60_CPU2MEM_1_BASE, MV64x60_CPU2MEM_1_SIZE },
113	{ MV64x60_CPU2MEM_2_BASE, MV64x60_CPU2MEM_2_SIZE },
114	{ MV64x60_CPU2MEM_3_BASE, MV64x60_CPU2MEM_3_SIZE }
115	};
116
117	static u32 com2mem_tab[MV64x60_CPU2MEM_WINDOWS][2] = {
118	{ MV64360_MPSC2MEM_0_BASE, MV64360_MPSC2MEM_0_SIZE },
119	{ MV64360_MPSC2MEM_1_BASE, MV64360_MPSC2MEM_1_SIZE },
120	{ MV64360_MPSC2MEM_2_BASE, MV64360_MPSC2MEM_2_SIZE },
121	{ MV64360_MPSC2MEM_3_BASE, MV64360_MPSC2MEM_3_SIZE }
122	};
123
124	static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] = { 0xe, 0xd, 0xb, 0x7 };
125	#endif
126
127	unsigned long
128	serial_init(int chan, void *ignored)
129	{
130	u32 mpsc_routing_base, sdma_base, brg_bcr, cdv;
131	int i;
132
133	chan = (chan == 1); /* default to chan 0 if anything but 1 */
134
135	if (chan_initialized[chan])
136	return chan;
137
138	chan_initialized[chan] = 1;
139
140	if (chan == 0) {
141	sdma_base = MV64x60_SDMA_0_OFFSET;
142	brg_bcr = MV64x60_BRG_0_OFFSET + BRG_BCR;
143	SDMA_REGS_INIT(&sdma_regs[0], MV64x60_SDMA_0_OFFSET);
144	} else {
145	sdma_base = MV64x60_SDMA_1_OFFSET;
146	brg_bcr = MV64x60_BRG_1_OFFSET + BRG_BCR;
147	SDMA_REGS_INIT(&sdma_regs[0], MV64x60_SDMA_1_OFFSET);
148	}
149
150	mpsc_routing_base = MV64x60_MPSC_ROUTING_OFFSET;
151
152	stop_dma(chan);
153
154	/* Set up ring buffers */
155	for (i=0; i<RX_NUM_DESC; i++) {
156	RX_INIT_RDP(&rd[chan][i]);
157	rd[chan][i].buffer = (u32)&rx_buf[chan][i * RX_BUF_SIZE];
158	rd[chan][i].next_desc_ptr = (u32)&rd[chan][i+1];
159	}
160	rd[chan][RX_NUM_DESC - 1].next_desc_ptr = (u32)&rd[chan][0];
161
162	for (i=0; i<TX_NUM_DESC; i++) {
163	td[chan][i].bytecnt = 0;
164	td[chan][i].shadow = 0;
165	td[chan][i].buffer = (u32)&tx_buf[chan][i * TX_BUF_SIZE];
166	td[chan][i].cmd_stat = SDMA_DESC_CMDSTAT_F\|SDMA_DESC_CMDSTAT_L;
167	td[chan][i].next_desc_ptr = (u32)&td[chan][i+1];
168	}
169	td[chan][TX_NUM_DESC - 1].next_desc_ptr = (u32)&td[chan][0];
170
171	/* Set MPSC Routing */
172	out_le32(mv64x60_base + mpsc_routing_base + MPSC_MRR, 0x3ffffe38);
173
174	#ifdef CONFIG_GT64260
175	out_le32(mv64x60_base + GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
176	#else /* Must be MV64360 or MV64460 */
177	{
178	u32 enables, prot_bits, v;
179
180	/* Set up comm unit to memory mapping windows */
181	/* Note: Assumes MV64x60_CPU2MEM_WINDOWS == 4 */
182
183	enables = in_le32(mv64x60_base + MV64360_CPU_BAR_ENABLE) & 0xf;
184	prot_bits = 0;
185
186	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
187	if (!(enables & (1 << i))) {
188	v = in_le32(mv64x60_base + cpu2mem_tab[i][0]);
189	v = ((v & 0xffff) << 16) \| (dram_selects[i] << 8);
190	out_le32(mv64x60_base + com2mem_tab[i][0], v);
191
192	v = in_le32(mv64x60_base + cpu2mem_tab[i][1]);
193	v = (v & 0xffff) << 16;
194	out_le32(mv64x60_base + com2mem_tab[i][1], v);
195
196	prot_bits \|= (0x3 << (i << 1)); /* r/w access */
197	}
198	}
199
200	out_le32(mv64x60_base + MV64360_MPSC_0_REMAP, 0);
201	out_le32(mv64x60_base + MV64360_MPSC_1_REMAP, 0);
202	out_le32(mv64x60_base + MV64360_MPSC2MEM_ACC_PROT_0, prot_bits);
203	out_le32(mv64x60_base + MV64360_MPSC2MEM_ACC_PROT_1, prot_bits);
204	out_le32(mv64x60_base + MV64360_MPSC2MEM_BAR_ENABLE, enables);
205	}
206	#endif
207
208	/* MPSC 0/1 Rx & Tx get clocks BRG0/1 */
209	out_le32(mv64x60_base + mpsc_routing_base + MPSC_RCRR, 0x00000100);
210	out_le32(mv64x60_base + mpsc_routing_base + MPSC_TCRR, 0x00000100);
211
212	/* clear pending interrupts */
213	out_le32(mv64x60_base + MV64x60_SDMA_INTR_OFFSET + SDMA_INTR_MASK, 0);
214
215	out_le32(mv64x60_base + SDMA_SCRDP + sdma_base, (int)&rd[chan][0]);
216	out_le32(mv64x60_base + SDMA_SCTDP + sdma_base,
217	(int)&td[chan][TX_NUM_DESC - 1]);
218	out_le32(mv64x60_base + SDMA_SFTDP + sdma_base,
219	(int)&td[chan][TX_NUM_DESC - 1]);
220
221	out_le32(mv64x60_base + SDMA_SDC + sdma_base,
222	SDMA_SDC_RFT \| SDMA_SDC_SFM \| SDMA_SDC_BLMR \| SDMA_SDC_BLMT \|
223	(3 << 12));
224
225	cdv = ((mv64x60_mpsc_clk_freq/(32*mv64x60_console_baud))-1);
226	out_le32(mv64x60_base + brg_bcr,
227	((mv64x60_mpsc_clk_src << 18) \| (1 << 16) \| cdv));
228
229	/* Put MPSC into UART mode, no null modem, 16x clock mode */
230	out_le32(mv64x60_base + MPSC_MMCRL + mpsc_base[chan], 0x000004c4);
231	out_le32(mv64x60_base + MPSC_MMCRH + mpsc_base[chan], 0x04400400);
232
233	out_le32(mv64x60_base + MPSC_CHR_1 + mpsc_base[chan], 0);
234	out_le32(mv64x60_base + MPSC_CHR_9 + mpsc_base[chan], 0);
235	out_le32(mv64x60_base + MPSC_CHR_10 + mpsc_base[chan], 0);
236	out_le32(mv64x60_base + MPSC_CHR_3 + mpsc_base[chan], 4);
237	out_le32(mv64x60_base + MPSC_CHR_4 + mpsc_base[chan], 0);
238	out_le32(mv64x60_base + MPSC_CHR_5 + mpsc_base[chan], 0);
239	out_le32(mv64x60_base + MPSC_CHR_6 + mpsc_base[chan], 0);
240	out_le32(mv64x60_base + MPSC_CHR_7 + mpsc_base[chan], 0);
241	out_le32(mv64x60_base + MPSC_CHR_8 + mpsc_base[chan], 0);
242
243	/* 8 data bits, 1 stop bit */
244	out_le32(mv64x60_base + MPSC_MPCR + mpsc_base[chan], (3 << 12));
245	out_le32(mv64x60_base + SDMA_SDCM + sdma_base, SDMA_SDCM_ERD);
246	out_le32(mv64x60_base + MPSC_CHR_2 + mpsc_base[chan], MPSC_CHR_2_EH);
247
248	udelay(100);
249
250	return chan;
251	}
252
253	static void
254	stop_dma(int chan)
255	{
256	int i;
257
258	/* Abort MPSC Rx (aborting Tx messes things up) */
259	out_le32(mv64x60_base + MPSC_CHR_2 + mpsc_base[chan], MPSC_CHR_2_RA);
260
261	/* Abort SDMA Rx, Tx */
262	out_le32(mv64x60_base + sdma_regs[chan].sdcm,
263	SDMA_SDCM_AR \| SDMA_SDCM_STD);
264
265	for (i=0; i<MAX_RESET_WAIT; i++) {
266	if ((in_le32(mv64x60_base + sdma_regs[chan].sdcm) &
267	(SDMA_SDCM_AR \| SDMA_SDCM_AT)) == 0)
268	break;
269
270	udelay(100);
271	}
272	}
273
274	static int
275	wait_for_ownership(int chan)
276	{
277	int i;
278
279	for (i=0; i<MAX_TX_WAIT; i++) {
280	if ((in_le32(mv64x60_base + sdma_regs[chan].sdcm) &
281	SDMA_SDCM_TXD) == 0)
282	break;
283
284	udelay(1000);
285	}
286
287	return (i < MAX_TX_WAIT);
288	}
289
290	void
291	serial_putc(unsigned long com_port, unsigned char c)
292	{
293	struct mv64x60_tx_desc *tdp;
294
295	if (wait_for_ownership(com_port) == 0)
296	return;
297
298	tdp = &td[com_port][cur_td[com_port]];
299	if (++cur_td[com_port] >= TX_NUM_DESC)
300	cur_td[com_port] = 0;
301
302	(unchar )(tdp->buffer ^ 7) = c;
303	tdp->bytecnt = 1;
304	tdp->shadow = 1;
305	tdp->cmd_stat = SDMA_DESC_CMDSTAT_L \| SDMA_DESC_CMDSTAT_F \|
306	SDMA_DESC_CMDSTAT_O;
307
308	out_le32(mv64x60_base + sdma_regs[com_port].sctdp, (int)tdp);
309	out_le32(mv64x60_base + sdma_regs[com_port].sftdp, (int)tdp);
310	out_le32(mv64x60_base + sdma_regs[com_port].sdcm,
311	in_le32(mv64x60_base + sdma_regs[com_port].sdcm) \|
312	SDMA_SDCM_TXD);
313	}
314
315	unsigned char
316	serial_getc(unsigned long com_port)
317	{
318	struct mv64x60_rx_desc *rdp;
319	unchar c = '\0';
320
321	rdp = &rd[com_port][cur_rd[com_port]];
322
323	if ((rdp->cmd_stat & (SDMA_DESC_CMDSTAT_O\|SDMA_DESC_CMDSTAT_ES)) == 0) {
324	c = (unchar )(rdp->buffer ^ 7);
325	RX_INIT_RDP(rdp);
326	if (++cur_rd[com_port] >= RX_NUM_DESC)
327	cur_rd[com_port] = 0;
328	}
329
330	return c;
331	}
332
333	int
334	serial_tstc(unsigned long com_port)
335	{
336	struct mv64x60_rx_desc *rdp;
337	int loop_count = 0;
338	int rc = 0;
339
340	rdp = &rd[com_port][cur_rd[com_port]];
341
342	/* Go thru rcv desc's until empty looking for one with data (no error)*/
343	while (((rdp->cmd_stat & SDMA_DESC_CMDSTAT_O) == 0) &&
344	(loop_count++ < RX_NUM_DESC)) {
345
346	/* If there was an error, reinit the desc & continue */
347	if ((rdp->cmd_stat & SDMA_DESC_CMDSTAT_ES) != 0) {
348	RX_INIT_RDP(rdp);
349	if (++cur_rd[com_port] >= RX_NUM_DESC)
350	cur_rd[com_port] = 0;
351	rdp = (struct mv64x60_rx_desc *)rdp->next_desc_ptr;
352	} else {
353	rc = 1;
354	break;
355	}
356	}
357
358	return rc;
359	}
360
361	void
362	serial_close(unsigned long com_port)
363	{
364	stop_dma(com_port);
365	}