Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file contains low level CPU setup functions. | |
3 | * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org) | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | * | |
10 | */ | |
11 | ||
12 | #include <linux/config.h> | |
13 | #include <asm/processor.h> | |
14 | #include <asm/page.h> | |
1da177e4 LT |
15 | #include <asm/cputable.h> |
16 | #include <asm/ppc_asm.h> | |
0013a854 | 17 | #include <asm/asm-offsets.h> |
1da177e4 LT |
18 | #include <asm/cache.h> |
19 | ||
20 | _GLOBAL(__setup_cpu_601) | |
21 | blr | |
22 | _GLOBAL(__setup_cpu_603) | |
23 | b setup_common_caches | |
24 | _GLOBAL(__setup_cpu_604) | |
25 | mflr r4 | |
26 | bl setup_common_caches | |
27 | bl setup_604_hid0 | |
28 | mtlr r4 | |
29 | blr | |
30 | _GLOBAL(__setup_cpu_750) | |
31 | mflr r4 | |
f1c55dea | 32 | bl __init_fpu_registers |
1da177e4 LT |
33 | bl setup_common_caches |
34 | bl setup_750_7400_hid0 | |
35 | mtlr r4 | |
36 | blr | |
37 | _GLOBAL(__setup_cpu_750cx) | |
38 | mflr r4 | |
f1c55dea | 39 | bl __init_fpu_registers |
1da177e4 LT |
40 | bl setup_common_caches |
41 | bl setup_750_7400_hid0 | |
42 | bl setup_750cx | |
43 | mtlr r4 | |
44 | blr | |
45 | _GLOBAL(__setup_cpu_750fx) | |
46 | mflr r4 | |
f1c55dea | 47 | bl __init_fpu_registers |
1da177e4 LT |
48 | bl setup_common_caches |
49 | bl setup_750_7400_hid0 | |
50 | bl setup_750fx | |
51 | mtlr r4 | |
52 | blr | |
53 | _GLOBAL(__setup_cpu_7400) | |
54 | mflr r4 | |
f1c55dea | 55 | bl __init_fpu_registers |
1da177e4 LT |
56 | bl setup_7400_workarounds |
57 | bl setup_common_caches | |
58 | bl setup_750_7400_hid0 | |
59 | mtlr r4 | |
60 | blr | |
61 | _GLOBAL(__setup_cpu_7410) | |
62 | mflr r4 | |
f1c55dea | 63 | bl __init_fpu_registers |
1da177e4 LT |
64 | bl setup_7410_workarounds |
65 | bl setup_common_caches | |
66 | bl setup_750_7400_hid0 | |
67 | li r3,0 | |
68 | mtspr SPRN_L2CR2,r3 | |
69 | mtlr r4 | |
70 | blr | |
71 | _GLOBAL(__setup_cpu_745x) | |
72 | mflr r4 | |
73 | bl setup_common_caches | |
74 | bl setup_745x_specifics | |
75 | mtlr r4 | |
76 | blr | |
77 | ||
78 | /* Enable caches for 603's, 604, 750 & 7400 */ | |
79 | setup_common_caches: | |
80 | mfspr r11,SPRN_HID0 | |
81 | andi. r0,r11,HID0_DCE | |
82 | ori r11,r11,HID0_ICE|HID0_DCE | |
83 | ori r8,r11,HID0_ICFI | |
84 | bne 1f /* don't invalidate the D-cache */ | |
85 | ori r8,r8,HID0_DCI /* unless it wasn't enabled */ | |
86 | 1: sync | |
f1c55dea | 87 | mtspr SPRN_HID0,r8 /* enable and invalidate caches */ |
1da177e4 LT |
88 | sync |
89 | mtspr SPRN_HID0,r11 /* enable caches */ | |
90 | sync | |
91 | isync | |
92 | blr | |
93 | ||
94 | /* 604, 604e, 604ev, ... | |
95 | * Enable superscalar execution & branch history table | |
96 | */ | |
97 | setup_604_hid0: | |
98 | mfspr r11,SPRN_HID0 | |
99 | ori r11,r11,HID0_SIED|HID0_BHTE | |
100 | ori r8,r11,HID0_BTCD | |
101 | sync | |
102 | mtspr SPRN_HID0,r8 /* flush branch target address cache */ | |
103 | sync /* on 604e/604r */ | |
104 | mtspr SPRN_HID0,r11 | |
105 | sync | |
106 | isync | |
107 | blr | |
108 | ||
109 | /* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some | |
110 | * erratas we work around here. | |
111 | * Moto MPC710CE.pdf describes them, those are errata | |
112 | * #3, #4 and #5 | |
113 | * Note that we assume the firmware didn't choose to | |
114 | * apply other workarounds (there are other ones documented | |
115 | * in the .pdf). It appear that Apple firmware only works | |
116 | * around #3 and with the same fix we use. We may want to | |
117 | * check if the CPU is using 60x bus mode in which case | |
118 | * the workaround for errata #4 is useless. Also, we may | |
119 | * want to explicitely clear HID0_NOPDST as this is not | |
120 | * needed once we have applied workaround #5 (though it's | |
121 | * not set by Apple's firmware at least). | |
122 | */ | |
123 | setup_7400_workarounds: | |
124 | mfpvr r3 | |
125 | rlwinm r3,r3,0,20,31 | |
126 | cmpwi 0,r3,0x0207 | |
127 | ble 1f | |
128 | blr | |
129 | setup_7410_workarounds: | |
130 | mfpvr r3 | |
131 | rlwinm r3,r3,0,20,31 | |
132 | cmpwi 0,r3,0x0100 | |
133 | bnelr | |
134 | 1: | |
135 | mfspr r11,SPRN_MSSSR0 | |
136 | /* Errata #3: Set L1OPQ_SIZE to 0x10 */ | |
137 | rlwinm r11,r11,0,9,6 | |
138 | oris r11,r11,0x0100 | |
139 | /* Errata #4: Set L2MQ_SIZE to 1 (check for MPX mode first ?) */ | |
140 | oris r11,r11,0x0002 | |
141 | /* Errata #5: Set DRLT_SIZE to 0x01 */ | |
142 | rlwinm r11,r11,0,5,2 | |
143 | oris r11,r11,0x0800 | |
144 | sync | |
145 | mtspr SPRN_MSSSR0,r11 | |
146 | sync | |
147 | isync | |
148 | blr | |
149 | ||
150 | /* 740/750/7400/7410 | |
151 | * Enable Store Gathering (SGE), Address Brodcast (ABE), | |
152 | * Branch History Table (BHTE), Branch Target ICache (BTIC) | |
153 | * Dynamic Power Management (DPM), Speculative (SPD) | |
154 | * Clear Instruction cache throttling (ICTC) | |
155 | */ | |
156 | setup_750_7400_hid0: | |
157 | mfspr r11,SPRN_HID0 | |
158 | ori r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC | |
f1c55dea | 159 | oris r11,r11,HID0_DPM@h |
1da177e4 | 160 | BEGIN_FTR_SECTION |
f1c55dea BH |
161 | xori r11,r11,HID0_BTIC |
162 | END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC) | |
163 | BEGIN_FTR_SECTION | |
164 | xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */ | |
165 | END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM) | |
1da177e4 LT |
166 | li r3,HID0_SPD |
167 | andc r11,r11,r3 /* clear SPD: enable speculative */ | |
168 | li r3,0 | |
169 | mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */ | |
170 | isync | |
171 | mtspr SPRN_HID0,r11 | |
172 | sync | |
173 | isync | |
174 | blr | |
175 | ||
176 | /* 750cx specific | |
177 | * Looks like we have to disable NAP feature for some PLL settings... | |
178 | * (waiting for confirmation) | |
179 | */ | |
180 | setup_750cx: | |
181 | mfspr r10, SPRN_HID1 | |
182 | rlwinm r10,r10,4,28,31 | |
183 | cmpwi cr0,r10,7 | |
184 | cmpwi cr1,r10,9 | |
185 | cmpwi cr2,r10,11 | |
186 | cror 4*cr0+eq,4*cr0+eq,4*cr1+eq | |
187 | cror 4*cr0+eq,4*cr0+eq,4*cr2+eq | |
188 | bnelr | |
189 | lwz r6,CPU_SPEC_FEATURES(r5) | |
190 | li r7,CPU_FTR_CAN_NAP | |
191 | andc r6,r6,r7 | |
192 | stw r6,CPU_SPEC_FEATURES(r5) | |
193 | blr | |
194 | ||
195 | /* 750fx specific | |
196 | */ | |
197 | setup_750fx: | |
198 | blr | |
199 | ||
200 | /* MPC 745x | |
201 | * Enable Store Gathering (SGE), Branch Folding (FOLD) | |
202 | * Branch History Table (BHTE), Branch Target ICache (BTIC) | |
203 | * Dynamic Power Management (DPM), Speculative (SPD) | |
204 | * Ensure our data cache instructions really operate. | |
205 | * Timebase has to be running or we wouldn't have made it here, | |
206 | * just ensure we don't disable it. | |
207 | * Clear Instruction cache throttling (ICTC) | |
208 | * Enable L2 HW prefetch | |
209 | */ | |
210 | setup_745x_specifics: | |
211 | /* We check for the presence of an L3 cache setup by | |
212 | * the firmware. If any, we disable NAP capability as | |
213 | * it's known to be bogus on rev 2.1 and earlier | |
214 | */ | |
215 | mfspr r11,SPRN_L3CR | |
216 | andis. r11,r11,L3CR_L3E@h | |
217 | beq 1f | |
218 | lwz r6,CPU_SPEC_FEATURES(r5) | |
219 | andi. r0,r6,CPU_FTR_L3_DISABLE_NAP | |
220 | beq 1f | |
221 | li r7,CPU_FTR_CAN_NAP | |
222 | andc r6,r6,r7 | |
223 | stw r6,CPU_SPEC_FEATURES(r5) | |
224 | 1: | |
225 | mfspr r11,SPRN_HID0 | |
226 | ||
227 | /* All of the bits we have to set..... | |
228 | */ | |
f1c55dea BH |
229 | ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE |
230 | ori r11,r11,HID0_LRSTK | HID0_BTIC | |
231 | oris r11,r11,HID0_DPM@h | |
1da177e4 LT |
232 | BEGIN_FTR_SECTION |
233 | xori r11,r11,HID0_BTIC | |
234 | END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC) | |
235 | BEGIN_FTR_SECTION | |
f1c55dea BH |
236 | xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */ |
237 | END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM) | |
1da177e4 LT |
238 | |
239 | /* All of the bits we have to clear.... | |
240 | */ | |
241 | li r3,HID0_SPD | HID0_NOPDST | HID0_NOPTI | |
242 | andc r11,r11,r3 /* clear SPD: enable speculative */ | |
243 | li r3,0 | |
244 | ||
245 | mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */ | |
246 | isync | |
247 | mtspr SPRN_HID0,r11 | |
248 | sync | |
249 | isync | |
250 | ||
80ac2912 | 251 | /* Enable L2 HW prefetch, if L2 is enabled |
1da177e4 | 252 | */ |
80ac2912 KG |
253 | mfspr r3,SPRN_L2CR |
254 | andis. r3,r3,L2CR_L2E@h | |
255 | beqlr | |
1da177e4 LT |
256 | mfspr r3,SPRN_MSSCR0 |
257 | ori r3,r3,3 | |
258 | sync | |
259 | mtspr SPRN_MSSCR0,r3 | |
260 | sync | |
261 | isync | |
262 | blr | |
263 | ||
f1c55dea BH |
264 | /* |
265 | * Initialize the FPU registers. This is needed to work around an errata | |
266 | * in some 750 cpus where using a not yet initialized FPU register after | |
267 | * power on reset may hang the CPU | |
268 | */ | |
269 | _GLOBAL(__init_fpu_registers) | |
270 | mfmsr r10 | |
271 | ori r11,r10,MSR_FP | |
272 | mtmsr r11 | |
273 | isync | |
274 | addis r9,r3,empty_zero_page@ha | |
275 | addi r9,r9,empty_zero_page@l | |
276 | REST_32FPRS(0,r9) | |
277 | sync | |
278 | mtmsr r10 | |
279 | isync | |
280 | blr | |
281 | ||
282 | ||
1da177e4 LT |
283 | /* Definitions for the table use to save CPU states */ |
284 | #define CS_HID0 0 | |
285 | #define CS_HID1 4 | |
286 | #define CS_HID2 8 | |
287 | #define CS_MSSCR0 12 | |
288 | #define CS_MSSSR0 16 | |
289 | #define CS_ICTRL 20 | |
290 | #define CS_LDSTCR 24 | |
291 | #define CS_LDSTDB 28 | |
292 | #define CS_SIZE 32 | |
293 | ||
294 | .data | |
295 | .balign L1_CACHE_LINE_SIZE | |
296 | cpu_state_storage: | |
297 | .space CS_SIZE | |
298 | .balign L1_CACHE_LINE_SIZE,0 | |
299 | .text | |
300 | ||
301 | /* Called in normal context to backup CPU 0 state. This | |
302 | * does not include cache settings. This function is also | |
303 | * called for machine sleep. This does not include the MMU | |
304 | * setup, BATs, etc... but rather the "special" registers | |
305 | * like HID0, HID1, MSSCR0, etc... | |
306 | */ | |
307 | _GLOBAL(__save_cpu_setup) | |
308 | /* Some CR fields are volatile, we back it up all */ | |
309 | mfcr r7 | |
310 | ||
311 | /* Get storage ptr */ | |
312 | lis r5,cpu_state_storage@h | |
313 | ori r5,r5,cpu_state_storage@l | |
314 | ||
315 | /* Save HID0 (common to all CONFIG_6xx cpus) */ | |
316 | mfspr r3,SPRN_HID0 | |
317 | stw r3,CS_HID0(r5) | |
318 | ||
319 | /* Now deal with CPU type dependent registers */ | |
320 | mfspr r3,SPRN_PVR | |
321 | srwi r3,r3,16 | |
322 | cmplwi cr0,r3,0x8000 /* 7450 */ | |
323 | cmplwi cr1,r3,0x000c /* 7400 */ | |
324 | cmplwi cr2,r3,0x800c /* 7410 */ | |
325 | cmplwi cr3,r3,0x8001 /* 7455 */ | |
326 | cmplwi cr4,r3,0x8002 /* 7457 */ | |
327 | cmplwi cr5,r3,0x8003 /* 7447A */ | |
328 | cmplwi cr6,r3,0x7000 /* 750FX */ | |
bbde630b | 329 | cmplwi cr7,r3,0x8004 /* 7448 */ |
1da177e4 LT |
330 | /* cr1 is 7400 || 7410 */ |
331 | cror 4*cr1+eq,4*cr1+eq,4*cr2+eq | |
332 | /* cr0 is 74xx */ | |
333 | cror 4*cr0+eq,4*cr0+eq,4*cr3+eq | |
334 | cror 4*cr0+eq,4*cr0+eq,4*cr4+eq | |
335 | cror 4*cr0+eq,4*cr0+eq,4*cr1+eq | |
336 | cror 4*cr0+eq,4*cr0+eq,4*cr5+eq | |
bbde630b | 337 | cror 4*cr0+eq,4*cr0+eq,4*cr7+eq |
1da177e4 LT |
338 | bne 1f |
339 | /* Backup 74xx specific regs */ | |
340 | mfspr r4,SPRN_MSSCR0 | |
341 | stw r4,CS_MSSCR0(r5) | |
342 | mfspr r4,SPRN_MSSSR0 | |
343 | stw r4,CS_MSSSR0(r5) | |
344 | beq cr1,1f | |
345 | /* Backup 745x specific registers */ | |
346 | mfspr r4,SPRN_HID1 | |
347 | stw r4,CS_HID1(r5) | |
348 | mfspr r4,SPRN_ICTRL | |
349 | stw r4,CS_ICTRL(r5) | |
350 | mfspr r4,SPRN_LDSTCR | |
351 | stw r4,CS_LDSTCR(r5) | |
352 | mfspr r4,SPRN_LDSTDB | |
353 | stw r4,CS_LDSTDB(r5) | |
354 | 1: | |
355 | bne cr6,1f | |
356 | /* Backup 750FX specific registers */ | |
357 | mfspr r4,SPRN_HID1 | |
358 | stw r4,CS_HID1(r5) | |
359 | /* If rev 2.x, backup HID2 */ | |
360 | mfspr r3,SPRN_PVR | |
361 | andi. r3,r3,0xff00 | |
362 | cmpwi cr0,r3,0x0200 | |
363 | bne 1f | |
364 | mfspr r4,SPRN_HID2 | |
365 | stw r4,CS_HID2(r5) | |
366 | 1: | |
367 | mtcr r7 | |
368 | blr | |
369 | ||
370 | /* Called with no MMU context (typically MSR:IR/DR off) to | |
371 | * restore CPU state as backed up by the previous | |
372 | * function. This does not include cache setting | |
373 | */ | |
374 | _GLOBAL(__restore_cpu_setup) | |
375 | /* Some CR fields are volatile, we back it up all */ | |
376 | mfcr r7 | |
377 | ||
378 | /* Get storage ptr */ | |
379 | lis r5,(cpu_state_storage-KERNELBASE)@h | |
380 | ori r5,r5,cpu_state_storage@l | |
381 | ||
382 | /* Restore HID0 */ | |
383 | lwz r3,CS_HID0(r5) | |
384 | sync | |
385 | isync | |
386 | mtspr SPRN_HID0,r3 | |
387 | sync | |
388 | isync | |
389 | ||
390 | /* Now deal with CPU type dependent registers */ | |
391 | mfspr r3,SPRN_PVR | |
392 | srwi r3,r3,16 | |
393 | cmplwi cr0,r3,0x8000 /* 7450 */ | |
394 | cmplwi cr1,r3,0x000c /* 7400 */ | |
395 | cmplwi cr2,r3,0x800c /* 7410 */ | |
396 | cmplwi cr3,r3,0x8001 /* 7455 */ | |
397 | cmplwi cr4,r3,0x8002 /* 7457 */ | |
398 | cmplwi cr5,r3,0x8003 /* 7447A */ | |
399 | cmplwi cr6,r3,0x7000 /* 750FX */ | |
bbde630b | 400 | cmplwi cr7,r3,0x8004 /* 7448 */ |
1da177e4 LT |
401 | /* cr1 is 7400 || 7410 */ |
402 | cror 4*cr1+eq,4*cr1+eq,4*cr2+eq | |
403 | /* cr0 is 74xx */ | |
404 | cror 4*cr0+eq,4*cr0+eq,4*cr3+eq | |
405 | cror 4*cr0+eq,4*cr0+eq,4*cr4+eq | |
406 | cror 4*cr0+eq,4*cr0+eq,4*cr1+eq | |
407 | cror 4*cr0+eq,4*cr0+eq,4*cr5+eq | |
bbde630b | 408 | cror 4*cr0+eq,4*cr0+eq,4*cr7+eq |
1da177e4 LT |
409 | bne 2f |
410 | /* Restore 74xx specific regs */ | |
411 | lwz r4,CS_MSSCR0(r5) | |
412 | sync | |
413 | mtspr SPRN_MSSCR0,r4 | |
414 | sync | |
415 | isync | |
416 | lwz r4,CS_MSSSR0(r5) | |
417 | sync | |
418 | mtspr SPRN_MSSSR0,r4 | |
419 | sync | |
420 | isync | |
421 | bne cr2,1f | |
422 | /* Clear 7410 L2CR2 */ | |
423 | li r4,0 | |
424 | mtspr SPRN_L2CR2,r4 | |
425 | 1: beq cr1,2f | |
426 | /* Restore 745x specific registers */ | |
427 | lwz r4,CS_HID1(r5) | |
428 | sync | |
429 | mtspr SPRN_HID1,r4 | |
430 | isync | |
431 | sync | |
432 | lwz r4,CS_ICTRL(r5) | |
433 | sync | |
434 | mtspr SPRN_ICTRL,r4 | |
435 | isync | |
436 | sync | |
437 | lwz r4,CS_LDSTCR(r5) | |
438 | sync | |
439 | mtspr SPRN_LDSTCR,r4 | |
440 | isync | |
441 | sync | |
442 | lwz r4,CS_LDSTDB(r5) | |
443 | sync | |
444 | mtspr SPRN_LDSTDB,r4 | |
445 | isync | |
446 | sync | |
447 | 2: bne cr6,1f | |
448 | /* Restore 750FX specific registers | |
449 | * that is restore HID2 on rev 2.x and PLL config & switch | |
450 | * to PLL 0 on all | |
451 | */ | |
452 | /* If rev 2.x, restore HID2 with low voltage bit cleared */ | |
453 | mfspr r3,SPRN_PVR | |
454 | andi. r3,r3,0xff00 | |
455 | cmpwi cr0,r3,0x0200 | |
456 | bne 4f | |
457 | lwz r4,CS_HID2(r5) | |
458 | rlwinm r4,r4,0,19,17 | |
459 | mtspr SPRN_HID2,r4 | |
460 | sync | |
461 | 4: | |
462 | lwz r4,CS_HID1(r5) | |
463 | rlwinm r5,r4,0,16,14 | |
464 | mtspr SPRN_HID1,r5 | |
465 | /* Wait for PLL to stabilize */ | |
466 | mftbl r5 | |
467 | 3: mftbl r6 | |
468 | sub r6,r6,r5 | |
469 | cmplwi cr0,r6,10000 | |
470 | ble 3b | |
471 | /* Setup final PLL */ | |
472 | mtspr SPRN_HID1,r4 | |
473 | 1: | |
474 | mtcr r7 | |
475 | blr | |
476 |