Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * arch/ppc/kernel/head_fsl_booke.S | |
3 | * | |
4 | * Kernel execution entry point code. | |
5 | * | |
6 | * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> | |
7 | * Initial PowerPC version. | |
8 | * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> | |
9 | * Rewritten for PReP | |
10 | * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> | |
11 | * Low-level exception handers, MMU support, and rewrite. | |
12 | * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> | |
13 | * PowerPC 8xx modifications. | |
14 | * Copyright (c) 1998-1999 TiVo, Inc. | |
15 | * PowerPC 403GCX modifications. | |
16 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> | |
17 | * PowerPC 403GCX/405GP modifications. | |
18 | * Copyright 2000 MontaVista Software Inc. | |
19 | * PPC405 modifications | |
20 | * PowerPC 403GCX/405GP modifications. | |
21 | * Author: MontaVista Software, Inc. | |
22 | * frank_rowand@mvista.com or source@mvista.com | |
23 | * debbie_chu@mvista.com | |
24 | * Copyright 2002-2004 MontaVista Software, Inc. | |
25 | * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> | |
26 | * Copyright 2004 Freescale Semiconductor, Inc | |
27 | * PowerPC e500 modifications, Kumar Gala <kumar.gala@freescale.com> | |
28 | * | |
29 | * This program is free software; you can redistribute it and/or modify it | |
30 | * under the terms of the GNU General Public License as published by the | |
31 | * Free Software Foundation; either version 2 of the License, or (at your | |
32 | * option) any later version. | |
33 | */ | |
34 | ||
35 | #include <linux/config.h> | |
36 | #include <linux/threads.h> | |
37 | #include <asm/processor.h> | |
38 | #include <asm/page.h> | |
39 | #include <asm/mmu.h> | |
40 | #include <asm/pgtable.h> | |
41 | #include <asm/cputable.h> | |
42 | #include <asm/thread_info.h> | |
43 | #include <asm/ppc_asm.h> | |
0013a854 | 44 | #include <asm/asm-offsets.h> |
1da177e4 LT |
45 | #include "head_booke.h" |
46 | ||
47 | /* As with the other PowerPC ports, it is expected that when code | |
48 | * execution begins here, the following registers contain valid, yet | |
49 | * optional, information: | |
50 | * | |
51 | * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) | |
52 | * r4 - Starting address of the init RAM disk | |
53 | * r5 - Ending address of the init RAM disk | |
54 | * r6 - Start of kernel command line string (e.g. "mem=128") | |
55 | * r7 - End of kernel command line string | |
56 | * | |
57 | */ | |
58 | .text | |
59 | _GLOBAL(_stext) | |
60 | _GLOBAL(_start) | |
61 | /* | |
62 | * Reserve a word at a fixed location to store the address | |
63 | * of abatron_pteptrs | |
64 | */ | |
65 | nop | |
66 | /* | |
67 | * Save parameters we are passed | |
68 | */ | |
69 | mr r31,r3 | |
70 | mr r30,r4 | |
71 | mr r29,r5 | |
72 | mr r28,r6 | |
73 | mr r27,r7 | |
74 | li r24,0 /* CPU number */ | |
75 | ||
76 | /* We try to not make any assumptions about how the boot loader | |
77 | * setup or used the TLBs. We invalidate all mappings from the | |
78 | * boot loader and load a single entry in TLB1[0] to map the | |
79 | * first 16M of kernel memory. Any boot info passed from the | |
80 | * bootloader needs to live in this first 16M. | |
81 | * | |
82 | * Requirement on bootloader: | |
83 | * - The page we're executing in needs to reside in TLB1 and | |
84 | * have IPROT=1. If not an invalidate broadcast could | |
85 | * evict the entry we're currently executing in. | |
86 | * | |
87 | * r3 = Index of TLB1 were executing in | |
88 | * r4 = Current MSR[IS] | |
89 | * r5 = Index of TLB1 temp mapping | |
90 | * | |
91 | * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0] | |
92 | * if needed | |
93 | */ | |
94 | ||
95 | /* 1. Find the index of the entry we're executing in */ | |
96 | bl invstr /* Find our address */ | |
97 | invstr: mflr r6 /* Make it accessible */ | |
98 | mfmsr r7 | |
99 | rlwinm r4,r7,27,31,31 /* extract MSR[IS] */ | |
100 | mfspr r7, SPRN_PID0 | |
101 | slwi r7,r7,16 | |
102 | or r7,r7,r4 | |
103 | mtspr SPRN_MAS6,r7 | |
104 | tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */ | |
33d9e9b5 | 105 | #ifndef CONFIG_E200 |
1da177e4 LT |
106 | mfspr r7,SPRN_MAS1 |
107 | andis. r7,r7,MAS1_VALID@h | |
108 | bne match_TLB | |
109 | mfspr r7,SPRN_PID1 | |
110 | slwi r7,r7,16 | |
111 | or r7,r7,r4 | |
112 | mtspr SPRN_MAS6,r7 | |
113 | tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */ | |
114 | mfspr r7,SPRN_MAS1 | |
115 | andis. r7,r7,MAS1_VALID@h | |
116 | bne match_TLB | |
117 | mfspr r7, SPRN_PID2 | |
118 | slwi r7,r7,16 | |
119 | or r7,r7,r4 | |
120 | mtspr SPRN_MAS6,r7 | |
121 | tlbsx 0,r6 /* Fall through, we had to match */ | |
33d9e9b5 | 122 | #endif |
1da177e4 LT |
123 | match_TLB: |
124 | mfspr r7,SPRN_MAS0 | |
125 | rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */ | |
126 | ||
127 | mfspr r7,SPRN_MAS1 /* Insure IPROT set */ | |
128 | oris r7,r7,MAS1_IPROT@h | |
129 | mtspr SPRN_MAS1,r7 | |
130 | tlbwe | |
131 | ||
132 | /* 2. Invalidate all entries except the entry we're executing in */ | |
133 | mfspr r9,SPRN_TLB1CFG | |
134 | andi. r9,r9,0xfff | |
135 | li r6,0 /* Set Entry counter to 0 */ | |
136 | 1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
137 | rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ | |
138 | mtspr SPRN_MAS0,r7 | |
139 | tlbre | |
140 | mfspr r7,SPRN_MAS1 | |
141 | rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ | |
142 | cmpw r3,r6 | |
143 | beq skpinv /* Dont update the current execution TLB */ | |
144 | mtspr SPRN_MAS1,r7 | |
145 | tlbwe | |
146 | isync | |
147 | skpinv: addi r6,r6,1 /* Increment */ | |
148 | cmpw r6,r9 /* Are we done? */ | |
149 | bne 1b /* If not, repeat */ | |
150 | ||
151 | /* Invalidate TLB0 */ | |
152 | li r6,0x04 | |
153 | tlbivax 0,r6 | |
154 | #ifdef CONFIG_SMP | |
155 | tlbsync | |
156 | #endif | |
157 | /* Invalidate TLB1 */ | |
158 | li r6,0x0c | |
159 | tlbivax 0,r6 | |
160 | #ifdef CONFIG_SMP | |
161 | tlbsync | |
162 | #endif | |
163 | msync | |
164 | ||
165 | /* 3. Setup a temp mapping and jump to it */ | |
166 | andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */ | |
167 | addi r5, r5, 0x1 | |
168 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
169 | rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ | |
170 | mtspr SPRN_MAS0,r7 | |
171 | tlbre | |
172 | ||
173 | /* Just modify the entry ID and EPN for the temp mapping */ | |
174 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
175 | rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ | |
176 | mtspr SPRN_MAS0,r7 | |
177 | xori r6,r4,1 /* Setup TMP mapping in the other Address space */ | |
178 | slwi r6,r6,12 | |
179 | oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h | |
180 | ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l | |
181 | mtspr SPRN_MAS1,r6 | |
182 | mfspr r6,SPRN_MAS2 | |
183 | li r7,0 /* temp EPN = 0 */ | |
184 | rlwimi r7,r6,0,20,31 | |
185 | mtspr SPRN_MAS2,r7 | |
186 | tlbwe | |
187 | ||
188 | xori r6,r4,1 | |
189 | slwi r6,r6,5 /* setup new context with other address space */ | |
190 | bl 1f /* Find our address */ | |
191 | 1: mflr r9 | |
192 | rlwimi r7,r9,0,20,31 | |
193 | addi r7,r7,24 | |
194 | mtspr SPRN_SRR0,r7 | |
195 | mtspr SPRN_SRR1,r6 | |
196 | rfi | |
197 | ||
198 | /* 4. Clear out PIDs & Search info */ | |
199 | li r6,0 | |
200 | mtspr SPRN_PID0,r6 | |
33d9e9b5 | 201 | #ifndef CONFIG_E200 |
1da177e4 LT |
202 | mtspr SPRN_PID1,r6 |
203 | mtspr SPRN_PID2,r6 | |
33d9e9b5 | 204 | #endif |
1da177e4 LT |
205 | mtspr SPRN_MAS6,r6 |
206 | ||
207 | /* 5. Invalidate mapping we started in */ | |
208 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
209 | rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ | |
210 | mtspr SPRN_MAS0,r7 | |
211 | tlbre | |
212 | li r6,0 | |
213 | mtspr SPRN_MAS1,r6 | |
214 | tlbwe | |
215 | /* Invalidate TLB1 */ | |
216 | li r9,0x0c | |
217 | tlbivax 0,r9 | |
218 | #ifdef CONFIG_SMP | |
219 | tlbsync | |
220 | #endif | |
221 | msync | |
222 | ||
223 | /* 6. Setup KERNELBASE mapping in TLB1[0] */ | |
224 | lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */ | |
225 | mtspr SPRN_MAS0,r6 | |
226 | lis r6,(MAS1_VALID|MAS1_IPROT)@h | |
227 | ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_16M))@l | |
228 | mtspr SPRN_MAS1,r6 | |
229 | li r7,0 | |
230 | lis r6,KERNELBASE@h | |
231 | ori r6,r6,KERNELBASE@l | |
232 | rlwimi r6,r7,0,20,31 | |
233 | mtspr SPRN_MAS2,r6 | |
234 | li r7,(MAS3_SX|MAS3_SW|MAS3_SR) | |
235 | mtspr SPRN_MAS3,r7 | |
236 | tlbwe | |
237 | ||
238 | /* 7. Jump to KERNELBASE mapping */ | |
252fcaed KG |
239 | lis r7,MSR_KERNEL@h |
240 | ori r7,r7,MSR_KERNEL@l | |
1da177e4 LT |
241 | bl 1f /* Find our address */ |
242 | 1: mflr r9 | |
243 | rlwimi r6,r9,0,20,31 | |
244 | addi r6,r6,24 | |
245 | mtspr SPRN_SRR0,r6 | |
246 | mtspr SPRN_SRR1,r7 | |
247 | rfi /* start execution out of TLB1[0] entry */ | |
248 | ||
249 | /* 8. Clear out the temp mapping */ | |
250 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
251 | rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ | |
252 | mtspr SPRN_MAS0,r7 | |
253 | tlbre | |
254 | mtspr SPRN_MAS1,r8 | |
255 | tlbwe | |
256 | /* Invalidate TLB1 */ | |
257 | li r9,0x0c | |
258 | tlbivax 0,r9 | |
259 | #ifdef CONFIG_SMP | |
260 | tlbsync | |
261 | #endif | |
262 | msync | |
263 | ||
264 | /* Establish the interrupt vector offsets */ | |
265 | SET_IVOR(0, CriticalInput); | |
266 | SET_IVOR(1, MachineCheck); | |
267 | SET_IVOR(2, DataStorage); | |
268 | SET_IVOR(3, InstructionStorage); | |
269 | SET_IVOR(4, ExternalInput); | |
270 | SET_IVOR(5, Alignment); | |
271 | SET_IVOR(6, Program); | |
272 | SET_IVOR(7, FloatingPointUnavailable); | |
273 | SET_IVOR(8, SystemCall); | |
274 | SET_IVOR(9, AuxillaryProcessorUnavailable); | |
275 | SET_IVOR(10, Decrementer); | |
276 | SET_IVOR(11, FixedIntervalTimer); | |
277 | SET_IVOR(12, WatchdogTimer); | |
278 | SET_IVOR(13, DataTLBError); | |
279 | SET_IVOR(14, InstructionTLBError); | |
280 | SET_IVOR(15, Debug); | |
281 | SET_IVOR(32, SPEUnavailable); | |
282 | SET_IVOR(33, SPEFloatingPointData); | |
283 | SET_IVOR(34, SPEFloatingPointRound); | |
33d9e9b5 | 284 | #ifndef CONFIG_E200 |
1da177e4 | 285 | SET_IVOR(35, PerformanceMonitor); |
33d9e9b5 | 286 | #endif |
1da177e4 LT |
287 | |
288 | /* Establish the interrupt vector base */ | |
289 | lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ | |
290 | mtspr SPRN_IVPR,r4 | |
291 | ||
292 | /* Setup the defaults for TLB entries */ | |
293 | li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l | |
33d9e9b5 KG |
294 | #ifdef CONFIG_E200 |
295 | oris r2,r2,MAS4_TLBSELD(1)@h | |
296 | #endif | |
1da177e4 LT |
297 | mtspr SPRN_MAS4, r2 |
298 | ||
299 | #if 0 | |
300 | /* Enable DOZE */ | |
301 | mfspr r2,SPRN_HID0 | |
302 | oris r2,r2,HID0_DOZE@h | |
303 | mtspr SPRN_HID0, r2 | |
304 | #endif | |
33d9e9b5 KG |
305 | #ifdef CONFIG_E200 |
306 | /* enable dedicated debug exception handling resources (Debug APU) */ | |
307 | mfspr r2,SPRN_HID0 | |
308 | ori r2,r2,HID0_DAPUEN@l | |
309 | mtspr SPRN_HID0,r2 | |
310 | #endif | |
1da177e4 | 311 | |
252fcaed KG |
312 | #if !defined(CONFIG_BDI_SWITCH) |
313 | /* | |
314 | * The Abatron BDI JTAG debugger does not tolerate others | |
315 | * mucking with the debug registers. | |
316 | */ | |
317 | lis r2,DBCR0_IDM@h | |
318 | mtspr SPRN_DBCR0,r2 | |
319 | /* clear any residual debug events */ | |
320 | li r2,-1 | |
321 | mtspr SPRN_DBSR,r2 | |
322 | #endif | |
323 | ||
1da177e4 LT |
324 | /* |
325 | * This is where the main kernel code starts. | |
326 | */ | |
327 | ||
328 | /* ptr to current */ | |
329 | lis r2,init_task@h | |
330 | ori r2,r2,init_task@l | |
331 | ||
332 | /* ptr to current thread */ | |
333 | addi r4,r2,THREAD /* init task's THREAD */ | |
334 | mtspr SPRN_SPRG3,r4 | |
335 | ||
336 | /* stack */ | |
337 | lis r1,init_thread_union@h | |
338 | ori r1,r1,init_thread_union@l | |
339 | li r0,0 | |
340 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
341 | ||
342 | bl early_init | |
343 | ||
344 | mfspr r3,SPRN_TLB1CFG | |
345 | andi. r3,r3,0xfff | |
346 | lis r4,num_tlbcam_entries@ha | |
347 | stw r3,num_tlbcam_entries@l(r4) | |
348 | /* | |
349 | * Decide what sort of machine this is and initialize the MMU. | |
350 | */ | |
351 | mr r3,r31 | |
352 | mr r4,r30 | |
353 | mr r5,r29 | |
354 | mr r6,r28 | |
355 | mr r7,r27 | |
356 | bl machine_init | |
357 | bl MMU_init | |
358 | ||
359 | /* Setup PTE pointers for the Abatron bdiGDB */ | |
360 | lis r6, swapper_pg_dir@h | |
361 | ori r6, r6, swapper_pg_dir@l | |
362 | lis r5, abatron_pteptrs@h | |
363 | ori r5, r5, abatron_pteptrs@l | |
364 | lis r4, KERNELBASE@h | |
365 | ori r4, r4, KERNELBASE@l | |
366 | stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ | |
367 | stw r6, 0(r5) | |
368 | ||
369 | /* Let's move on */ | |
370 | lis r4,start_kernel@h | |
371 | ori r4,r4,start_kernel@l | |
372 | lis r3,MSR_KERNEL@h | |
373 | ori r3,r3,MSR_KERNEL@l | |
374 | mtspr SPRN_SRR0,r4 | |
375 | mtspr SPRN_SRR1,r3 | |
376 | rfi /* change context and jump to start_kernel */ | |
377 | ||
f50b153b KG |
378 | /* Macros to hide the PTE size differences |
379 | * | |
380 | * FIND_PTE -- walks the page tables given EA & pgdir pointer | |
381 | * r10 -- EA of fault | |
382 | * r11 -- PGDIR pointer | |
383 | * r12 -- free | |
384 | * label 2: is the bailout case | |
385 | * | |
386 | * if we find the pte (fall through): | |
387 | * r11 is low pte word | |
388 | * r12 is pointer to the pte | |
389 | */ | |
390 | #ifdef CONFIG_PTE_64BIT | |
391 | #define PTE_FLAGS_OFFSET 4 | |
392 | #define FIND_PTE \ | |
393 | rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ | |
394 | lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ | |
395 | rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ | |
396 | beq 2f; /* Bail if no table */ \ | |
397 | rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ | |
398 | lwz r11, 4(r12); /* Get pte entry */ | |
399 | #else | |
400 | #define PTE_FLAGS_OFFSET 0 | |
401 | #define FIND_PTE \ | |
402 | rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \ | |
403 | lwz r11, 0(r11); /* Get L1 entry */ \ | |
404 | rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \ | |
405 | beq 2f; /* Bail if no table */ \ | |
406 | rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \ | |
407 | lwz r11, 0(r12); /* Get Linux PTE */ | |
408 | #endif | |
409 | ||
1da177e4 LT |
410 | /* |
411 | * Interrupt vector entry code | |
412 | * | |
413 | * The Book E MMUs are always on so we don't need to handle | |
414 | * interrupts in real mode as with previous PPC processors. In | |
415 | * this case we handle interrupts in the kernel virtual address | |
416 | * space. | |
417 | * | |
418 | * Interrupt vectors are dynamically placed relative to the | |
419 | * interrupt prefix as determined by the address of interrupt_base. | |
420 | * The interrupt vectors offsets are programmed using the labels | |
421 | * for each interrupt vector entry. | |
422 | * | |
423 | * Interrupt vectors must be aligned on a 16 byte boundary. | |
424 | * We align on a 32 byte cache line boundary for good measure. | |
425 | */ | |
426 | ||
427 | interrupt_base: | |
428 | /* Critical Input Interrupt */ | |
429 | CRITICAL_EXCEPTION(0x0100, CriticalInput, UnknownException) | |
430 | ||
431 | /* Machine Check Interrupt */ | |
33d9e9b5 KG |
432 | #ifdef CONFIG_E200 |
433 | /* no RFMCI, MCSRRs on E200 */ | |
434 | CRITICAL_EXCEPTION(0x0200, MachineCheck, MachineCheckException) | |
435 | #else | |
1da177e4 | 436 | MCHECK_EXCEPTION(0x0200, MachineCheck, MachineCheckException) |
33d9e9b5 | 437 | #endif |
1da177e4 LT |
438 | |
439 | /* Data Storage Interrupt */ | |
440 | START_EXCEPTION(DataStorage) | |
441 | mtspr SPRN_SPRG0, r10 /* Save some working registers */ | |
442 | mtspr SPRN_SPRG1, r11 | |
443 | mtspr SPRN_SPRG4W, r12 | |
444 | mtspr SPRN_SPRG5W, r13 | |
445 | mfcr r11 | |
446 | mtspr SPRN_SPRG7W, r11 | |
447 | ||
448 | /* | |
449 | * Check if it was a store fault, if not then bail | |
450 | * because a user tried to access a kernel or | |
451 | * read-protected page. Otherwise, get the | |
452 | * offending address and handle it. | |
453 | */ | |
454 | mfspr r10, SPRN_ESR | |
455 | andis. r10, r10, ESR_ST@h | |
456 | beq 2f | |
457 | ||
458 | mfspr r10, SPRN_DEAR /* Get faulting address */ | |
459 | ||
460 | /* If we are faulting a kernel address, we have to use the | |
461 | * kernel page tables. | |
462 | */ | |
463 | lis r11, TASK_SIZE@h | |
464 | ori r11, r11, TASK_SIZE@l | |
465 | cmplw 0, r10, r11 | |
466 | bge 2f | |
467 | ||
468 | /* Get the PGD for the current thread */ | |
469 | 3: | |
470 | mfspr r11,SPRN_SPRG3 | |
471 | lwz r11,PGDIR(r11) | |
472 | 4: | |
f50b153b | 473 | FIND_PTE |
1da177e4 LT |
474 | |
475 | /* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */ | |
476 | andi. r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE | |
477 | cmpwi 0, r13, _PAGE_RW|_PAGE_USER | |
478 | bne 2f /* Bail if not */ | |
479 | ||
480 | /* Update 'changed'. */ | |
481 | ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE | |
f50b153b | 482 | stw r11, PTE_FLAGS_OFFSET(r12) /* Update Linux page table */ |
1da177e4 LT |
483 | |
484 | /* MAS2 not updated as the entry does exist in the tlb, this | |
485 | fault taken to detect state transition (eg: COW -> DIRTY) | |
486 | */ | |
f50b153b | 487 | andi. r11, r11, _PAGE_HWEXEC |
1da177e4 LT |
488 | rlwimi r11, r11, 31, 27, 27 /* SX <- _PAGE_HWEXEC */ |
489 | ori r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */ | |
490 | ||
491 | /* update search PID in MAS6, AS = 0 */ | |
492 | mfspr r12, SPRN_PID0 | |
493 | slwi r12, r12, 16 | |
494 | mtspr SPRN_MAS6, r12 | |
495 | ||
496 | /* find the TLB index that caused the fault. It has to be here. */ | |
497 | tlbsx 0, r10 | |
498 | ||
f50b153b KG |
499 | /* only update the perm bits, assume the RPN is fine */ |
500 | mfspr r12, SPRN_MAS3 | |
501 | rlwimi r12, r11, 0, 20, 31 | |
502 | mtspr SPRN_MAS3,r12 | |
1da177e4 LT |
503 | tlbwe |
504 | ||
505 | /* Done...restore registers and get out of here. */ | |
506 | mfspr r11, SPRN_SPRG7R | |
507 | mtcr r11 | |
508 | mfspr r13, SPRN_SPRG5R | |
509 | mfspr r12, SPRN_SPRG4R | |
510 | mfspr r11, SPRN_SPRG1 | |
511 | mfspr r10, SPRN_SPRG0 | |
512 | rfi /* Force context change */ | |
513 | ||
514 | 2: | |
515 | /* | |
516 | * The bailout. Restore registers to pre-exception conditions | |
517 | * and call the heavyweights to help us out. | |
518 | */ | |
519 | mfspr r11, SPRN_SPRG7R | |
520 | mtcr r11 | |
521 | mfspr r13, SPRN_SPRG5R | |
522 | mfspr r12, SPRN_SPRG4R | |
523 | mfspr r11, SPRN_SPRG1 | |
524 | mfspr r10, SPRN_SPRG0 | |
525 | b data_access | |
526 | ||
527 | /* Instruction Storage Interrupt */ | |
528 | INSTRUCTION_STORAGE_EXCEPTION | |
529 | ||
530 | /* External Input Interrupt */ | |
531 | EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE) | |
532 | ||
533 | /* Alignment Interrupt */ | |
534 | ALIGNMENT_EXCEPTION | |
535 | ||
536 | /* Program Interrupt */ | |
537 | PROGRAM_EXCEPTION | |
538 | ||
539 | /* Floating Point Unavailable Interrupt */ | |
443a848c PM |
540 | #ifdef CONFIG_PPC_FPU |
541 | FP_UNAVAILABLE_EXCEPTION | |
33d9e9b5 KG |
542 | #else |
543 | #ifdef CONFIG_E200 | |
544 | /* E200 treats 'normal' floating point instructions as FP Unavail exception */ | |
545 | EXCEPTION(0x0800, FloatingPointUnavailable, ProgramCheckException, EXC_XFER_EE) | |
443a848c | 546 | #else |
1da177e4 | 547 | EXCEPTION(0x0800, FloatingPointUnavailable, UnknownException, EXC_XFER_EE) |
33d9e9b5 | 548 | #endif |
443a848c | 549 | #endif |
1da177e4 LT |
550 | |
551 | /* System Call Interrupt */ | |
552 | START_EXCEPTION(SystemCall) | |
553 | NORMAL_EXCEPTION_PROLOG | |
554 | EXC_XFER_EE_LITE(0x0c00, DoSyscall) | |
555 | ||
556 | /* Auxillary Processor Unavailable Interrupt */ | |
557 | EXCEPTION(0x2900, AuxillaryProcessorUnavailable, UnknownException, EXC_XFER_EE) | |
558 | ||
559 | /* Decrementer Interrupt */ | |
560 | DECREMENTER_EXCEPTION | |
561 | ||
562 | /* Fixed Internal Timer Interrupt */ | |
563 | /* TODO: Add FIT support */ | |
564 | EXCEPTION(0x3100, FixedIntervalTimer, UnknownException, EXC_XFER_EE) | |
565 | ||
566 | /* Watchdog Timer Interrupt */ | |
a2f40ccd KG |
567 | #ifdef CONFIG_BOOKE_WDT |
568 | CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException) | |
569 | #else | |
1da177e4 | 570 | CRITICAL_EXCEPTION(0x3200, WatchdogTimer, UnknownException) |
a2f40ccd | 571 | #endif |
1da177e4 LT |
572 | |
573 | /* Data TLB Error Interrupt */ | |
574 | START_EXCEPTION(DataTLBError) | |
575 | mtspr SPRN_SPRG0, r10 /* Save some working registers */ | |
576 | mtspr SPRN_SPRG1, r11 | |
577 | mtspr SPRN_SPRG4W, r12 | |
578 | mtspr SPRN_SPRG5W, r13 | |
579 | mfcr r11 | |
580 | mtspr SPRN_SPRG7W, r11 | |
581 | mfspr r10, SPRN_DEAR /* Get faulting address */ | |
582 | ||
583 | /* If we are faulting a kernel address, we have to use the | |
584 | * kernel page tables. | |
585 | */ | |
586 | lis r11, TASK_SIZE@h | |
587 | ori r11, r11, TASK_SIZE@l | |
588 | cmplw 5, r10, r11 | |
589 | blt 5, 3f | |
590 | lis r11, swapper_pg_dir@h | |
591 | ori r11, r11, swapper_pg_dir@l | |
592 | ||
593 | mfspr r12,SPRN_MAS1 /* Set TID to 0 */ | |
594 | rlwinm r12,r12,0,16,1 | |
595 | mtspr SPRN_MAS1,r12 | |
596 | ||
597 | b 4f | |
598 | ||
599 | /* Get the PGD for the current thread */ | |
600 | 3: | |
601 | mfspr r11,SPRN_SPRG3 | |
602 | lwz r11,PGDIR(r11) | |
603 | ||
604 | 4: | |
f50b153b KG |
605 | FIND_PTE |
606 | andi. r13, r11, _PAGE_PRESENT /* Is the page present? */ | |
607 | beq 2f /* Bail if not present */ | |
1da177e4 | 608 | |
f50b153b KG |
609 | #ifdef CONFIG_PTE_64BIT |
610 | lwz r13, 0(r12) | |
611 | #endif | |
1da177e4 | 612 | ori r11, r11, _PAGE_ACCESSED |
f50b153b | 613 | stw r11, PTE_FLAGS_OFFSET(r12) |
1da177e4 LT |
614 | |
615 | /* Jump to common tlb load */ | |
616 | b finish_tlb_load | |
617 | 2: | |
618 | /* The bailout. Restore registers to pre-exception conditions | |
619 | * and call the heavyweights to help us out. | |
620 | */ | |
621 | mfspr r11, SPRN_SPRG7R | |
622 | mtcr r11 | |
623 | mfspr r13, SPRN_SPRG5R | |
624 | mfspr r12, SPRN_SPRG4R | |
625 | mfspr r11, SPRN_SPRG1 | |
626 | mfspr r10, SPRN_SPRG0 | |
627 | b data_access | |
628 | ||
629 | /* Instruction TLB Error Interrupt */ | |
630 | /* | |
631 | * Nearly the same as above, except we get our | |
632 | * information from different registers and bailout | |
633 | * to a different point. | |
634 | */ | |
635 | START_EXCEPTION(InstructionTLBError) | |
636 | mtspr SPRN_SPRG0, r10 /* Save some working registers */ | |
637 | mtspr SPRN_SPRG1, r11 | |
638 | mtspr SPRN_SPRG4W, r12 | |
639 | mtspr SPRN_SPRG5W, r13 | |
640 | mfcr r11 | |
641 | mtspr SPRN_SPRG7W, r11 | |
642 | mfspr r10, SPRN_SRR0 /* Get faulting address */ | |
643 | ||
644 | /* If we are faulting a kernel address, we have to use the | |
645 | * kernel page tables. | |
646 | */ | |
647 | lis r11, TASK_SIZE@h | |
648 | ori r11, r11, TASK_SIZE@l | |
649 | cmplw 5, r10, r11 | |
650 | blt 5, 3f | |
651 | lis r11, swapper_pg_dir@h | |
652 | ori r11, r11, swapper_pg_dir@l | |
653 | ||
654 | mfspr r12,SPRN_MAS1 /* Set TID to 0 */ | |
655 | rlwinm r12,r12,0,16,1 | |
656 | mtspr SPRN_MAS1,r12 | |
657 | ||
658 | b 4f | |
659 | ||
660 | /* Get the PGD for the current thread */ | |
661 | 3: | |
662 | mfspr r11,SPRN_SPRG3 | |
663 | lwz r11,PGDIR(r11) | |
664 | ||
665 | 4: | |
f50b153b KG |
666 | FIND_PTE |
667 | andi. r13, r11, _PAGE_PRESENT /* Is the page present? */ | |
668 | beq 2f /* Bail if not present */ | |
1da177e4 | 669 | |
f50b153b KG |
670 | #ifdef CONFIG_PTE_64BIT |
671 | lwz r13, 0(r12) | |
672 | #endif | |
1da177e4 | 673 | ori r11, r11, _PAGE_ACCESSED |
f50b153b | 674 | stw r11, PTE_FLAGS_OFFSET(r12) |
1da177e4 LT |
675 | |
676 | /* Jump to common TLB load point */ | |
677 | b finish_tlb_load | |
678 | ||
679 | 2: | |
680 | /* The bailout. Restore registers to pre-exception conditions | |
681 | * and call the heavyweights to help us out. | |
682 | */ | |
683 | mfspr r11, SPRN_SPRG7R | |
684 | mtcr r11 | |
685 | mfspr r13, SPRN_SPRG5R | |
686 | mfspr r12, SPRN_SPRG4R | |
687 | mfspr r11, SPRN_SPRG1 | |
688 | mfspr r10, SPRN_SPRG0 | |
689 | b InstructionStorage | |
690 | ||
691 | #ifdef CONFIG_SPE | |
692 | /* SPE Unavailable */ | |
693 | START_EXCEPTION(SPEUnavailable) | |
694 | NORMAL_EXCEPTION_PROLOG | |
695 | bne load_up_spe | |
696 | addi r3,r1,STACK_FRAME_OVERHEAD | |
697 | EXC_XFER_EE_LITE(0x2010, KernelSPE) | |
698 | #else | |
699 | EXCEPTION(0x2020, SPEUnavailable, UnknownException, EXC_XFER_EE) | |
700 | #endif /* CONFIG_SPE */ | |
701 | ||
702 | /* SPE Floating Point Data */ | |
703 | #ifdef CONFIG_SPE | |
704 | EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE); | |
705 | #else | |
706 | EXCEPTION(0x2040, SPEFloatingPointData, UnknownException, EXC_XFER_EE) | |
707 | #endif /* CONFIG_SPE */ | |
708 | ||
709 | /* SPE Floating Point Round */ | |
710 | EXCEPTION(0x2050, SPEFloatingPointRound, UnknownException, EXC_XFER_EE) | |
711 | ||
712 | /* Performance Monitor */ | |
713 | EXCEPTION(0x2060, PerformanceMonitor, PerformanceMonitorException, EXC_XFER_STD) | |
714 | ||
715 | ||
716 | /* Debug Interrupt */ | |
717 | DEBUG_EXCEPTION | |
718 | ||
719 | /* | |
720 | * Local functions | |
721 | */ | |
33d9e9b5 | 722 | |
1da177e4 LT |
723 | /* |
724 | * Data TLB exceptions will bail out to this point | |
725 | * if they can't resolve the lightweight TLB fault. | |
726 | */ | |
727 | data_access: | |
728 | NORMAL_EXCEPTION_PROLOG | |
729 | mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ | |
730 | stw r5,_ESR(r11) | |
731 | mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ | |
732 | andis. r10,r5,(ESR_ILK|ESR_DLK)@h | |
733 | bne 1f | |
734 | EXC_XFER_EE_LITE(0x0300, handle_page_fault) | |
735 | 1: | |
736 | addi r3,r1,STACK_FRAME_OVERHEAD | |
737 | EXC_XFER_EE_LITE(0x0300, CacheLockingException) | |
738 | ||
739 | /* | |
740 | ||
741 | * Both the instruction and data TLB miss get to this | |
742 | * point to load the TLB. | |
743 | * r10 - EA of fault | |
744 | * r11 - TLB (info from Linux PTE) | |
745 | * r12, r13 - available to use | |
746 | * CR5 - results of addr < TASK_SIZE | |
747 | * MAS0, MAS1 - loaded with proper value when we get here | |
748 | * MAS2, MAS3 - will need additional info from Linux PTE | |
749 | * Upon exit, we reload everything and RFI. | |
750 | */ | |
751 | finish_tlb_load: | |
752 | /* | |
753 | * We set execute, because we don't have the granularity to | |
754 | * properly set this at the page level (Linux problem). | |
755 | * Many of these bits are software only. Bits we don't set | |
756 | * here we (properly should) assume have the appropriate value. | |
757 | */ | |
758 | ||
759 | mfspr r12, SPRN_MAS2 | |
f50b153b KG |
760 | #ifdef CONFIG_PTE_64BIT |
761 | rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */ | |
762 | #else | |
1da177e4 | 763 | rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */ |
f50b153b | 764 | #endif |
1da177e4 LT |
765 | mtspr SPRN_MAS2, r12 |
766 | ||
767 | bge 5, 1f | |
768 | ||
f50b153b KG |
769 | /* is user addr */ |
770 | andi. r12, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC) | |
771 | andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */ | |
772 | srwi r10, r12, 1 | |
1da177e4 | 773 | or r12, r12, r10 /* Copy user perms into supervisor */ |
f50b153b | 774 | iseleq r12, 0, r12 |
1da177e4 LT |
775 | b 2f |
776 | ||
f50b153b | 777 | /* is kernel addr */ |
1da177e4 LT |
778 | 1: rlwinm r12, r11, 31, 29, 29 /* Extract _PAGE_HWWRITE into SW */ |
779 | ori r12, r12, (MAS3_SX | MAS3_SR) | |
780 | ||
f50b153b KG |
781 | #ifdef CONFIG_PTE_64BIT |
782 | 2: rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */ | |
783 | rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */ | |
784 | mtspr SPRN_MAS3, r12 | |
785 | BEGIN_FTR_SECTION | |
786 | srwi r10, r13, 8 /* grab RPN[8:31] */ | |
787 | mtspr SPRN_MAS7, r10 | |
788 | END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS) | |
789 | #else | |
1da177e4 LT |
790 | 2: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */ |
791 | mtspr SPRN_MAS3, r11 | |
f50b153b | 792 | #endif |
33d9e9b5 KG |
793 | #ifdef CONFIG_E200 |
794 | /* Round robin TLB1 entries assignment */ | |
795 | mfspr r12, SPRN_MAS0 | |
796 | ||
797 | /* Extract TLB1CFG(NENTRY) */ | |
798 | mfspr r11, SPRN_TLB1CFG | |
799 | andi. r11, r11, 0xfff | |
800 | ||
801 | /* Extract MAS0(NV) */ | |
802 | andi. r13, r12, 0xfff | |
803 | addi r13, r13, 1 | |
804 | cmpw 0, r13, r11 | |
805 | addi r12, r12, 1 | |
806 | ||
807 | /* check if we need to wrap */ | |
808 | blt 7f | |
809 | ||
810 | /* wrap back to first free tlbcam entry */ | |
811 | lis r13, tlbcam_index@ha | |
812 | lwz r13, tlbcam_index@l(r13) | |
813 | rlwimi r12, r13, 0, 20, 31 | |
814 | 7: | |
815 | mtspr SPRN_MAS0,r12 | |
816 | #endif /* CONFIG_E200 */ | |
817 | ||
1da177e4 LT |
818 | tlbwe |
819 | ||
820 | /* Done...restore registers and get out of here. */ | |
821 | mfspr r11, SPRN_SPRG7R | |
822 | mtcr r11 | |
823 | mfspr r13, SPRN_SPRG5R | |
824 | mfspr r12, SPRN_SPRG4R | |
825 | mfspr r11, SPRN_SPRG1 | |
826 | mfspr r10, SPRN_SPRG0 | |
827 | rfi /* Force context change */ | |
828 | ||
829 | #ifdef CONFIG_SPE | |
830 | /* Note that the SPE support is closely modeled after the AltiVec | |
831 | * support. Changes to one are likely to be applicable to the | |
832 | * other! */ | |
833 | load_up_spe: | |
834 | /* | |
835 | * Disable SPE for the task which had SPE previously, | |
836 | * and save its SPE registers in its thread_struct. | |
837 | * Enables SPE for use in the kernel on return. | |
838 | * On SMP we know the SPE units are free, since we give it up every | |
839 | * switch. -- Kumar | |
840 | */ | |
841 | mfmsr r5 | |
842 | oris r5,r5,MSR_SPE@h | |
843 | mtmsr r5 /* enable use of SPE now */ | |
844 | isync | |
845 | /* | |
846 | * For SMP, we don't do lazy SPE switching because it just gets too | |
847 | * horrendously complex, especially when a task switches from one CPU | |
848 | * to another. Instead we call giveup_spe in switch_to. | |
849 | */ | |
850 | #ifndef CONFIG_SMP | |
851 | lis r3,last_task_used_spe@ha | |
852 | lwz r4,last_task_used_spe@l(r3) | |
853 | cmpi 0,r4,0 | |
854 | beq 1f | |
855 | addi r4,r4,THREAD /* want THREAD of last_task_used_spe */ | |
856 | SAVE_32EVR(0,r10,r4) | |
857 | evxor evr10, evr10, evr10 /* clear out evr10 */ | |
858 | evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */ | |
859 | li r5,THREAD_ACC | |
860 | evstddx evr10, r4, r5 /* save off accumulator */ | |
861 | lwz r5,PT_REGS(r4) | |
862 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
863 | lis r10,MSR_SPE@h | |
864 | andc r4,r4,r10 /* disable SPE for previous task */ | |
865 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
866 | 1: | |
867 | #endif /* CONFIG_SMP */ | |
868 | /* enable use of SPE after return */ | |
869 | oris r9,r9,MSR_SPE@h | |
870 | mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ | |
871 | li r4,1 | |
872 | li r10,THREAD_ACC | |
873 | stw r4,THREAD_USED_SPE(r5) | |
874 | evlddx evr4,r10,r5 | |
875 | evmra evr4,evr4 | |
876 | REST_32EVR(0,r10,r5) | |
877 | #ifndef CONFIG_SMP | |
878 | subi r4,r5,THREAD | |
879 | stw r4,last_task_used_spe@l(r3) | |
880 | #endif /* CONFIG_SMP */ | |
881 | /* restore registers and return */ | |
882 | 2: REST_4GPRS(3, r11) | |
883 | lwz r10,_CCR(r11) | |
884 | REST_GPR(1, r11) | |
885 | mtcr r10 | |
886 | lwz r10,_LINK(r11) | |
887 | mtlr r10 | |
888 | REST_GPR(10, r11) | |
889 | mtspr SPRN_SRR1,r9 | |
890 | mtspr SPRN_SRR0,r12 | |
891 | REST_GPR(9, r11) | |
892 | REST_GPR(12, r11) | |
893 | lwz r11,GPR11(r11) | |
894 | SYNC | |
895 | rfi | |
896 | ||
897 | /* | |
898 | * SPE unavailable trap from kernel - print a message, but let | |
899 | * the task use SPE in the kernel until it returns to user mode. | |
900 | */ | |
901 | KernelSPE: | |
902 | lwz r3,_MSR(r1) | |
903 | oris r3,r3,MSR_SPE@h | |
904 | stw r3,_MSR(r1) /* enable use of SPE after return */ | |
905 | lis r3,87f@h | |
906 | ori r3,r3,87f@l | |
907 | mr r4,r2 /* current */ | |
908 | lwz r5,_NIP(r1) | |
909 | bl printk | |
910 | b ret_from_except | |
911 | 87: .string "SPE used in kernel (task=%p, pc=%x) \n" | |
912 | .align 4,0 | |
913 | ||
914 | #endif /* CONFIG_SPE */ | |
915 | ||
916 | /* | |
917 | * Global functions | |
918 | */ | |
919 | ||
920 | /* | |
921 | * extern void loadcam_entry(unsigned int index) | |
922 | * | |
923 | * Load TLBCAM[index] entry in to the L2 CAM MMU | |
924 | */ | |
925 | _GLOBAL(loadcam_entry) | |
926 | lis r4,TLBCAM@ha | |
927 | addi r4,r4,TLBCAM@l | |
928 | mulli r5,r3,20 | |
929 | add r3,r5,r4 | |
930 | lwz r4,0(r3) | |
931 | mtspr SPRN_MAS0,r4 | |
932 | lwz r4,4(r3) | |
933 | mtspr SPRN_MAS1,r4 | |
934 | lwz r4,8(r3) | |
935 | mtspr SPRN_MAS2,r4 | |
936 | lwz r4,12(r3) | |
937 | mtspr SPRN_MAS3,r4 | |
938 | tlbwe | |
939 | isync | |
940 | blr | |
941 | ||
942 | /* | |
943 | * extern void giveup_altivec(struct task_struct *prev) | |
944 | * | |
945 | * The e500 core does not have an AltiVec unit. | |
946 | */ | |
947 | _GLOBAL(giveup_altivec) | |
948 | blr | |
949 | ||
950 | #ifdef CONFIG_SPE | |
951 | /* | |
952 | * extern void giveup_spe(struct task_struct *prev) | |
953 | * | |
954 | */ | |
955 | _GLOBAL(giveup_spe) | |
956 | mfmsr r5 | |
957 | oris r5,r5,MSR_SPE@h | |
958 | SYNC | |
959 | mtmsr r5 /* enable use of SPE now */ | |
960 | isync | |
961 | cmpi 0,r3,0 | |
962 | beqlr- /* if no previous owner, done */ | |
963 | addi r3,r3,THREAD /* want THREAD of task */ | |
964 | lwz r5,PT_REGS(r3) | |
965 | cmpi 0,r5,0 | |
966 | SAVE_32EVR(0, r4, r3) | |
967 | evxor evr6, evr6, evr6 /* clear out evr6 */ | |
968 | evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */ | |
969 | li r4,THREAD_ACC | |
970 | evstddx evr6, r4, r3 /* save off accumulator */ | |
971 | mfspr r6,SPRN_SPEFSCR | |
972 | stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */ | |
973 | beq 1f | |
974 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
975 | lis r3,MSR_SPE@h | |
976 | andc r4,r4,r3 /* disable SPE for previous task */ | |
977 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
978 | 1: | |
979 | #ifndef CONFIG_SMP | |
980 | li r5,0 | |
981 | lis r4,last_task_used_spe@ha | |
982 | stw r5,last_task_used_spe@l(r4) | |
983 | #endif /* CONFIG_SMP */ | |
984 | blr | |
985 | #endif /* CONFIG_SPE */ | |
986 | ||
987 | /* | |
988 | * extern void giveup_fpu(struct task_struct *prev) | |
989 | * | |
443a848c | 990 | * Not all FSL Book-E cores have an FPU |
1da177e4 | 991 | */ |
443a848c | 992 | #ifndef CONFIG_PPC_FPU |
1da177e4 LT |
993 | _GLOBAL(giveup_fpu) |
994 | blr | |
443a848c | 995 | #endif |
1da177e4 LT |
996 | |
997 | /* | |
998 | * extern void abort(void) | |
999 | * | |
1000 | * At present, this routine just applies a system reset. | |
1001 | */ | |
1002 | _GLOBAL(abort) | |
1003 | li r13,0 | |
1004 | mtspr SPRN_DBCR0,r13 /* disable all debug events */ | |
1005 | mfmsr r13 | |
1006 | ori r13,r13,MSR_DE@l /* Enable Debug Events */ | |
1007 | mtmsr r13 | |
1008 | mfspr r13,SPRN_DBCR0 | |
1009 | lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h | |
1010 | mtspr SPRN_DBCR0,r13 | |
1011 | ||
1012 | _GLOBAL(set_context) | |
1013 | ||
1014 | #ifdef CONFIG_BDI_SWITCH | |
1015 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
1016 | * The PGDIR is the second parameter. | |
1017 | */ | |
1018 | lis r5, abatron_pteptrs@h | |
1019 | ori r5, r5, abatron_pteptrs@l | |
1020 | stw r4, 0x4(r5) | |
1021 | #endif | |
1022 | mtspr SPRN_PID,r3 | |
1023 | isync /* Force context change */ | |
1024 | blr | |
1025 | ||
1026 | /* | |
1027 | * We put a few things here that have to be page-aligned. This stuff | |
1028 | * goes at the beginning of the data segment, which is page-aligned. | |
1029 | */ | |
1030 | .data | |
1031 | _GLOBAL(sdata) | |
1032 | _GLOBAL(empty_zero_page) | |
1033 | .space 4096 | |
1034 | _GLOBAL(swapper_pg_dir) | |
1035 | .space 4096 | |
1036 | ||
1037 | /* Reserved 4k for the critical exception stack & 4k for the machine | |
1038 | * check stack per CPU for kernel mode exceptions */ | |
1039 | .section .bss | |
1040 | .align 12 | |
1041 | exception_stack_bottom: | |
1042 | .space BOOKE_EXCEPTION_STACK_SIZE * NR_CPUS | |
1043 | _GLOBAL(exception_stack_top) | |
1044 | ||
1045 | /* | |
1046 | * This space gets a copy of optional info passed to us by the bootstrap | |
1047 | * which is used to pass parameters into the kernel like root=/dev/sda1, etc. | |
1048 | */ | |
1049 | _GLOBAL(cmd_line) | |
1050 | .space 512 | |
1051 | ||
1052 | /* | |
1053 | * Room for two PTE pointers, usually the kernel and current user pointers | |
1054 | * to their respective root page table. | |
1055 | */ | |
1056 | abatron_pteptrs: | |
1057 | .space 8 | |
1058 |