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kbuild: m68k,parisc,ppc,ppc64,s390,xtensa use generic asm-offsets.h support
[deliverable/linux.git] / arch / ppc / kernel / misc.S
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1da177e4
LT		 1/*
2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
6 * and Paul Mackerras.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 *
13 */
14
15#include <linux/config.h>
16#include <linux/sys.h>
17#include <asm/unistd.h>
18#include <asm/errno.h>
19#include <asm/processor.h>
20#include <asm/page.h>
21#include <asm/cache.h>
22#include <asm/cputable.h>
23#include <asm/mmu.h>
24#include <asm/ppc_asm.h>
25#include <asm/thread_info.h>
0013a854 26#include <asm/asm-offsets.h>
1da177e4
LT		 27
28 .text
29
30 .align 5
31_GLOBAL(__delay)
32 cmpwi 0,r3,0
33 mtctr r3
34 beqlr
351: bdnz 1b
36 blr
37
38/*
39 * Returns (address we're running at) - (address we were linked at)
40 * for use before the text and data are mapped to KERNELBASE.
41 */
42_GLOBAL(reloc_offset)
43 mflr r0
44 bl 1f
451: mflr r3
46 lis r4,1b@ha
47 addi r4,r4,1b@l
48 subf r3,r4,r3
49 mtlr r0
50 blr
51
52/*
53 * add_reloc_offset(x) returns x + reloc_offset().
54 */
55_GLOBAL(add_reloc_offset)
56 mflr r0
57 bl 1f
581: mflr r5
59 lis r4,1b@ha
60 addi r4,r4,1b@l
61 subf r5,r4,r5
62 add r3,r3,r5
63 mtlr r0
64 blr
65
66/*
67 * sub_reloc_offset(x) returns x - reloc_offset().
68 */
69_GLOBAL(sub_reloc_offset)
70 mflr r0
71 bl 1f
721: mflr r5
73 lis r4,1b@ha
74 addi r4,r4,1b@l
75 subf r5,r4,r5
76 subf r3,r5,r3
77 mtlr r0
78 blr
79
80/*
81 * reloc_got2 runs through the .got2 section adding an offset
82 * to each entry.
83 */
84_GLOBAL(reloc_got2)
85 mflr r11
86 lis r7,__got2_start@ha
87 addi r7,r7,__got2_start@l
88 lis r8,__got2_end@ha
89 addi r8,r8,__got2_end@l
90 subf r8,r7,r8
91 srwi. r8,r8,2
92 beqlr
93 mtctr r8
94 bl 1f
951: mflr r0
96 lis r4,1b@ha
97 addi r4,r4,1b@l
98 subf r0,r4,r0
99 add r7,r0,r7
1002: lwz r0,0(r7)
101 add r0,r0,r3
102 stw r0,0(r7)
103 addi r7,r7,4
104 bdnz 2b
105 mtlr r11
106 blr
107
108/*
109 * identify_cpu,
110 * called with r3 = data offset and r4 = CPU number
111 * doesn't change r3
112 */
113_GLOBAL(identify_cpu)
114 addis r8,r3,cpu_specs@ha
115 addi r8,r8,cpu_specs@l
116 mfpvr r7
1171:
118 lwz r5,CPU_SPEC_PVR_MASK(r8)
119 and r5,r5,r7
120 lwz r6,CPU_SPEC_PVR_VALUE(r8)
121 cmplw 0,r6,r5
122 beq 1f
123 addi r8,r8,CPU_SPEC_ENTRY_SIZE
124 b 1b
1251:
126 addis r6,r3,cur_cpu_spec@ha
127 addi r6,r6,cur_cpu_spec@l
128 slwi r4,r4,2
129 sub r8,r8,r3
130 stwx r8,r4,r6
131 blr
132
133/*
134 * do_cpu_ftr_fixups - goes through the list of CPU feature fixups
135 * and writes nop's over sections of code that don't apply for this cpu.
136 * r3 = data offset (not changed)
137 */
138_GLOBAL(do_cpu_ftr_fixups)
139 /* Get CPU 0 features */
140 addis r6,r3,cur_cpu_spec@ha
141 addi r6,r6,cur_cpu_spec@l
142 lwz r4,0(r6)
143 add r4,r4,r3
144 lwz r4,CPU_SPEC_FEATURES(r4)
145
146 /* Get the fixup table */
147 addis r6,r3,__start___ftr_fixup@ha
148 addi r6,r6,__start___ftr_fixup@l
149 addis r7,r3,__stop___ftr_fixup@ha
150 addi r7,r7,__stop___ftr_fixup@l
151
152 /* Do the fixup */
1531: cmplw 0,r6,r7
154 bgelr
155 addi r6,r6,16
156 lwz r8,-16(r6) /* mask */
157 and r8,r8,r4
158 lwz r9,-12(r6) /* value */
159 cmplw 0,r8,r9
160 beq 1b
161 lwz r8,-8(r6) /* section begin */
162 lwz r9,-4(r6) /* section end */
163 subf. r9,r8,r9
164 beq 1b
165 /* write nops over the section of code */
166 /* todo: if large section, add a branch at the start of it */
167 srwi r9,r9,2
168 mtctr r9
169 add r8,r8,r3
170 lis r0,0x60000000@h /* nop */
1713: stw r0,0(r8)
172 andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
173 beq 2f
174 dcbst 0,r8 /* suboptimal, but simpler */
175 sync
176 icbi 0,r8
1772: addi r8,r8,4
178 bdnz 3b
179 sync /* additional sync needed on g4 */
180 isync
181 b 1b
182
183/*
184 * call_setup_cpu - call the setup_cpu function for this cpu
185 * r3 = data offset, r24 = cpu number
186 *
187 * Setup function is called with:
188 * r3 = data offset
189 * r4 = CPU number
190 * r5 = ptr to CPU spec (relocated)
191 */
192_GLOBAL(call_setup_cpu)
193 addis r5,r3,cur_cpu_spec@ha
194 addi r5,r5,cur_cpu_spec@l
195 slwi r4,r24,2
196 lwzx r5,r4,r5
197 add r5,r5,r3
198 lwz r6,CPU_SPEC_SETUP(r5)
199 add r6,r6,r3
200 mtctr r6
201 mr r4,r24
202 bctr
203
204#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
205
206/* This gets called by via-pmu.c to switch the PLL selection
207 * on 750fx CPU. This function should really be moved to some
208 * other place (as most of the cpufreq code in via-pmu
209 */
210_GLOBAL(low_choose_750fx_pll)
211 /* Clear MSR:EE */
212 mfmsr r7
213 rlwinm r0,r7,0,17,15
214 mtmsr r0
215
216 /* If switching to PLL1, disable HID0:BTIC */
217 cmplwi cr0,r3,0
218 beq 1f
219 mfspr r5,SPRN_HID0
220 rlwinm r5,r5,0,27,25
221 sync
222 mtspr SPRN_HID0,r5
223 isync
224 sync
225
2261:
227 /* Calc new HID1 value */
228 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
229 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
230 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
231 or r4,r4,r5
232 mtspr SPRN_HID1,r4
233
234 /* Store new HID1 image */
235 rlwinm r6,r1,0,0,18
236 lwz r6,TI_CPU(r6)
237 slwi r6,r6,2
238 addis r6,r6,nap_save_hid1@ha
239 stw r4,nap_save_hid1@l(r6)
240
241 /* If switching to PLL0, enable HID0:BTIC */
242 cmplwi cr0,r3,0
243 bne 1f
244 mfspr r5,SPRN_HID0
245 ori r5,r5,HID0_BTIC
246 sync
247 mtspr SPRN_HID0,r5
248 isync
249 sync
250
2511:
252 /* Return */
253 mtmsr r7
254 blr
255
256_GLOBAL(low_choose_7447a_dfs)
257 /* Clear MSR:EE */
258 mfmsr r7
259 rlwinm r0,r7,0,17,15
260 mtmsr r0
261
262 /* Calc new HID1 value */
263 mfspr r4,SPRN_HID1
264 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
265 sync
266 mtspr SPRN_HID1,r4
267 sync
268 isync
269
270 /* Return */
271 mtmsr r7
272 blr
273
274#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
275
276/* void local_save_flags_ptr(unsigned long *flags) */
277_GLOBAL(local_save_flags_ptr)
278 mfmsr r4
279 stw r4,0(r3)
280 blr
281 /*
282 * Need these nops here for taking over save/restore to
283 * handle lost intrs
284 * -- Cort
285 */
286 nop
287 nop
288 nop
289 nop
290 nop
291 nop
292 nop
293 nop
294 nop
295 nop
296 nop
297 nop
298 nop
299 nop
300 nop
301 nop
302 nop
303_GLOBAL(local_save_flags_ptr_end)
304
305/* void local_irq_restore(unsigned long flags) */
306_GLOBAL(local_irq_restore)
307/*
308 * Just set/clear the MSR_EE bit through restore/flags but do not
309 * change anything else. This is needed by the RT system and makes
310 * sense anyway.
311 * -- Cort
312 */
313 mfmsr r4
314 /* Copy all except the MSR_EE bit from r4 (current MSR value)
315 to r3. This is the sort of thing the rlwimi instruction is
316 designed for. -- paulus. */
317 rlwimi r3,r4,0,17,15
318 /* Check if things are setup the way we want _already_. */
319 cmpw 0,r3,r4
320 beqlr
3211: SYNC
322 mtmsr r3
323 SYNC
324 blr
325 nop
326 nop
327 nop
328 nop
329 nop
330 nop
331 nop
332 nop
333 nop
334 nop
335 nop
336 nop
337 nop
338 nop
339 nop
340 nop
341 nop
342 nop
343 nop
344_GLOBAL(local_irq_restore_end)
345
346_GLOBAL(local_irq_disable)
347 mfmsr r0 /* Get current interrupt state */
348 rlwinm r3,r0,16+1,32-1,31 /* Extract old value of 'EE' */
349 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
350 SYNC /* Some chip revs have problems here... */
351 mtmsr r0 /* Update machine state */
352 blr /* Done */
353 /*
354 * Need these nops here for taking over save/restore to
355 * handle lost intrs
356 * -- Cort
357 */
358 nop
359 nop
360 nop
361 nop
362 nop
363 nop
364 nop
365 nop
366 nop
367 nop
368 nop
369 nop
370 nop
371 nop
372 nop
373_GLOBAL(local_irq_disable_end)
374
375_GLOBAL(local_irq_enable)
376 mfmsr r3 /* Get current state */
377 ori r3,r3,MSR_EE /* Turn on 'EE' bit */
378 SYNC /* Some chip revs have problems here... */
379 mtmsr r3 /* Update machine state */
380 blr
381 /*
382 * Need these nops here for taking over save/restore to
383 * handle lost intrs
384 * -- Cort
385 */
386 nop
387 nop
388 nop
389 nop
390 nop
391 nop
392 nop
393 nop
394 nop
395 nop
396 nop
397 nop
398 nop
399 nop
400 nop
401 nop
402_GLOBAL(local_irq_enable_end)
403
404/*
405 * complement mask on the msr then "or" some values on.
406 * _nmask_and_or_msr(nmask, value_to_or)
407 */
408_GLOBAL(_nmask_and_or_msr)
409 mfmsr r0 /* Get current msr */
410 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
411 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
412 SYNC /* Some chip revs have problems here... */
413 mtmsr r0 /* Update machine state */
414 isync
415 blr /* Done */
416
417
418/*
419 * Flush MMU TLB
420 */
421_GLOBAL(_tlbia)
422#if defined(CONFIG_40x)
423 sync /* Flush to memory before changing mapping */
424 tlbia
425 isync /* Flush shadow TLB */
426#elif defined(CONFIG_44x)
427 li r3,0
428 sync
429
430 /* Load high watermark */
431 lis r4,tlb_44x_hwater@ha
432 lwz r5,tlb_44x_hwater@l(r4)
433
4341: tlbwe r3,r3,PPC44x_TLB_PAGEID
435 addi r3,r3,1
436 cmpw 0,r3,r5
437 ble 1b
438
439 isync
440#elif defined(CONFIG_FSL_BOOKE)
441 /* Invalidate all entries in TLB0 */
442 li r3, 0x04
443 tlbivax 0,3
444 /* Invalidate all entries in TLB1 */
445 li r3, 0x0c
446 tlbivax 0,3
447 /* Invalidate all entries in TLB2 */
448 li r3, 0x14
449 tlbivax 0,3
450 /* Invalidate all entries in TLB3 */
451 li r3, 0x1c
452 tlbivax 0,3
453 msync
454#ifdef CONFIG_SMP
455 tlbsync
456#endif /* CONFIG_SMP */
457#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
458#if defined(CONFIG_SMP)
459 rlwinm r8,r1,0,0,18
460 lwz r8,TI_CPU(r8)
461 oris r8,r8,10
462 mfmsr r10
463 SYNC
464 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
465 rlwinm r0,r0,0,28,26 /* clear DR */
466 mtmsr r0
467 SYNC_601
468 isync
469 lis r9,mmu_hash_lock@h
470 ori r9,r9,mmu_hash_lock@l
471 tophys(r9,r9)
47210: lwarx r7,0,r9
473 cmpwi 0,r7,0
474 bne- 10b
475 stwcx. r8,0,r9
476 bne- 10b
477 sync
478 tlbia
479 sync
480 TLBSYNC
481 li r0,0
482 stw r0,0(r9) /* clear mmu_hash_lock */
483 mtmsr r10
484 SYNC_601
485 isync
486#else /* CONFIG_SMP */
487 sync
488 tlbia
489 sync
490#endif /* CONFIG_SMP */
491#endif /* ! defined(CONFIG_40x) */
492 blr
493
494/*
495 * Flush MMU TLB for a particular address
496 */
497_GLOBAL(_tlbie)
498#if defined(CONFIG_40x)
499 tlbsx. r3, 0, r3
500 bne 10f
501 sync
502 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
503 * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
504 * the TLB entry. */
505 tlbwe r3, r3, TLB_TAG
506 isync
50710:
508#elif defined(CONFIG_44x)
509 mfspr r4,SPRN_MMUCR
510 mfspr r5,SPRN_PID /* Get PID */
511 rlwimi r4,r5,0,24,31 /* Set TID */
512 mtspr SPRN_MMUCR,r4
513
514 tlbsx. r3, 0, r3
515 bne 10f
516 sync
517 /* There are only 64 TLB entries, so r3 < 64,
518 * which means bit 22, is clear. Since 22 is
519 * the V bit in the TLB_PAGEID, loading this
520 * value will invalidate the TLB entry.
521 */
522 tlbwe r3, r3, PPC44x_TLB_PAGEID
523 isync
52410:
525#elif defined(CONFIG_FSL_BOOKE)
526 rlwinm r4, r3, 0, 0, 19
527 ori r5, r4, 0x08 /* TLBSEL = 1 */
528 ori r6, r4, 0x10 /* TLBSEL = 2 */
529 ori r7, r4, 0x18 /* TLBSEL = 3 */
530 tlbivax 0, r4
531 tlbivax 0, r5
532 tlbivax 0, r6
533 tlbivax 0, r7
534 msync
535#if defined(CONFIG_SMP)
536 tlbsync
537#endif /* CONFIG_SMP */
538#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
539#if defined(CONFIG_SMP)
540 rlwinm r8,r1,0,0,18
541 lwz r8,TI_CPU(r8)
542 oris r8,r8,11
543 mfmsr r10
544 SYNC
545 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
546 rlwinm r0,r0,0,28,26 /* clear DR */
547 mtmsr r0
548 SYNC_601
549 isync
550 lis r9,mmu_hash_lock@h
551 ori r9,r9,mmu_hash_lock@l
552 tophys(r9,r9)
55310: lwarx r7,0,r9
554 cmpwi 0,r7,0
555 bne- 10b
556 stwcx. r8,0,r9
557 bne- 10b
558 eieio
559 tlbie r3
560 sync
561 TLBSYNC
562 li r0,0
563 stw r0,0(r9) /* clear mmu_hash_lock */
564 mtmsr r10
565 SYNC_601
566 isync
567#else /* CONFIG_SMP */
568 tlbie r3
569 sync
570#endif /* CONFIG_SMP */
571#endif /* ! CONFIG_40x */
572 blr
573
574/*
575 * Flush instruction cache.
576 * This is a no-op on the 601.
577 */
578_GLOBAL(flush_instruction_cache)
579#if defined(CONFIG_8xx)
580 isync
581 lis r5, IDC_INVALL@h
582 mtspr SPRN_IC_CST, r5
583#elif defined(CONFIG_4xx)
584#ifdef CONFIG_403GCX
585 li r3, 512
586 mtctr r3
587 lis r4, KERNELBASE@h
5881: iccci 0, r4
589 addi r4, r4, 16
590 bdnz 1b
591#else
592 lis r3, KERNELBASE@h
593 iccci 0,r3
594#endif
595#elif CONFIG_FSL_BOOKE
33d9e9b5
KG		 596BEGIN_FTR_SECTION
597 mfspr r3,SPRN_L1CSR0
598 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
599 /* msync; isync recommended here */
600 mtspr SPRN_L1CSR0,r3
601 isync
602 blr
603END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
1da177e4
LT		 604 mfspr r3,SPRN_L1CSR1
605 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
606 mtspr SPRN_L1CSR1,r3
607#else
608 mfspr r3,SPRN_PVR
609 rlwinm r3,r3,16,16,31
610 cmpwi 0,r3,1
611 beqlr /* for 601, do nothing */
612 /* 603/604 processor - use invalidate-all bit in HID0 */
613 mfspr r3,SPRN_HID0
614 ori r3,r3,HID0_ICFI
615 mtspr SPRN_HID0,r3
616#endif /* CONFIG_8xx/4xx */
617 isync
618 blr
619
620/*
621 * Write any modified data cache blocks out to memory
622 * and invalidate the corresponding instruction cache blocks.
623 * This is a no-op on the 601.
624 *
625 * flush_icache_range(unsigned long start, unsigned long stop)
626 */
627_GLOBAL(flush_icache_range)
628BEGIN_FTR_SECTION
629 blr /* for 601, do nothing */
4481e8ee 630END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
1da177e4
LT		 631 li r5,L1_CACHE_LINE_SIZE-1
632 andc r3,r3,r5
633 subf r4,r3,r4
634 add r4,r4,r5
635 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE
636 beqlr
637 mtctr r4
638 mr r6,r3
6391: dcbst 0,r3
640 addi r3,r3,L1_CACHE_LINE_SIZE
641 bdnz 1b
642 sync /* wait for dcbst's to get to ram */
643 mtctr r4
6442: icbi 0,r6
645 addi r6,r6,L1_CACHE_LINE_SIZE
646 bdnz 2b
647 sync /* additional sync needed on g4 */
648 isync
649 blr
650/*
651 * Write any modified data cache blocks out to memory.
652 * Does not invalidate the corresponding cache lines (especially for
653 * any corresponding instruction cache).
654 *
655 * clean_dcache_range(unsigned long start, unsigned long stop)
656 */
657_GLOBAL(clean_dcache_range)
658 li r5,L1_CACHE_LINE_SIZE-1
659 andc r3,r3,r5
660 subf r4,r3,r4
661 add r4,r4,r5
662 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE
663 beqlr
664 mtctr r4
665
6661: dcbst 0,r3
667 addi r3,r3,L1_CACHE_LINE_SIZE
668 bdnz 1b
669 sync /* wait for dcbst's to get to ram */
670 blr
671
672/*
673 * Write any modified data cache blocks out to memory and invalidate them.
674 * Does not invalidate the corresponding instruction cache blocks.
675 *
676 * flush_dcache_range(unsigned long start, unsigned long stop)
677 */
678_GLOBAL(flush_dcache_range)
679 li r5,L1_CACHE_LINE_SIZE-1
680 andc r3,r3,r5
681 subf r4,r3,r4
682 add r4,r4,r5
683 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE
684 beqlr
685 mtctr r4
686
6871: dcbf 0,r3
688 addi r3,r3,L1_CACHE_LINE_SIZE
689 bdnz 1b
690 sync /* wait for dcbst's to get to ram */
691 blr
692
693/*
694 * Like above, but invalidate the D-cache. This is used by the 8xx
695 * to invalidate the cache so the PPC core doesn't get stale data
696 * from the CPM (no cache snooping here :-).
697 *
698 * invalidate_dcache_range(unsigned long start, unsigned long stop)
699 */
700_GLOBAL(invalidate_dcache_range)
701 li r5,L1_CACHE_LINE_SIZE-1
702 andc r3,r3,r5
703 subf r4,r3,r4
704 add r4,r4,r5
705 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE
706 beqlr
707 mtctr r4
708
7091: dcbi 0,r3
710 addi r3,r3,L1_CACHE_LINE_SIZE
711 bdnz 1b
712 sync /* wait for dcbi's to get to ram */
713 blr
714
715#ifdef CONFIG_NOT_COHERENT_CACHE
716/*
717 * 40x cores have 8K or 16K dcache and 32 byte line size.
718 * 44x has a 32K dcache and 32 byte line size.
719 * 8xx has 1, 2, 4, 8K variants.
720 * For now, cover the worst case of the 44x.
721 * Must be called with external interrupts disabled.
722 */
723#define CACHE_NWAYS 64
724#define CACHE_NLINES 16
725
726_GLOBAL(flush_dcache_all)
727 li r4, (2 * CACHE_NWAYS * CACHE_NLINES)
728 mtctr r4
729 lis r5, KERNELBASE@h
7301: lwz r3, 0(r5) /* Load one word from every line */
731 addi r5, r5, L1_CACHE_LINE_SIZE
732 bdnz 1b
733 blr
734#endif /* CONFIG_NOT_COHERENT_CACHE */
735
736/*
737 * Flush a particular page from the data cache to RAM.
738 * Note: this is necessary because the instruction cache does *not*
739 * snoop from the data cache.
740 * This is a no-op on the 601 which has a unified cache.
741 *
742 * void __flush_dcache_icache(void *page)
743 */
744_GLOBAL(__flush_dcache_icache)
745BEGIN_FTR_SECTION
746 blr /* for 601, do nothing */
4481e8ee 747END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
1da177e4
LT		 748 rlwinm r3,r3,0,0,19 /* Get page base address */
749 li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */
750 mtctr r4
751 mr r6,r3
7520: dcbst 0,r3 /* Write line to ram */
753 addi r3,r3,L1_CACHE_LINE_SIZE
754 bdnz 0b
755 sync
756 mtctr r4
7571: icbi 0,r6
758 addi r6,r6,L1_CACHE_LINE_SIZE
759 bdnz 1b
760 sync
761 isync
762 blr
763
764/*
765 * Flush a particular page from the data cache to RAM, identified
766 * by its physical address. We turn off the MMU so we can just use
767 * the physical address (this may be a highmem page without a kernel
768 * mapping).
769 *
770 * void __flush_dcache_icache_phys(unsigned long physaddr)
771 */
772_GLOBAL(__flush_dcache_icache_phys)
773BEGIN_FTR_SECTION
774 blr /* for 601, do nothing */
4481e8ee 775END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
1da177e4
LT		 776 mfmsr r10
777 rlwinm r0,r10,0,28,26 /* clear DR */
778 mtmsr r0
779 isync
780 rlwinm r3,r3,0,0,19 /* Get page base address */
781 li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */
782 mtctr r4
783 mr r6,r3
7840: dcbst 0,r3 /* Write line to ram */
785 addi r3,r3,L1_CACHE_LINE_SIZE
786 bdnz 0b
787 sync
788 mtctr r4
7891: icbi 0,r6
790 addi r6,r6,L1_CACHE_LINE_SIZE
791 bdnz 1b
792 sync
793 mtmsr r10 /* restore DR */
794 isync
795 blr
796
797/*
798 * Clear pages using the dcbz instruction, which doesn't cause any
799 * memory traffic (except to write out any cache lines which get
800 * displaced). This only works on cacheable memory.
801 *
802 * void clear_pages(void *page, int order) ;
803 */
804_GLOBAL(clear_pages)
805 li r0,4096/L1_CACHE_LINE_SIZE
806 slw r0,r0,r4
807 mtctr r0
808#ifdef CONFIG_8xx
809 li r4, 0
8101: stw r4, 0(r3)
811 stw r4, 4(r3)
812 stw r4, 8(r3)
813 stw r4, 12(r3)
814#else
8151: dcbz 0,r3
816#endif
817 addi r3,r3,L1_CACHE_LINE_SIZE
818 bdnz 1b
819 blr
820
821/*
822 * Copy a whole page. We use the dcbz instruction on the destination
823 * to reduce memory traffic (it eliminates the unnecessary reads of
824 * the destination into cache). This requires that the destination
825 * is cacheable.
826 */
827#define COPY_16_BYTES \
828 lwz r6,4(r4); \
829 lwz r7,8(r4); \
830 lwz r8,12(r4); \
831 lwzu r9,16(r4); \
832 stw r6,4(r3); \
833 stw r7,8(r3); \
834 stw r8,12(r3); \
835 stwu r9,16(r3)
836
837_GLOBAL(copy_page)
838 addi r3,r3,-4
839 addi r4,r4,-4
840
841#ifdef CONFIG_8xx
842 /* don't use prefetch on 8xx */
843 li r0,4096/L1_CACHE_LINE_SIZE
844 mtctr r0
8451: COPY_16_BYTES
846 bdnz 1b
847 blr
848
849#else /* not 8xx, we can prefetch */
850 li r5,4
851
852#if MAX_COPY_PREFETCH > 1
853 li r0,MAX_COPY_PREFETCH
854 li r11,4
855 mtctr r0
85611: dcbt r11,r4
857 addi r11,r11,L1_CACHE_LINE_SIZE
858 bdnz 11b
859#else /* MAX_COPY_PREFETCH == 1 */
860 dcbt r5,r4
861 li r11,L1_CACHE_LINE_SIZE+4
862#endif /* MAX_COPY_PREFETCH */
863 li r0,4096/L1_CACHE_LINE_SIZE - MAX_COPY_PREFETCH
864 crclr 4*cr0+eq
8652:
866 mtctr r0
8671:
868 dcbt r11,r4
869 dcbz r5,r3
870 COPY_16_BYTES
871#if L1_CACHE_LINE_SIZE >= 32
872 COPY_16_BYTES
873#if L1_CACHE_LINE_SIZE >= 64
874 COPY_16_BYTES
875 COPY_16_BYTES
876#if L1_CACHE_LINE_SIZE >= 128
877 COPY_16_BYTES
878 COPY_16_BYTES
879 COPY_16_BYTES
880 COPY_16_BYTES
881#endif
882#endif
883#endif
884 bdnz 1b
885 beqlr
886 crnot 4*cr0+eq,4*cr0+eq
887 li r0,MAX_COPY_PREFETCH
888 li r11,4
889 b 2b
890#endif /* CONFIG_8xx */
891
892/*
893 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
894 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
895 */
896_GLOBAL(atomic_clear_mask)
89710: lwarx r5,0,r4
898 andc r5,r5,r3
899 PPC405_ERR77(0,r4)
900 stwcx. r5,0,r4
901 bne- 10b
902 blr
903_GLOBAL(atomic_set_mask)
90410: lwarx r5,0,r4
905 or r5,r5,r3
906 PPC405_ERR77(0,r4)
907 stwcx. r5,0,r4
908 bne- 10b
909 blr
910
911/*
912 * I/O string operations
913 *
914 * insb(port, buf, len)
915 * outsb(port, buf, len)
916 * insw(port, buf, len)
917 * outsw(port, buf, len)
918 * insl(port, buf, len)
919 * outsl(port, buf, len)
920 * insw_ns(port, buf, len)
921 * outsw_ns(port, buf, len)
922 * insl_ns(port, buf, len)
923 * outsl_ns(port, buf, len)
924 *
925 * The *_ns versions don't do byte-swapping.
926 */
927_GLOBAL(_insb)
928 cmpwi 0,r5,0
929 mtctr r5
930 subi r4,r4,1
931 blelr-
93200: lbz r5,0(r3)
933 eieio
934 stbu r5,1(r4)
935 bdnz 00b
936 blr
937
938_GLOBAL(_outsb)
939 cmpwi 0,r5,0
940 mtctr r5
941 subi r4,r4,1
942 blelr-
94300: lbzu r5,1(r4)
944 stb r5,0(r3)
945 eieio
946 bdnz 00b
947 blr
948
949_GLOBAL(_insw)
950 cmpwi 0,r5,0
951 mtctr r5
952 subi r4,r4,2
953 blelr-
95400: lhbrx r5,0,r3
955 eieio
956 sthu r5,2(r4)
957 bdnz 00b
958 blr
959
960_GLOBAL(_outsw)
961 cmpwi 0,r5,0
962 mtctr r5
963 subi r4,r4,2
964 blelr-
96500: lhzu r5,2(r4)
966 eieio
967 sthbrx r5,0,r3
968 bdnz 00b
969 blr
970
971_GLOBAL(_insl)
972 cmpwi 0,r5,0
973 mtctr r5
974 subi r4,r4,4
975 blelr-
97600: lwbrx r5,0,r3
977 eieio
978 stwu r5,4(r4)
979 bdnz 00b
980 blr
981
982_GLOBAL(_outsl)
983 cmpwi 0,r5,0
984 mtctr r5
985 subi r4,r4,4
986 blelr-
98700: lwzu r5,4(r4)
988 stwbrx r5,0,r3
989 eieio
990 bdnz 00b
991 blr
992
993_GLOBAL(__ide_mm_insw)
994_GLOBAL(_insw_ns)
995 cmpwi 0,r5,0
996 mtctr r5
997 subi r4,r4,2
998 blelr-
99900: lhz r5,0(r3)
1000 eieio
1001 sthu r5,2(r4)
1002 bdnz 00b
1003 blr
1004
1005_GLOBAL(__ide_mm_outsw)
1006_GLOBAL(_outsw_ns)
1007 cmpwi 0,r5,0
1008 mtctr r5
1009 subi r4,r4,2
1010 blelr-
101100: lhzu r5,2(r4)
1012 sth r5,0(r3)
1013 eieio
1014 bdnz 00b
1015 blr
1016
1017_GLOBAL(__ide_mm_insl)
1018_GLOBAL(_insl_ns)
1019 cmpwi 0,r5,0
1020 mtctr r5
1021 subi r4,r4,4
1022 blelr-
102300: lwz r5,0(r3)
1024 eieio
1025 stwu r5,4(r4)
1026 bdnz 00b
1027 blr
1028
1029_GLOBAL(__ide_mm_outsl)
1030_GLOBAL(_outsl_ns)
1031 cmpwi 0,r5,0
1032 mtctr r5
1033 subi r4,r4,4
1034 blelr-
103500: lwzu r5,4(r4)
1036 stw r5,0(r3)
1037 eieio
1038 bdnz 00b
1039 blr
1040
1041/*
1042 * Extended precision shifts.
1043 *
1044 * Updated to be valid for shift counts from 0 to 63 inclusive.
1045 * -- Gabriel
1046 *
1047 * R3/R4 has 64 bit value
1048 * R5 has shift count
1049 * result in R3/R4
1050 *
1051 * ashrdi3: arithmetic right shift (sign propagation)
1052 * lshrdi3: logical right shift
1053 * ashldi3: left shift
1054 */
1055_GLOBAL(__ashrdi3)
1056 subfic r6,r5,32
1057 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
1058 addi r7,r5,32 # could be xori, or addi with -32
1059 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
1060 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
1061 sraw r7,r3,r7 # t2 = MSW >> (count-32)
1062 or r4,r4,r6 # LSW |= t1
1063 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
1064 sraw r3,r3,r5 # MSW = MSW >> count
1065 or r4,r4,r7 # LSW |= t2
1066 blr
1067
1068_GLOBAL(__ashldi3)
1069 subfic r6,r5,32
1070 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
1071 addi r7,r5,32 # could be xori, or addi with -32
1072 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
1073 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
1074 or r3,r3,r6 # MSW |= t1
1075 slw r4,r4,r5 # LSW = LSW << count
1076 or r3,r3,r7 # MSW |= t2
1077 blr
1078
1079_GLOBAL(__lshrdi3)
1080 subfic r6,r5,32
1081 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
1082 addi r7,r5,32 # could be xori, or addi with -32
1083 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
1084 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
1085 or r4,r4,r6 # LSW |= t1
1086 srw r3,r3,r5 # MSW = MSW >> count
1087 or r4,r4,r7 # LSW |= t2
1088 blr
1089
1090_GLOBAL(abs)
1091 srawi r4,r3,31
1092 xor r3,r3,r4
1093 sub r3,r3,r4
1094 blr
1095
1096_GLOBAL(_get_SP)
1097 mr r3,r1 /* Close enough */
1098 blr
1099
1100/*
1101 * These are used in the alignment trap handler when emulating
1102 * single-precision loads and stores.
1103 * We restore and save the fpscr so the task gets the same result
1104 * and exceptions as if the cpu had performed the load or store.
1105 */
1106
443a848c 1107#ifdef CONFIG_PPC_FPU
1da177e4
LT		 1108_GLOBAL(cvt_fd)
1109 lfd 0,-4(r5) /* load up fpscr value */
1110 mtfsf 0xff,0
1111 lfs 0,0(r3)
1112 stfd 0,0(r4)
1113 mffs 0 /* save new fpscr value */
1114 stfd 0,-4(r5)
1115 blr
1116
1117_GLOBAL(cvt_df)
1118 lfd 0,-4(r5) /* load up fpscr value */
1119 mtfsf 0xff,0
1120 lfd 0,0(r3)
1121 stfs 0,0(r4)
1122 mffs 0 /* save new fpscr value */
1123 stfd 0,-4(r5)
1124 blr
1125#endif
1126
1127/*
1128 * Create a kernel thread
1129 * kernel_thread(fn, arg, flags)
1130 */
1131_GLOBAL(kernel_thread)
1132 stwu r1,-16(r1)
1133 stw r30,8(r1)
1134 stw r31,12(r1)
1135 mr r30,r3 /* function */
1136 mr r31,r4 /* argument */
1137 ori r3,r5,CLONE_VM /* flags */
1138 oris r3,r3,CLONE_UNTRACED>>16
1139 li r4,0 /* new sp (unused) */
1140 li r0,__NR_clone
1141 sc
1142 cmpwi 0,r3,0 /* parent or child? */
1143 bne 1f /* return if parent */
1144 li r0,0 /* make top-level stack frame */
1145 stwu r0,-16(r1)
1146 mtlr r30 /* fn addr in lr */
1147 mr r3,r31 /* load arg and call fn */
c9cf73ae 1148 PPC440EP_ERR42
1da177e4
LT		 1149 blrl
1150 li r0,__NR_exit /* exit if function returns */
1151 li r3,0
1152 sc
11531: lwz r30,8(r1)
1154 lwz r31,12(r1)
1155 addi r1,r1,16
1156 blr
1157
1158/*
1159 * This routine is just here to keep GCC happy - sigh...
1160 */
1161_GLOBAL(__main)
1162 blr
1163
1164#define SYSCALL(name) \
1165_GLOBAL(name) \
1166 li r0,__NR_##name; \
1167 sc; \
1168 bnslr; \
1169 lis r4,errno@ha; \
1170 stw r3,errno@l(r4); \
1171 li r3,-1; \
1172 blr
1173
1174SYSCALL(execve)
1175
1176/* Why isn't this a) automatic, b) written in 'C'? */
1177 .data
1178 .align 4
1179_GLOBAL(sys_call_table)
1180 .long sys_restart_syscall /* 0 */
1181 .long sys_exit
1182 .long ppc_fork
1183 .long sys_read
1184 .long sys_write
1185 .long sys_open /* 5 */
1186 .long sys_close
1187 .long sys_waitpid
1188 .long sys_creat
1189 .long sys_link
1190 .long sys_unlink /* 10 */
1191 .long sys_execve
1192 .long sys_chdir
1193 .long sys_time
1194 .long sys_mknod
1195 .long sys_chmod /* 15 */
1196 .long sys_lchown
1197 .long sys_ni_syscall /* old break syscall holder */
1198 .long sys_stat
1199 .long sys_lseek
1200 .long sys_getpid /* 20 */
1201 .long sys_mount
1202 .long sys_oldumount
1203 .long sys_setuid
1204 .long sys_getuid
1205 .long sys_stime /* 25 */
1206 .long sys_ptrace
1207 .long sys_alarm
1208 .long sys_fstat
1209 .long sys_pause
1210 .long sys_utime /* 30 */
1211 .long sys_ni_syscall /* old stty syscall holder */
1212 .long sys_ni_syscall /* old gtty syscall holder */
1213 .long sys_access
1214 .long sys_nice
1215 .long sys_ni_syscall /* 35 */ /* old ftime syscall holder */
1216 .long sys_sync
1217 .long sys_kill
1218 .long sys_rename
1219 .long sys_mkdir
1220 .long sys_rmdir /* 40 */
1221 .long sys_dup
1222 .long sys_pipe
1223 .long sys_times
1224 .long sys_ni_syscall /* old prof syscall holder */
1225 .long sys_brk /* 45 */
1226 .long sys_setgid
1227 .long sys_getgid
1228 .long sys_signal
1229 .long sys_geteuid
1230 .long sys_getegid /* 50 */
1231 .long sys_acct
1232 .long sys_umount /* recycled never used phys() */
1233 .long sys_ni_syscall /* old lock syscall holder */
1234 .long sys_ioctl
1235 .long sys_fcntl /* 55 */
1236 .long sys_ni_syscall /* old mpx syscall holder */
1237 .long sys_setpgid
1238 .long sys_ni_syscall /* old ulimit syscall holder */
1239 .long sys_olduname
1240 .long sys_umask /* 60 */
1241 .long sys_chroot
1242 .long sys_ustat
1243 .long sys_dup2
1244 .long sys_getppid
1245 .long sys_getpgrp /* 65 */
1246 .long sys_setsid
1247 .long sys_sigaction
1248 .long sys_sgetmask
1249 .long sys_ssetmask
1250 .long sys_setreuid /* 70 */
1251 .long sys_setregid
1252 .long ppc_sigsuspend
1253 .long sys_sigpending
1254 .long sys_sethostname
1255 .long sys_setrlimit /* 75 */
1256 .long sys_old_getrlimit
1257 .long sys_getrusage
1258 .long sys_gettimeofday
1259 .long sys_settimeofday
1260 .long sys_getgroups /* 80 */
1261 .long sys_setgroups
1262 .long ppc_select
1263 .long sys_symlink
1264 .long sys_lstat
1265 .long sys_readlink /* 85 */
1266 .long sys_uselib
1267 .long sys_swapon
1268 .long sys_reboot
1269 .long old_readdir
1270 .long sys_mmap /* 90 */
1271 .long sys_munmap
1272 .long sys_truncate
1273 .long sys_ftruncate
1274 .long sys_fchmod
1275 .long sys_fchown /* 95 */
1276 .long sys_getpriority
1277 .long sys_setpriority
1278 .long sys_ni_syscall /* old profil syscall holder */
1279 .long sys_statfs
1280 .long sys_fstatfs /* 100 */
1281 .long sys_ni_syscall
1282 .long sys_socketcall
1283 .long sys_syslog
1284 .long sys_setitimer
1285 .long sys_getitimer /* 105 */
1286 .long sys_newstat
1287 .long sys_newlstat
1288 .long sys_newfstat
1289 .long sys_uname
1290 .long sys_ni_syscall /* 110 */
1291 .long sys_vhangup
1292 .long sys_ni_syscall /* old 'idle' syscall */
1293 .long sys_ni_syscall
1294 .long sys_wait4
1295 .long sys_swapoff /* 115 */
1296 .long sys_sysinfo
1297 .long sys_ipc
1298 .long sys_fsync
1299 .long sys_sigreturn
1300 .long ppc_clone /* 120 */
1301 .long sys_setdomainname
1302 .long sys_newuname
1303 .long sys_ni_syscall
1304 .long sys_adjtimex
1305 .long sys_mprotect /* 125 */
1306 .long sys_sigprocmask
1307 .long sys_ni_syscall /* old sys_create_module */
1308 .long sys_init_module
1309 .long sys_delete_module
1310 .long sys_ni_syscall /* old sys_get_kernel_syms */ /* 130 */
1311 .long sys_quotactl
1312 .long sys_getpgid
1313 .long sys_fchdir
1314 .long sys_bdflush
1315 .long sys_sysfs /* 135 */
1316 .long sys_personality
1317 .long sys_ni_syscall /* for afs_syscall */
1318 .long sys_setfsuid
1319 .long sys_setfsgid
1320 .long sys_llseek /* 140 */
1321 .long sys_getdents
1322 .long ppc_select
1323 .long sys_flock
1324 .long sys_msync
1325 .long sys_readv /* 145 */
1326 .long sys_writev
1327 .long sys_getsid
1328 .long sys_fdatasync
1329 .long sys_sysctl
1330 .long sys_mlock /* 150 */
1331 .long sys_munlock
1332 .long sys_mlockall
1333 .long sys_munlockall
1334 .long sys_sched_setparam
1335 .long sys_sched_getparam /* 155 */
1336 .long sys_sched_setscheduler
1337 .long sys_sched_getscheduler
1338 .long sys_sched_yield
1339 .long sys_sched_get_priority_max
1340 .long sys_sched_get_priority_min /* 160 */
1341 .long sys_sched_rr_get_interval
1342 .long sys_nanosleep
1343 .long sys_mremap
1344 .long sys_setresuid
1345 .long sys_getresuid /* 165 */
1346 .long sys_ni_syscall /* old sys_query_module */
1347 .long sys_poll
1348 .long sys_nfsservctl
1349 .long sys_setresgid
1350 .long sys_getresgid /* 170 */
1351 .long sys_prctl
1352 .long sys_rt_sigreturn
1353 .long sys_rt_sigaction
1354 .long sys_rt_sigprocmask
1355 .long sys_rt_sigpending /* 175 */
1356 .long sys_rt_sigtimedwait
1357 .long sys_rt_sigqueueinfo
1358 .long ppc_rt_sigsuspend
1359 .long sys_pread64
1360 .long sys_pwrite64 /* 180 */
1361 .long sys_chown
1362 .long sys_getcwd
1363 .long sys_capget
1364 .long sys_capset
1365 .long sys_sigaltstack /* 185 */
1366 .long sys_sendfile
1367 .long sys_ni_syscall /* streams1 */
1368 .long sys_ni_syscall /* streams2 */
1369 .long ppc_vfork
1370 .long sys_getrlimit /* 190 */
1371 .long sys_readahead
1372 .long sys_mmap2
1373 .long sys_truncate64
1374 .long sys_ftruncate64
1375 .long sys_stat64 /* 195 */
1376 .long sys_lstat64
1377 .long sys_fstat64
1378 .long sys_pciconfig_read
1379 .long sys_pciconfig_write
1380 .long sys_pciconfig_iobase /* 200 */
1381 .long sys_ni_syscall /* 201 - reserved - MacOnLinux - new */
1382 .long sys_getdents64
1383 .long sys_pivot_root
1384 .long sys_fcntl64
1385 .long sys_madvise /* 205 */
1386 .long sys_mincore
1387 .long sys_gettid
1388 .long sys_tkill
1389 .long sys_setxattr
1390 .long sys_lsetxattr /* 210 */
1391 .long sys_fsetxattr
1392 .long sys_getxattr
1393 .long sys_lgetxattr
1394 .long sys_fgetxattr
1395 .long sys_listxattr /* 215 */
1396 .long sys_llistxattr
1397 .long sys_flistxattr
1398 .long sys_removexattr
1399 .long sys_lremovexattr
1400 .long sys_fremovexattr /* 220 */
1401 .long sys_futex
1402 .long sys_sched_setaffinity
1403 .long sys_sched_getaffinity
1404 .long sys_ni_syscall
1405 .long sys_ni_syscall /* 225 - reserved for Tux */
1406 .long sys_sendfile64
1407 .long sys_io_setup
1408 .long sys_io_destroy
1409 .long sys_io_getevents
1410 .long sys_io_submit /* 230 */
1411 .long sys_io_cancel
1412 .long sys_set_tid_address
1413 .long sys_fadvise64
1414 .long sys_exit_group
1415 .long sys_lookup_dcookie /* 235 */
1416 .long sys_epoll_create
1417 .long sys_epoll_ctl
1418 .long sys_epoll_wait
1419 .long sys_remap_file_pages
1420 .long sys_timer_create /* 240 */
1421 .long sys_timer_settime
1422 .long sys_timer_gettime
1423 .long sys_timer_getoverrun
1424 .long sys_timer_delete
1425 .long sys_clock_settime /* 245 */
1426 .long sys_clock_gettime
1427 .long sys_clock_getres
1428 .long sys_clock_nanosleep
1429 .long ppc_swapcontext
1430 .long sys_tgkill /* 250 */
1431 .long sys_utimes
1432 .long sys_statfs64
1433 .long sys_fstatfs64
1434 .long ppc_fadvise64_64
1435 .long sys_ni_syscall /* 255 - rtas (used on ppc64) */
1436 .long sys_debug_setcontext
1437 .long sys_ni_syscall /* 257 reserved for vserver */
1438 .long sys_ni_syscall /* 258 reserved for new sys_remap_file_pages */
1439 .long sys_ni_syscall /* 259 reserved for new sys_mbind */
1440 .long sys_ni_syscall /* 260 reserved for new sys_get_mempolicy */
1441 .long sys_ni_syscall /* 261 reserved for new sys_set_mempolicy */
1442 .long sys_mq_open
1443 .long sys_mq_unlink
1444 .long sys_mq_timedsend
1445 .long sys_mq_timedreceive /* 265 */
1446 .long sys_mq_notify
1447 .long sys_mq_getsetattr
70765aa4 1448 .long sys_kexec_load
1da177e4
LT		 1449 .long sys_add_key
1450 .long sys_request_key /* 270 */
1451 .long sys_keyctl
1452 .long sys_waitid
22e2c507
JA		 1453 .long sys_ioprio_set
1454 .long sys_ioprio_get
141d751e
RL		 1455 .long sys_inotify_init /* 275 */
1456 .long sys_inotify_add_watch
1457 .long sys_inotify_rm_watch
Linux kernel - Deliverables
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